drivers: gpio: Add GPIO support for mimx8ml8_m7 (NXP i.MX8M Plus SoC)
The current MCUX IGPIO driver assumes that the target SoC supports the DR_SET, DR_CLEAR, and DR_TOGGLE functionality, but some do not (namely, the M7 core of the i.MX8M Plus SoC). Current releases of the MCUXpresso SDK IGPIO driver contain utility functions to set, clear, and toggle pins which include provisions to support SoCs with and without DR_SET, DR_CLEAR, and DR_TOGGLE, and this change switches to using these utility functions. Additionally, this change enables GPIO support on the mimx8ml8_m7 target. Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
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9ac83be650
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f401be157f
7 changed files with 91 additions and 5 deletions
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@ -26,3 +26,7 @@
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status = "okay";
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current-speed = <115200>;
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};
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&gpio3 {
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status = "okay";
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};
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@ -26,3 +26,7 @@
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status = "okay";
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current-speed = <115200>;
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};
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&gpio3 {
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status = "okay";
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};
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@ -47,11 +47,11 @@ static int mcux_igpio_configure(const struct device *dev,
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}
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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base->DR_SET = BIT(pin);
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GPIO_WritePinOutput(base, pin, 1);
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}
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if (flags & GPIO_OUTPUT_INIT_LOW) {
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base->DR_CLEAR = BIT(pin);
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GPIO_WritePinOutput(base, pin, 0);
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}
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WRITE_BIT(base->GDIR, pin, flags & GPIO_OUTPUT);
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@ -87,7 +87,7 @@ static int mcux_igpio_port_set_bits_raw(const struct device *dev,
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const struct mcux_igpio_config *config = dev->config;
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GPIO_Type *base = config->base;
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base->DR_SET = mask;
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GPIO_PortSet(base, mask);
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return 0;
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}
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@ -98,7 +98,7 @@ static int mcux_igpio_port_clear_bits_raw(const struct device *dev,
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const struct mcux_igpio_config *config = dev->config;
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GPIO_Type *base = config->base;
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base->DR_CLEAR = mask;
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GPIO_PortClear(base, mask);
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return 0;
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}
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@ -109,7 +109,7 @@ static int mcux_igpio_port_toggle_bits(const struct device *dev,
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const struct mcux_igpio_config *config = dev->config;
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GPIO_Type *base = config->base;
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base->DR_TOGGLE = mask;
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GPIO_PortToggle(base, mask);
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return 0;
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}
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@ -87,6 +87,76 @@
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#clock-cells = <3>;
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};
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gpio1: gpio@30200000 {
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compatible = "nxp,imx-gpio";
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reg = <0x30200000 DT_SIZE_K(64)>;
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interrupts = <64 0>, <65 0>;
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rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M7_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "GPIO_1";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio2: gpio@30210000 {
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compatible = "nxp,imx-gpio";
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reg = <0x30210000 DT_SIZE_K(64)>;
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interrupts = <66 0>, <67 0>;
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rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M7_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "GPIO_2";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio3: gpio@30220000 {
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compatible = "nxp,imx-gpio";
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reg = <0x30220000 DT_SIZE_K(64)>;
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interrupts = <68 0>, <69 0>;
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rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M7_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "GPIO_3";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio4: gpio@30230000 {
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compatible = "nxp,imx-gpio";
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reg = <0x30230000 DT_SIZE_K(64)>;
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interrupts = <70 0>, <71 0>;
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rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M7_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "GPIO_4";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio5: gpio@30240000 {
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compatible = "nxp,imx-gpio";
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reg = <0x30240000 DT_SIZE_K(64)>;
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interrupts = <72 0>, <73 0>;
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rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M7_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "GPIO_5";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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/*
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* For now only UART4 is supported and
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* tested with the serial driver
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@ -27,6 +27,9 @@ config PINMUX_MCUX
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endif # PINMUX
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config GPIO
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default y
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if SERIAL
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config UART_MCUX_IUART
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@ -13,6 +13,10 @@ config NUM_IRQS
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# must be >= the highest interrupt number used
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default 159
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config GPIO_MCUX_IGPIO
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default y if HAS_MCUX_IGPIO
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depends on GPIO
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source "soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.mimx8ml8_m7"
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endif # SOC_SERIES_IMX8ML_M7
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@ -15,6 +15,7 @@ config SOC_MIMX8ML8
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select CPU_HAS_ARM_MPU
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select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
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select ARM_MPU
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select HAS_MCUX_IGPIO
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endchoice
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