ITE soc/riscv/riscv-ite/common/chipregs: add registers and IRQ num
Add registers and IRQ number for PD control. Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
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2 changed files with 12 additions and 2 deletions
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@ -124,6 +124,11 @@
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#define IT8XXX2_IRQ_WU124 145
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#define IT8XXX2_IRQ_WU125 146
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#define IT8XXX2_IRQ_WU126 147
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/* Group 20 */
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#define IT8XXX2_IRQ_USBPD0 165
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#define IT8XXX2_IRQ_USBPD1 166
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/* Group 21 */
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#define IT8XXX2_IRQ_USBPD2 174
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/* Group 22 */
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#define IT8XXX2_IRQ_WU40 176
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#define IT8XXX2_IRQ_WU45 177
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@ -1,4 +1,4 @@
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/*
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/*
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* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -672,6 +672,8 @@
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#define GPCRD5 ECREG(EC_REG_BASE_ADDR + 0x162D)
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#define GPCRE5 ECREG(EC_REG_BASE_ADDR + 0x1635)
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#define GPCRF3 ECREG(EC_REG_BASE_ADDR + 0x163B)
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#define GPCRF4 ECREG(EC_REG_BASE_ADDR + 0x163C)
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#define GPCRF5 ECREG(EC_REG_BASE_ADDR + 0x163D)
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#define GPCRH1 ECREG(EC_REG_BASE_ADDR + 0x1649)
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#define GPCRH2 ECREG(EC_REG_BASE_ADDR + 0x164A)
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#define GPCRI7 ECREG(EC_REG_BASE_ADDR + 0x1657)
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@ -1558,7 +1560,7 @@
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#define PECIHEN BIT(3)
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#define CONCTRL BIT(2)
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#define AWFCS_EN BIT(1)
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#define START BIT(0)
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#define PECISTART BIT(0)
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#define HOCMDR ECREG(EC_REG_BASE_ADDR + 0x2C02)
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#define HOTRADDR ECREG(EC_REG_BASE_ADDR + 0x2C03)
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#define HOWRLR ECREG(EC_REG_BASE_ADDR + 0x2C04)
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@ -1628,6 +1630,9 @@
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#define IT8XXX2_GPIO_GRC1 ECREG(IT8XXX2_GPIO_BASE + 0xF0)
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#define IT8XXX2_GPIO_GRC21 ECREG(IT8XXX2_GPIO_BASE + 0xE6)
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#define IT8XXX2_GPIO_GPCRP0 ECREG(IT8XXX2_GPIO2_BASE + 0x18)
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#define IT8XXX2_GPIO_GPCRP1 ECREG(IT8XXX2_GPIO2_BASE + 0x19)
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/* Analog to Digital Converter (ADC) */
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#ifndef __ASSEMBLER__
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