soc: nxp_kinetis: Convert to new DT_INST macros
Convert older DT_INST_ macro use the new include/devicetree.h DT_INST macro APIs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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d267ad1b22
5 changed files with 46 additions and 46 deletions
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@ -13,7 +13,7 @@
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#define DT_ADC_1_IRQ_PRI DT_NXP_KINETIS_ADC16_400BB000_IRQ_0_PRIORITY
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#define DT_ADC_1_NAME DT_NXP_KINETIS_ADC16_400BB000_LABEL
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#define DT_RTC_0_NAME DT_INST_0_NXP_KINETIS_RTC_LABEL
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#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, nxp_kinetis_rtc))
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#define DT_FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFE_40020000_BASE_ADDRESS
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#define DT_FLASH_DEV_NAME DT_NXP_KINETIS_FTFE_40020000_LABEL
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@ -17,7 +17,7 @@
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#define CONFIG_ENTROPY_NAME DT_NXP_KINETIS_TRNG_400A0000_LABEL
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#define DT_RTC_0_NAME DT_INST_0_NXP_KINETIS_RTC_LABEL
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#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, nxp_kinetis_rtc))
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#define DT_USBD_KINETIS_NAME DT_NXP_KINETIS_USBD_40072000_LABEL
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#define DT_USBD_KINETIS_IRQ DT_NXP_KINETIS_USBD_40072000_IRQ_USB_OTG
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@ -7,7 +7,7 @@
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_RTC_0_NAME DT_INST_0_NXP_KINETIS_RTC_LABEL
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#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, nxp_kinetis_rtc))
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#define DT_FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFE_40020000_BASE_ADDRESS
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#define DT_FLASH_DEV_NAME DT_NXP_KINETIS_FTFE_40020000_LABEL
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@ -28,53 +28,53 @@
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#define TO_ASYNC_CLK_DIV(val) _DO_CONCAT(kSCG_AsyncClkDivBy, val)
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/* System Clock configuration */
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ASSERT_WITHIN_RANGE(DT_INST_0_NXP_KINETIS_SCG_CLK_DIVIDER_SLOW, 2, 8,
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ASSERT_WITHIN_RANGE(DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_divider_slow), 2, 8,
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"Invalid SCG slow clock divider value");
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ASSERT_WITHIN_RANGE(DT_INST_0_NXP_KINETIS_SCG_CLK_DIVIDER_BUS, 1, 16,
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ASSERT_WITHIN_RANGE(DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_divider_bus), 1, 16,
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"Invalid SCG bus clock divider value");
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#if DT_INST_0_NXP_KINETIS_SCG_CLK_SOURCE == KINETIS_SCG_SCLK_SRC_SPLL
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#if DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_source) == KINETIS_SCG_SCLK_SRC_SPLL
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/* Core divider range is 1 to 4 with SPLL as clock source */
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ASSERT_WITHIN_RANGE(DT_INST_0_NXP_KINETIS_SCG_CLK_DIVIDER_CORE, 1, 4,
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ASSERT_WITHIN_RANGE(DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_divider_core), 1, 4,
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"Invalid SCG core clock divider value");
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#else
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ASSERT_WITHIN_RANGE(DT_INST_0_NXP_KINETIS_SCG_CLK_DIVIDER_CORE, 1, 16,
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ASSERT_WITHIN_RANGE(DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_divider_core), 1, 16,
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"Invalid SCG core clock divider value");
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#endif
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static const scg_sys_clk_config_t scg_sys_clk_config = {
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.divSlow = TO_SYS_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_CLK_DIVIDER_SLOW),
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.divBus = TO_SYS_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_CLK_DIVIDER_BUS),
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.divCore = TO_SYS_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_CLK_DIVIDER_CORE),
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.src = DT_INST_0_NXP_KINETIS_SCG_CLK_SOURCE
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.divSlow = TO_SYS_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_divider_slow)),
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.divBus = TO_SYS_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_divider_bus)),
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.divCore = TO_SYS_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_divider_core)),
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.src = DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_source)
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};
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#ifdef DT_INST_0_NXP_KINETIS_SCG_SOSC_FREQ
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#if DT_NODE_HAS_PROP(DT_INST(0, nxp_kinetis_scg), sosc_freq)
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/* System Oscillator (SOSC) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(DT_INST_0_NXP_KINETIS_SCG_SOSC_DIVIDER_1,
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ASSERT_ASYNC_CLK_DIV_VALID(DT_PROP(DT_INST(0, nxp_kinetis_scg), sosc_divider_1),
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"Invalid SCG SOSC divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(DT_INST_0_NXP_KINETIS_SCG_SOSC_DIVIDER_2,
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ASSERT_ASYNC_CLK_DIV_VALID(DT_PROP(DT_INST(0, nxp_kinetis_scg), sosc_divider_2),
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"Invalid SCG SOSC divider 2 value");
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static const scg_sosc_config_t scg_sosc_config = {
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.freq = DT_INST_0_NXP_KINETIS_SCG_SOSC_FREQ,
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.freq = DT_PROP(DT_INST(0, nxp_kinetis_scg), sosc_freq),
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.monitorMode = kSCG_SysOscMonitorDisable,
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.enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableInLowPower,
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.div1 = TO_ASYNC_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_SOSC_DIVIDER_1),
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.div2 = TO_ASYNC_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_SOSC_DIVIDER_2),
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.workMode = DT_INST_0_NXP_KINETIS_SCG_SOSC_MODE
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.div1 = TO_ASYNC_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), sosc_divider_1)),
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.div2 = TO_ASYNC_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), sosc_divider_2)),
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.workMode = DT_PROP(DT_INST(0, nxp_kinetis_scg), sosc_mode)
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};
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#endif /* DT_INST_0_NXP_KINETIS_SCG_SOSC_FREQ */
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#endif /* DT_NODE_HAS_PROP(DT_INST(0, nxp_kinetis_scg), sosc_freq) */
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/* Slow Internal Reference Clock (SIRC) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(DT_INST_0_NXP_KINETIS_SCG_SIRC_DIVIDER_1,
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ASSERT_ASYNC_CLK_DIV_VALID(DT_PROP(DT_INST(0, nxp_kinetis_scg), sirc_divider_1),
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"Invalid SCG SIRC divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(DT_INST_0_NXP_KINETIS_SCG_SIRC_DIVIDER_2,
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ASSERT_ASYNC_CLK_DIV_VALID(DT_PROP(DT_INST(0, nxp_kinetis_scg), sirc_divider_2),
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"Invalid SCG SIRC divider 2 value");
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static const scg_sirc_config_t scg_sirc_config = {
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.enableMode = kSCG_SircEnable,
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.div1 = TO_ASYNC_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_SIRC_DIVIDER_1),
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.div2 = TO_ASYNC_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_SIRC_DIVIDER_2),
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#if MHZ(2) == DT_INST_0_NXP_KINETIS_SCG_SIRC_RANGE
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.div1 = TO_ASYNC_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), sirc_divider_1)),
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.div2 = TO_ASYNC_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), sirc_divider_2)),
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#if MHZ(2) == DT_PROP(DT_INST(0, nxp_kinetis_scg), sirc_range)
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.range = kSCG_SircRangeLow
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#elif MHZ(8) == DT_INST_0_NXP_KINETIS_SCG_SIRC_RANGE
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#elif MHZ(8) == DT_PROP(DT_INST(0, nxp_kinetis_scg), sirc_range)
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.range = kSCG_SircRangeHigh
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#else
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#error Invalid SCG SIRC range
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@ -82,21 +82,21 @@ static const scg_sirc_config_t scg_sirc_config = {
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};
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/* Fast Internal Reference Clock (FIRC) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(DT_INST_0_NXP_KINETIS_SCG_FIRC_DIVIDER_1,
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ASSERT_ASYNC_CLK_DIV_VALID(DT_PROP(DT_INST(0, nxp_kinetis_scg), firc_divider_1),
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"Invalid SCG FIRC divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(DT_INST_0_NXP_KINETIS_SCG_FIRC_DIVIDER_2,
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ASSERT_ASYNC_CLK_DIV_VALID(DT_PROP(DT_INST(0, nxp_kinetis_scg), firc_divider_2),
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"Invalid SCG FIRC divider 2 value");
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static const scg_firc_config_t scg_firc_config = {
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.enableMode = kSCG_FircEnable,
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.div1 = TO_ASYNC_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_FIRC_DIVIDER_1),
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.div2 = TO_ASYNC_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_FIRC_DIVIDER_2),
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#if MHZ(48) == DT_INST_0_NXP_KINETIS_SCG_FIRC_RANGE
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.div1 = TO_ASYNC_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), firc_divider_1)),
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.div2 = TO_ASYNC_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), firc_divider_2)),
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#if MHZ(48) == DT_PROP(DT_INST(0, nxp_kinetis_scg), firc_range)
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.range = kSCG_FircRange48M,
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#elif MHZ(52) == DT_INST_0_NXP_KINETIS_SCG_FIRC_RANGE
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#elif MHZ(52) == DT_PROP(DT_INST(0, nxp_kinetis_scg), firc_range)
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.range = kSCG_FircRange52M,
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#elif MHZ(56) == DT_INST_0_NXP_KINETIS_SCG_FIRC_RANGE
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#elif MHZ(56) == DT_PROP(DT_INST(0, nxp_kinetis_scg), firc_range)
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.range = kSCG_FircRange56M,
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#elif MHZ(60) == DT_INST_0_NXP_KINETIS_SCG_FIRC_RANGE
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#elif MHZ(60) == DT_PROP(DT_INST(0, nxp_kinetis_scg), firc_range)
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.range = kSCG_FircRange60M,
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#else
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#error Invalid SCG FIRC range
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@ -105,28 +105,28 @@ static const scg_firc_config_t scg_firc_config = {
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};
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/* System Phase-Locked Loop (SPLL) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(DT_INST_0_NXP_KINETIS_SCG_SPLL_DIVIDER_1,
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ASSERT_ASYNC_CLK_DIV_VALID(DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_divider_1),
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"Invalid SCG SPLL divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(DT_INST_0_NXP_KINETIS_SCG_SPLL_DIVIDER_2,
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ASSERT_ASYNC_CLK_DIV_VALID(DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_divider_2),
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"Invalid SCG SPLL divider 2 value");
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ASSERT_WITHIN_RANGE(DT_INST_0_NXP_KINETIS_SCG_SPLL_DIVIDER_PRE, 1, 8,
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ASSERT_WITHIN_RANGE(DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_divider_pre), 1, 8,
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"Invalid SCG SPLL pre divider value");
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ASSERT_WITHIN_RANGE(DT_INST_0_NXP_KINETIS_SCG_SPLL_MULTIPLIER, 16, 47,
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ASSERT_WITHIN_RANGE(DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_multiplier), 16, 47,
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"Invalid SCG SPLL multiplier value");
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static const scg_spll_config_t scg_spll_config = {
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.enableMode = kSCG_SysPllEnable,
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.monitorMode = kSCG_SysPllMonitorDisable,
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.div1 = TO_ASYNC_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_SPLL_DIVIDER_1),
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.div2 = TO_ASYNC_CLK_DIV(DT_INST_0_NXP_KINETIS_SCG_SPLL_DIVIDER_2),
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#if DT_INST_0_NXP_KINETIS_SCG_SPLL_SOURCE == KINETIS_SCG_SPLL_SRC_SOSC
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.div1 = TO_ASYNC_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_divider_1)),
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.div2 = TO_ASYNC_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_divider_2)),
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#if DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_source) == KINETIS_SCG_SPLL_SRC_SOSC
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.src = kSCG_SysPllSrcSysOsc,
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#elif DT_INST_0_NXP_KINETIS_SCG_SPLL_SOURCE == KINETIS_SCG_SPLL_SRC_FIRC
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#elif DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_source) == KINETIS_SCG_SPLL_SRC_FIRC
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.src = kSCG_SysPllSrcFirc,
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#else
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#error Invalid SCG SPLL source
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#endif
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.prediv = (DT_INST_0_NXP_KINETIS_SCG_SPLL_DIVIDER_PRE - 1U),
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.mult = (DT_INST_0_NXP_KINETIS_SCG_SPLL_MULTIPLIER - 16U)
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.prediv = (DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_divider_pre) - 1U),
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.mult = (DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_multiplier) - 16U)
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};
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static ALWAYS_INLINE void clk_init(void)
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@ -139,7 +139,7 @@ static ALWAYS_INLINE void clk_init(void)
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};
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scg_sys_clk_config_t current;
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#ifdef DT_INST_0_NXP_KINETIS_SCG_SOSC_FREQ
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#if DT_NODE_HAS_PROP(DT_INST(0, nxp_kinetis_scg), sosc_freq)
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/* Optionally initialize system oscillator */
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CLOCK_InitSysOsc(&scg_sosc_config);
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CLOCK_SetXtal0Freq(scg_sosc_config.freq);
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@ -7,7 +7,7 @@
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#define DT_ADC_0_IRQ_PRI DT_NXP_KINETIS_ADC16_4003B000_IRQ_0_PRIORITY
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#define DT_ADC_0_NAME DT_NXP_KINETIS_ADC16_4003B000_LABEL
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#define DT_RTC_0_NAME DT_INST_0_NXP_KINETIS_RTC_LABEL
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#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, nxp_kinetis_rtc))
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#if defined(CONFIG_SOC_MKW22D5) || defined(CONFIG_SOC_MKW24D5)
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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