Microchip: MEC172x: ADC driver
Add ADC driver version 2 for MEC172x using new in-tree headers and device tree properties. Update the ADC shell for the new driver. Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit is contained in:
parent
b6bd40f5fa
commit
19dd46ef68
9 changed files with 418 additions and 1 deletions
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@ -63,3 +63,7 @@
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status = "okay";
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current-speed = <115200>;
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};
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&adc0 {
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status = "okay";
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};
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@ -15,3 +15,4 @@ CONFIG_PINMUX=y
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CONFIG_SERIAL=y
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_ADC=y
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@ -20,3 +20,4 @@ zephyr_library_sources_ifdef(CONFIG_ADC_NPCX adc_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE adc_handlers.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_CC32XX adc_cc32xx.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_EMUL adc_emul.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_XEC_V2 adc_mchp_xec_v2.c)
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@ -1,11 +1,19 @@
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# Microchip XEC ADC configuration
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# Copyright (c) 2019 Intel Corporation
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# Copyright (c) 2021 Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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config ADC_XEC
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bool "Microchip XEC series ADC driver"
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depends on SOC_FAMILY_MEC
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depends on SOC_SERIES_MEC1501X
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default y
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help
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Enable ADC driver for Microchip XEC MCU series.
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config ADC_XEC_V2
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bool "Microchip XEC series ADC V2 driver"
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depends on SOC_SERIES_MEC172X
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default y
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help
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Enable ADC driver for Microchip XEC MEC172x MCU series.
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348
drivers/adc/adc_mchp_xec_v2.c
Normal file
348
drivers/adc/adc_mchp_xec_v2.c
Normal file
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@ -0,0 +1,348 @@
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/*
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* Copyright (c) 2019 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_xec_adc_v2
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#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(adc_mchp_xec);
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#include <drivers/adc.h>
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#include <drivers/interrupt_controller/intc_mchp_xec_ecia.h>
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#include <soc.h>
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#include <errno.h>
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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#define XEC_ADC_VREF_ANALOG 3300
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/* ADC Control Register */
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#define XEC_ADC_CTRL_SINGLE_DONE_STATUS BIT(7)
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#define XEC_ADC_CTRL_REPEAT_DONE_STATUS BIT(6)
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#define XER_ADC_CTRL_SOFT_RESET BIT(4)
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#define XEC_ADC_CTRL_POWER_SAVER_DIS BIT(3)
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#define XEC_ADC_CTRL_START_REPEAT BIT(2)
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#define XEC_ADC_CTRL_START_SINGLE BIT(1)
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#define XEC_ADC_CTRL_ACTIVATE BIT(0)
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struct adc_xec_config {
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uintptr_t base_addr;
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uint8_t girq_single;
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uint8_t girq_single_pos;
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uint8_t girq_repeat;
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uint8_t girq_repeat_pos;
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uint8_t pcr_regidx;
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uint8_t pcr_bitpos;
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};
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struct adc_xec_data {
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struct adc_context ctx;
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uint16_t *buffer;
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uint16_t *repeat_buffer;
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};
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struct adc_xec_regs {
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uint32_t control_reg;
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uint32_t delay_reg;
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uint32_t status_reg;
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uint32_t single_reg;
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uint32_t repeat_reg;
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uint32_t channel_read_reg[8];
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uint32_t unused[18];
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uint32_t config_reg;
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uint32_t vref_channel_reg;
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uint32_t vref_control_reg;
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uint32_t sar_control_reg;
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};
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#define ADC_XEC_CONFIG(dev) \
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((struct adc_xec_config const *)(dev)->config)
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#define ADC_XEC_DATA(dev) \
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((struct adc_xec_data *const)(dev)->data)
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#define ADC_XEC_REG_BASE(dev) \
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((struct adc_xec_regs *)ADC_XEC_CONFIG(dev)->base_addr)
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#define ADC_XEC_0_REG_BASE \
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(struct adc_xec_regs *)(DT_INST_REG_ADDR(0))
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct adc_xec_data *data = CONTAINER_OF(ctx, struct adc_xec_data, ctx);
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struct adc_xec_regs *adc_regs = ADC_XEC_0_REG_BASE;
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data->repeat_buffer = data->buffer;
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adc_regs->single_reg = ctx->sequence.channels;
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adc_regs->control_reg |= XEC_ADC_CTRL_START_SINGLE;
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx,
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bool repeat_sampling)
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{
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struct adc_xec_data *data = CONTAINER_OF(ctx, struct adc_xec_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->repeat_buffer;
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}
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}
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static int adc_xec_channel_setup(const struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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struct adc_xec_regs *adc_regs = ADC_XEC_0_REG_BASE;
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uint32_t reg;
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ARG_UNUSED(dev);
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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return -EINVAL;
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}
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if (channel_cfg->channel_id >= MCHP_ADC_MAX_CHAN) {
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return -EINVAL;
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}
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if (channel_cfg->gain != ADC_GAIN_1) {
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return -EINVAL;
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}
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/* Setup VREF */
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reg = adc_regs->vref_channel_reg;
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reg &= ~MCHP_ADC_CH_VREF_SEL_MASK(channel_cfg->channel_id);
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if (channel_cfg->reference == ADC_REF_INTERNAL) {
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reg |= MCHP_ADC_CH_VREF_SEL_PAD(channel_cfg->channel_id);
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} else if (channel_cfg->reference == ADC_REF_EXTERNAL0) {
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reg |= MCHP_ADC_CH_VREF_SEL_GPIO(channel_cfg->channel_id);
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} else {
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return -EINVAL;
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}
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adc_regs->vref_channel_reg = reg;
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/* Differential mode? */
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reg = adc_regs->sar_control_reg;
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reg &= ~BIT(MCHP_ADC_SAR_CTRL_SELDIFF_POS);
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if (channel_cfg->differential != 0) {
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reg |= MCHP_ADC_SAR_CTRL_SELDIFF_EN;
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}
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adc_regs->sar_control_reg = reg;
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return 0;
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}
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static bool adc_xec_validate_buffer_size(const struct adc_sequence *sequence)
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{
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int chan_count = 0;
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size_t buff_need;
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uint32_t chan_mask;
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for (chan_mask = 0x80; chan_mask != 0; chan_mask >>= 1) {
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if (chan_mask & sequence->channels) {
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chan_count++;
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}
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}
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buff_need = chan_count * sizeof(uint16_t);
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if (sequence->options) {
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buff_need *= 1 + sequence->options->extra_samplings;
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}
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if (buff_need > sequence->buffer_size) {
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return false;
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}
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return true;
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}
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static int adc_xec_start_read(const struct device *dev,
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const struct adc_sequence *sequence)
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{
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struct adc_xec_regs *adc_regs = ADC_XEC_REG_BASE(dev);
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struct adc_xec_data *data = ADC_XEC_DATA(dev);
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uint32_t reg;
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if (sequence->channels & ~BIT_MASK(MCHP_ADC_MAX_CHAN)) {
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LOG_ERR("Incorrect channels, bitmask 0x%x", sequence->channels);
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return -EINVAL;
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}
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if (sequence->channels == 0UL) {
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LOG_ERR("No channel selected");
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return -EINVAL;
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}
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if (!adc_xec_validate_buffer_size(sequence)) {
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LOG_ERR("Incorrect buffer size");
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return -ENOMEM;
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}
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/* Setup ADC resolution */
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reg = adc_regs->sar_control_reg;
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reg &= ~(MCHP_ADC_SAR_CTRL_RES_MASK |
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(1 << MCHP_ADC_SAR_CTRL_SHIFTD_POS));
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if (sequence->resolution == 12) {
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reg |= MCHP_ADC_SAR_CTRL_RES_12_BITS;
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} else if (sequence->resolution == 10) {
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reg |= MCHP_ADC_SAR_CTRL_RES_10_BITS;
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reg |= MCHP_ADC_SAR_CTRL_SHIFTD_EN;
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} else {
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return -EINVAL;
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}
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adc_regs->sar_control_reg = reg;
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data->buffer = sequence->buffer;
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adc_context_start_read(&data->ctx, sequence);
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return adc_context_wait_for_completion(&data->ctx);
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}
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static int adc_xec_read(const struct device *dev,
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const struct adc_sequence *sequence)
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{
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struct adc_xec_data *data = ADC_XEC_DATA(dev);
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int error;
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adc_context_lock(&data->ctx, false, NULL);
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error = adc_xec_start_read(dev, sequence);
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adc_context_release(&data->ctx, error);
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return error;
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}
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#ifdef CONFIG_ADC_ASYNC
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static int adc_xec_read_async(const struct device *dev,
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const struct adc_sequence *sequence,
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struct k_poll_signal *async)
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{
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struct adc_xec_data *data = ADC_XEC_DATA(dev);
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int error;
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adc_context_lock(&data->ctx, true, async);
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error = adc_xec_start_read(dev, sequence);
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adc_context_release(&data->ctx, error);
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return error;
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}
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#endif /* CONFIG_ADC_ASYNC */
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static void xec_adc_get_sample(const struct device *dev)
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{
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struct adc_xec_regs *adc_regs = ADC_XEC_REG_BASE(dev);
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struct adc_xec_data *data = ADC_XEC_DATA(dev);
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uint32_t idx;
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uint32_t channels = adc_regs->status_reg;
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uint32_t ch_status = channels;
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uint32_t bit;
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/*
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* Using the enabled channel bit set, from
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* lowest channel number to highest, find out
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* which channel is enabled and copy the ADC
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* values from hardware registers to the data
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* buffer.
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*/
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bit = find_lsb_set(channels);
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while (bit != 0) {
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idx = bit - 1;
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*data->buffer = (uint16_t)adc_regs->channel_read_reg[idx];
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data->buffer++;
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channels &= ~BIT(idx);
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bit = find_lsb_set(channels);
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}
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/* Clear the status register */
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adc_regs->status_reg = ch_status;
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}
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static void adc_xec_isr(const struct device *dev)
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{
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const struct adc_xec_config *const cfg = ADC_XEC_CONFIG(dev);
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struct adc_xec_regs *adc_regs = ADC_XEC_REG_BASE(dev);
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struct adc_xec_data *data = ADC_XEC_DATA(dev);
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uint32_t reg;
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/* Clear START_SINGLE bit and clear SINGLE_DONE_STATUS */
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reg = adc_regs->control_reg;
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reg &= ~XEC_ADC_CTRL_START_SINGLE;
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reg |= XEC_ADC_CTRL_SINGLE_DONE_STATUS;
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adc_regs->control_reg = reg;
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/* Also clear GIRQ source status bit */
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mchp_xec_ecia_girq_src_clr(cfg->girq_single, cfg->girq_single_pos);
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xec_adc_get_sample(dev);
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adc_context_on_sampling_done(&data->ctx, dev);
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LOG_DBG("ADC ISR triggered.");
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}
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struct adc_driver_api adc_xec_api = {
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.channel_setup = adc_xec_channel_setup,
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.read = adc_xec_read,
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#if defined(CONFIG_ADC_ASYNC)
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.read_async = adc_xec_read_async,
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#endif
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.ref_internal = XEC_ADC_VREF_ANALOG,
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};
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static int adc_xec_init(const struct device *dev)
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{
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const struct adc_xec_config *const cfg = ADC_XEC_CONFIG(dev);
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struct adc_xec_regs *adc_regs = ADC_XEC_REG_BASE(dev);
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struct adc_xec_data *data = ADC_XEC_DATA(dev);
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adc_regs->control_reg = XEC_ADC_CTRL_ACTIVATE
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| XEC_ADC_CTRL_POWER_SAVER_DIS
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| XEC_ADC_CTRL_SINGLE_DONE_STATUS
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| XEC_ADC_CTRL_REPEAT_DONE_STATUS;
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mchp_xec_ecia_girq_src_dis(cfg->girq_single, cfg->girq_single_pos);
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mchp_xec_ecia_girq_src_dis(cfg->girq_repeat, cfg->girq_repeat_pos);
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mchp_xec_ecia_girq_src_clr(cfg->girq_single, cfg->girq_single_pos);
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mchp_xec_ecia_girq_src_clr(cfg->girq_repeat, cfg->girq_repeat_pos);
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mchp_xec_ecia_girq_src_en(cfg->girq_single, cfg->girq_single_pos);
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IRQ_CONNECT(DT_INST_IRQN(0),
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DT_INST_IRQ(0, priority),
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adc_xec_isr, DEVICE_DT_INST_GET(0), 0);
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irq_enable(DT_INST_IRQN(0));
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static struct adc_xec_config adc_xec_dev_cfg_0 = {
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.base_addr = (uintptr_t)(DT_INST_REG_ADDR(0)),
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.girq_single = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 0)),
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.girq_single_pos = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 1)),
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.girq_repeat = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 2)),
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.girq_repeat_pos = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 3)),
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.pcr_regidx = (uint8_t)(DT_INST_PROP_BY_IDX(0, pcrs, 0)),
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.pcr_bitpos = (uint8_t)(DT_INST_PROP_BY_IDX(0, pcrs, 1)),
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};
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static struct adc_xec_data adc_xec_dev_data_0 = {
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ADC_CONTEXT_INIT_TIMER(adc_xec_dev_data_0, ctx),
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ADC_CONTEXT_INIT_LOCK(adc_xec_dev_data_0, ctx),
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ADC_CONTEXT_INIT_SYNC(adc_xec_dev_data_0, ctx),
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};
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DEVICE_DT_INST_DEFINE(0, adc_xec_init, NULL,
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&adc_xec_dev_data_0, &adc_xec_dev_cfg_0,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&adc_xec_api);
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@ -19,6 +19,8 @@
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#define DT_DRV_COMPAT ite_it8xxx2_adc
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#elif DT_HAS_COMPAT_STATUS_OKAY(microchip_xec_adc)
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#define DT_DRV_COMPAT microchip_xec_adc
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#elif DT_HAS_COMPAT_STATUS_OKAY(microchip_xec_adc_v2)
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#define DT_DRV_COMPAT microchip_xec_adc_v2
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#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_adc)
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#define DT_DRV_COMPAT nordic_nrf_adc
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#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_saadc)
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@ -739,6 +739,7 @@
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status = "disabled";
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};
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adc0: adc@40007c00 {
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compatible = "microchip,xec-adc-v2";
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reg = <0x40007c00 0x90>;
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interrupts = <78 0>, <79 0>;
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girqs = <17 8>, <17 9>;
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48
dts/bindings/adc/microchip,xec-adc-v2.yaml
Normal file
48
dts/bindings/adc/microchip,xec-adc-v2.yaml
Normal file
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# Copyright (c) 2019, Intel Corporation
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# Copyright (c) 2021, Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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description: Microchip XEC ADC
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compatible: "microchip,xec-adc-v2"
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include: adc-controller.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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"#io-channel-cells":
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const: 1
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girqs:
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type: array
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required: true
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description: Array of pairs of GIRQ number and bit position
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pcrs:
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type: array
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required: true
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description: ADC PCR register index and bit position
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"#girq-cells":
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||||
type: int
|
||||
const: 2
|
||||
|
||||
"#pcr-cells":
|
||||
type: int
|
||||
const: 2
|
||||
|
||||
io-channel-cells:
|
||||
- input
|
||||
|
||||
girq-cells:
|
||||
- girqnum
|
||||
- bitpos
|
||||
|
||||
pcr-cells:
|
||||
- regidx
|
||||
- bitpos
|
|
@ -23,4 +23,8 @@ config PINMUX_XEC
|
|||
default y
|
||||
depends on PINMUX
|
||||
|
||||
config ADC_XEC_V2
|
||||
default y
|
||||
depends on ADC
|
||||
|
||||
endif # SOC_MEC172X_NSZ
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue