Microchip: MEC172x: ADC driver

Add ADC driver version 2 for MEC172x using new in-tree headers
and device tree properties. Update the ADC shell for the new driver.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit is contained in:
Scott Worley 2021-08-10 16:02:15 -04:00 committed by Christopher Friedt
commit 19dd46ef68
9 changed files with 418 additions and 1 deletions

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@ -63,3 +63,7 @@
status = "okay";
current-speed = <115200>;
};
&adc0 {
status = "okay";
};

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@ -15,3 +15,4 @@ CONFIG_PINMUX=y
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_ADC=y

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@ -20,3 +20,4 @@ zephyr_library_sources_ifdef(CONFIG_ADC_NPCX adc_npcx.c)
zephyr_library_sources_ifdef(CONFIG_USERSPACE adc_handlers.c)
zephyr_library_sources_ifdef(CONFIG_ADC_CC32XX adc_cc32xx.c)
zephyr_library_sources_ifdef(CONFIG_ADC_EMUL adc_emul.c)
zephyr_library_sources_ifdef(CONFIG_ADC_XEC_V2 adc_mchp_xec_v2.c)

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@ -1,11 +1,19 @@
# Microchip XEC ADC configuration
# Copyright (c) 2019 Intel Corporation
# Copyright (c) 2021 Microchip Technology Inc.
# SPDX-License-Identifier: Apache-2.0
config ADC_XEC
bool "Microchip XEC series ADC driver"
depends on SOC_FAMILY_MEC
depends on SOC_SERIES_MEC1501X
default y
help
Enable ADC driver for Microchip XEC MCU series.
config ADC_XEC_V2
bool "Microchip XEC series ADC V2 driver"
depends on SOC_SERIES_MEC172X
default y
help
Enable ADC driver for Microchip XEC MEC172x MCU series.

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@ -0,0 +1,348 @@
/*
* Copyright (c) 2019 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT microchip_xec_adc_v2
#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
#include <logging/log.h>
LOG_MODULE_REGISTER(adc_mchp_xec);
#include <drivers/adc.h>
#include <drivers/interrupt_controller/intc_mchp_xec_ecia.h>
#include <soc.h>
#include <errno.h>
#define ADC_CONTEXT_USES_KERNEL_TIMER
#include "adc_context.h"
#define XEC_ADC_VREF_ANALOG 3300
/* ADC Control Register */
#define XEC_ADC_CTRL_SINGLE_DONE_STATUS BIT(7)
#define XEC_ADC_CTRL_REPEAT_DONE_STATUS BIT(6)
#define XER_ADC_CTRL_SOFT_RESET BIT(4)
#define XEC_ADC_CTRL_POWER_SAVER_DIS BIT(3)
#define XEC_ADC_CTRL_START_REPEAT BIT(2)
#define XEC_ADC_CTRL_START_SINGLE BIT(1)
#define XEC_ADC_CTRL_ACTIVATE BIT(0)
struct adc_xec_config {
uintptr_t base_addr;
uint8_t girq_single;
uint8_t girq_single_pos;
uint8_t girq_repeat;
uint8_t girq_repeat_pos;
uint8_t pcr_regidx;
uint8_t pcr_bitpos;
};
struct adc_xec_data {
struct adc_context ctx;
uint16_t *buffer;
uint16_t *repeat_buffer;
};
struct adc_xec_regs {
uint32_t control_reg;
uint32_t delay_reg;
uint32_t status_reg;
uint32_t single_reg;
uint32_t repeat_reg;
uint32_t channel_read_reg[8];
uint32_t unused[18];
uint32_t config_reg;
uint32_t vref_channel_reg;
uint32_t vref_control_reg;
uint32_t sar_control_reg;
};
#define ADC_XEC_CONFIG(dev) \
((struct adc_xec_config const *)(dev)->config)
#define ADC_XEC_DATA(dev) \
((struct adc_xec_data *const)(dev)->data)
#define ADC_XEC_REG_BASE(dev) \
((struct adc_xec_regs *)ADC_XEC_CONFIG(dev)->base_addr)
#define ADC_XEC_0_REG_BASE \
(struct adc_xec_regs *)(DT_INST_REG_ADDR(0))
static void adc_context_start_sampling(struct adc_context *ctx)
{
struct adc_xec_data *data = CONTAINER_OF(ctx, struct adc_xec_data, ctx);
struct adc_xec_regs *adc_regs = ADC_XEC_0_REG_BASE;
data->repeat_buffer = data->buffer;
adc_regs->single_reg = ctx->sequence.channels;
adc_regs->control_reg |= XEC_ADC_CTRL_START_SINGLE;
}
static void adc_context_update_buffer_pointer(struct adc_context *ctx,
bool repeat_sampling)
{
struct adc_xec_data *data = CONTAINER_OF(ctx, struct adc_xec_data, ctx);
if (repeat_sampling) {
data->buffer = data->repeat_buffer;
}
}
static int adc_xec_channel_setup(const struct device *dev,
const struct adc_channel_cfg *channel_cfg)
{
struct adc_xec_regs *adc_regs = ADC_XEC_0_REG_BASE;
uint32_t reg;
ARG_UNUSED(dev);
if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
return -EINVAL;
}
if (channel_cfg->channel_id >= MCHP_ADC_MAX_CHAN) {
return -EINVAL;
}
if (channel_cfg->gain != ADC_GAIN_1) {
return -EINVAL;
}
/* Setup VREF */
reg = adc_regs->vref_channel_reg;
reg &= ~MCHP_ADC_CH_VREF_SEL_MASK(channel_cfg->channel_id);
if (channel_cfg->reference == ADC_REF_INTERNAL) {
reg |= MCHP_ADC_CH_VREF_SEL_PAD(channel_cfg->channel_id);
} else if (channel_cfg->reference == ADC_REF_EXTERNAL0) {
reg |= MCHP_ADC_CH_VREF_SEL_GPIO(channel_cfg->channel_id);
} else {
return -EINVAL;
}
adc_regs->vref_channel_reg = reg;
/* Differential mode? */
reg = adc_regs->sar_control_reg;
reg &= ~BIT(MCHP_ADC_SAR_CTRL_SELDIFF_POS);
if (channel_cfg->differential != 0) {
reg |= MCHP_ADC_SAR_CTRL_SELDIFF_EN;
}
adc_regs->sar_control_reg = reg;
return 0;
}
static bool adc_xec_validate_buffer_size(const struct adc_sequence *sequence)
{
int chan_count = 0;
size_t buff_need;
uint32_t chan_mask;
for (chan_mask = 0x80; chan_mask != 0; chan_mask >>= 1) {
if (chan_mask & sequence->channels) {
chan_count++;
}
}
buff_need = chan_count * sizeof(uint16_t);
if (sequence->options) {
buff_need *= 1 + sequence->options->extra_samplings;
}
if (buff_need > sequence->buffer_size) {
return false;
}
return true;
}
static int adc_xec_start_read(const struct device *dev,
const struct adc_sequence *sequence)
{
struct adc_xec_regs *adc_regs = ADC_XEC_REG_BASE(dev);
struct adc_xec_data *data = ADC_XEC_DATA(dev);
uint32_t reg;
if (sequence->channels & ~BIT_MASK(MCHP_ADC_MAX_CHAN)) {
LOG_ERR("Incorrect channels, bitmask 0x%x", sequence->channels);
return -EINVAL;
}
if (sequence->channels == 0UL) {
LOG_ERR("No channel selected");
return -EINVAL;
}
if (!adc_xec_validate_buffer_size(sequence)) {
LOG_ERR("Incorrect buffer size");
return -ENOMEM;
}
/* Setup ADC resolution */
reg = adc_regs->sar_control_reg;
reg &= ~(MCHP_ADC_SAR_CTRL_RES_MASK |
(1 << MCHP_ADC_SAR_CTRL_SHIFTD_POS));
if (sequence->resolution == 12) {
reg |= MCHP_ADC_SAR_CTRL_RES_12_BITS;
} else if (sequence->resolution == 10) {
reg |= MCHP_ADC_SAR_CTRL_RES_10_BITS;
reg |= MCHP_ADC_SAR_CTRL_SHIFTD_EN;
} else {
return -EINVAL;
}
adc_regs->sar_control_reg = reg;
data->buffer = sequence->buffer;
adc_context_start_read(&data->ctx, sequence);
return adc_context_wait_for_completion(&data->ctx);
}
static int adc_xec_read(const struct device *dev,
const struct adc_sequence *sequence)
{
struct adc_xec_data *data = ADC_XEC_DATA(dev);
int error;
adc_context_lock(&data->ctx, false, NULL);
error = adc_xec_start_read(dev, sequence);
adc_context_release(&data->ctx, error);
return error;
}
#ifdef CONFIG_ADC_ASYNC
static int adc_xec_read_async(const struct device *dev,
const struct adc_sequence *sequence,
struct k_poll_signal *async)
{
struct adc_xec_data *data = ADC_XEC_DATA(dev);
int error;
adc_context_lock(&data->ctx, true, async);
error = adc_xec_start_read(dev, sequence);
adc_context_release(&data->ctx, error);
return error;
}
#endif /* CONFIG_ADC_ASYNC */
static void xec_adc_get_sample(const struct device *dev)
{
struct adc_xec_regs *adc_regs = ADC_XEC_REG_BASE(dev);
struct adc_xec_data *data = ADC_XEC_DATA(dev);
uint32_t idx;
uint32_t channels = adc_regs->status_reg;
uint32_t ch_status = channels;
uint32_t bit;
/*
* Using the enabled channel bit set, from
* lowest channel number to highest, find out
* which channel is enabled and copy the ADC
* values from hardware registers to the data
* buffer.
*/
bit = find_lsb_set(channels);
while (bit != 0) {
idx = bit - 1;
*data->buffer = (uint16_t)adc_regs->channel_read_reg[idx];
data->buffer++;
channels &= ~BIT(idx);
bit = find_lsb_set(channels);
}
/* Clear the status register */
adc_regs->status_reg = ch_status;
}
static void adc_xec_isr(const struct device *dev)
{
const struct adc_xec_config *const cfg = ADC_XEC_CONFIG(dev);
struct adc_xec_regs *adc_regs = ADC_XEC_REG_BASE(dev);
struct adc_xec_data *data = ADC_XEC_DATA(dev);
uint32_t reg;
/* Clear START_SINGLE bit and clear SINGLE_DONE_STATUS */
reg = adc_regs->control_reg;
reg &= ~XEC_ADC_CTRL_START_SINGLE;
reg |= XEC_ADC_CTRL_SINGLE_DONE_STATUS;
adc_regs->control_reg = reg;
/* Also clear GIRQ source status bit */
mchp_xec_ecia_girq_src_clr(cfg->girq_single, cfg->girq_single_pos);
xec_adc_get_sample(dev);
adc_context_on_sampling_done(&data->ctx, dev);
LOG_DBG("ADC ISR triggered.");
}
struct adc_driver_api adc_xec_api = {
.channel_setup = adc_xec_channel_setup,
.read = adc_xec_read,
#if defined(CONFIG_ADC_ASYNC)
.read_async = adc_xec_read_async,
#endif
.ref_internal = XEC_ADC_VREF_ANALOG,
};
static int adc_xec_init(const struct device *dev)
{
const struct adc_xec_config *const cfg = ADC_XEC_CONFIG(dev);
struct adc_xec_regs *adc_regs = ADC_XEC_REG_BASE(dev);
struct adc_xec_data *data = ADC_XEC_DATA(dev);
adc_regs->control_reg = XEC_ADC_CTRL_ACTIVATE
| XEC_ADC_CTRL_POWER_SAVER_DIS
| XEC_ADC_CTRL_SINGLE_DONE_STATUS
| XEC_ADC_CTRL_REPEAT_DONE_STATUS;
mchp_xec_ecia_girq_src_dis(cfg->girq_single, cfg->girq_single_pos);
mchp_xec_ecia_girq_src_dis(cfg->girq_repeat, cfg->girq_repeat_pos);
mchp_xec_ecia_girq_src_clr(cfg->girq_single, cfg->girq_single_pos);
mchp_xec_ecia_girq_src_clr(cfg->girq_repeat, cfg->girq_repeat_pos);
mchp_xec_ecia_girq_src_en(cfg->girq_single, cfg->girq_single_pos);
IRQ_CONNECT(DT_INST_IRQN(0),
DT_INST_IRQ(0, priority),
adc_xec_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
adc_context_unlock_unconditionally(&data->ctx);
return 0;
}
static struct adc_xec_config adc_xec_dev_cfg_0 = {
.base_addr = (uintptr_t)(DT_INST_REG_ADDR(0)),
.girq_single = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 0)),
.girq_single_pos = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 1)),
.girq_repeat = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 2)),
.girq_repeat_pos = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 3)),
.pcr_regidx = (uint8_t)(DT_INST_PROP_BY_IDX(0, pcrs, 0)),
.pcr_bitpos = (uint8_t)(DT_INST_PROP_BY_IDX(0, pcrs, 1)),
};
static struct adc_xec_data adc_xec_dev_data_0 = {
ADC_CONTEXT_INIT_TIMER(adc_xec_dev_data_0, ctx),
ADC_CONTEXT_INIT_LOCK(adc_xec_dev_data_0, ctx),
ADC_CONTEXT_INIT_SYNC(adc_xec_dev_data_0, ctx),
};
DEVICE_DT_INST_DEFINE(0, adc_xec_init, NULL,
&adc_xec_dev_data_0, &adc_xec_dev_cfg_0,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&adc_xec_api);

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@ -19,6 +19,8 @@
#define DT_DRV_COMPAT ite_it8xxx2_adc
#elif DT_HAS_COMPAT_STATUS_OKAY(microchip_xec_adc)
#define DT_DRV_COMPAT microchip_xec_adc
#elif DT_HAS_COMPAT_STATUS_OKAY(microchip_xec_adc_v2)
#define DT_DRV_COMPAT microchip_xec_adc_v2
#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_adc)
#define DT_DRV_COMPAT nordic_nrf_adc
#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_saadc)

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@ -739,6 +739,7 @@
status = "disabled";
};
adc0: adc@40007c00 {
compatible = "microchip,xec-adc-v2";
reg = <0x40007c00 0x90>;
interrupts = <78 0>, <79 0>;
girqs = <17 8>, <17 9>;

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@ -0,0 +1,48 @@
# Copyright (c) 2019, Intel Corporation
# Copyright (c) 2021, Microchip Technology Inc.
# SPDX-License-Identifier: Apache-2.0
description: Microchip XEC ADC
compatible: "microchip,xec-adc-v2"
include: adc-controller.yaml
properties:
reg:
required: true
interrupts:
required: true
"#io-channel-cells":
const: 1
girqs:
type: array
required: true
description: Array of pairs of GIRQ number and bit position
pcrs:
type: array
required: true
description: ADC PCR register index and bit position
"#girq-cells":
type: int
const: 2
"#pcr-cells":
type: int
const: 2
io-channel-cells:
- input
girq-cells:
- girqnum
- bitpos
pcr-cells:
- regidx
- bitpos

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@ -23,4 +23,8 @@ config PINMUX_XEC
default y
depends on PINMUX
config ADC_XEC_V2
default y
depends on ADC
endif # SOC_MEC172X_NSZ