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dts: it8xxx2: change flash size to 1M byte

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Flash size of IT8xxx2 is 1M byte.

Change-Id: Ic1464b6e36f16291f14024a6fb49acbf3a243176
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit is contained in:
Dino Li 2021-03-22 19:10:56 +08:00 • committed by Maureen Helm
commit ee39291553
3 changed files with 20 additions and 5 deletions
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10
dts/riscv/it8xxx2.dtsi
View file

@ -37,18 +37,18 @@
flash0: flash@80000000 {
compatible = "soc-nv-flash";
reg = <0x80000000 DT_SIZE_K(512)>;
erase-block-size = <1024>;
write-block-size = <1>;
reg = <0x80000000 DT_SIZE_M(1)>;
erase-block-size = <4096>;
write-block-size = <4>;
};
};
pinmux: pinmux@f016f0 {
compatible = "ite,it8xxx2-pinmux";
reg = <0x00f016f0 0x0010>;
};
sram0: memory@80080000 {
sram0: memory@80100000 {
compatible = "mmio-sram";
reg = <0x80080000 DT_SIZE_K(60)>;
reg = <0x80100000 DT_SIZE_K(60)>;
};
intc: interrupt-controller@f03f00 {
#interrupt-cells = <2>;

4
soc/riscv/riscv-ite/common/chip_chipregs.h
View file

@ -292,6 +292,10 @@
#define SEMBARH ECREG(EC_REG_BASE_ADDR + 0x109E)
#define SCRATH_SRAM 0x08
/* --- General Control (GCTRL) --- */
#define IT8XXX2_GCTRL_BASE 0x00F02000
#define IT8XXX2_GCTRL_EIDSR ECREG(IT8XXX2_GCTRL_BASE + 0x31)
/**
*
* (11xxh) Interrupt controller (INTC)

11
soc/riscv/riscv-ite/common/vector.S
View file

@ -5,6 +5,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "chip_chipregs.h"
#include <toolchain.h>
/* exports */
@ -25,6 +26,16 @@ SECTION_FUNC(vectors, __start)
csrw mtvec, t0
csrwi mie, 0
/*
* bit[3-0]@EIDSR=8: instruction local memory size is 1M byte
* This operation must be done before accessing memory.
*/
la t0, IT8XXX2_GCTRL_EIDSR
lb t1, 0(t0)
andi t1, t1, 0xf0
ori t1, t1, 0x8
sb t1, 0(t0)
/* Jump to __initialize */
tail __initialize