soc: arm: Introduce gigadevice soc

Add gigadevice soc initial version.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>

modules/hal_gigadevice/CMakeLists.txt

@@ -5,6 +5,11 @@ if(CONFIG_HAS_GD32_HAL)
 
 zephyr_library_named(hal_gigadevice)
 
+if(CONFIG_SOC_SERIES_GD32F403)
+  set(gd32_soc_uc GD32F403)
+  set(gd32_soc_lc gd32f403)
+endif()
+
 zephyr_library_compile_definitions(${gd32_soc_uc})
 
 set(gd32_soc_dir     ${ZEPHYR_HAL_GIGADEVICE_MODULE_DIR}/${gd32_soc_uc})

modules/hal_gigadevice/Kconfig

@@ -6,6 +6,7 @@ config ZEPHYR_HAL_GIGADEVICE_MODULE
 
 config HAS_GD32_HAL
 	bool
+	select HAS_CMSIS_CORE if SOC_FAMILY_GD32_ARM
 
 if HAS_GD32_HAL
 

soc/arm/gigadevice/CMakeLists.txt

@@ -0,0 +1,4 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${SOC_SERIES})

soc/arm/gigadevice/Kconfig

@@ -0,0 +1,22 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_GD32
+	bool
+	select HAS_GD32_HAL
+	select BUILD_OUTPUT_HEX
+
+config SOC_FAMILY
+	string
+	default "gigadevice"
+	depends on SOC_FAMILY_GD32
+
+config SOC_FAMILY_GD32_ARM
+	bool
+	select SOC_FAMILY_GD32
+
+if SOC_FAMILY_GD32_ARM
+
+source "soc/arm/gigadevice/*/Kconfig.soc"
+
+endif # SOC_FAMILY_GD32_ARM

soc/arm/gigadevice/Kconfig.defconfig

@@ -0,0 +1,4 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/arm/gigadevice/*/Kconfig.defconfig.series"

soc/arm/gigadevice/Kconfig.soc

@@ -0,0 +1,4 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/arm/gigadevice/*/Kconfig.series"

soc/arm/gigadevice/gd32f4/CMakeLists.txt

@@ -0,0 +1,5 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+zephyr_sources(soc.c)

soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f403

@@ -0,0 +1,21 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_GD32F403R || SOC_GD32F403V || SOC_GD32F403Z
+
+config SOC
+	default	"gd32f403r" if SOC_GD32F403R
+	default	"gd32f403v" if SOC_GD32F403V
+	default	"gd32f403z" if SOC_GD32F403Z
+
+config SOC_SERIES_GD32F403
+	bool
+	default y
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 168000000
+
+config NUM_IRQS
+	default 68
+
+endif

soc/arm/gigadevice/gd32f4/Kconfig.defconfig.series

@@ -0,0 +1,11 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_GD32F4
+
+source "soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f4*"
+
+config SOC_SERIES
+	default "gd32f4"
+
+endif   # SOC_SERIES_GD32F4

soc/arm/gigadevice/gd32f4/Kconfig.series

@@ -0,0 +1,14 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_GD32F4
+	bool "GigaDevice GD32F4xxx series Cortex-M4F MCU"
+	select ARM
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_VTOR
+	select SOC_FAMILY_GD32_ARM
+	help
+	  Enable support for GigaDevice GD32F4xxx MCU series

soc/arm/gigadevice/gd32f4/Kconfig.soc

@@ -0,0 +1,17 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "GigaDevice GD32F4xx MCU Selection"
+	depends on SOC_SERIES_GD32F4
+
+	config SOC_GD32F403R
+		bool "gd32f403r"
+
+	config SOC_GD32F403V
+		bool "gd32f403v"
+
+	config SOC_GD32F403Z
+		bool "gd32f403z"
+
+endchoice

soc/arm/gigadevice/gd32f4/linker.ld

@@ -0,0 +1,9 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/gigadevice/gd32f4/soc.c

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2021, ATL Electronics
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief GD32 MCU series initialization code
+ *
+ * This module provides routines to initialize and support board-level
+ * hardware for the GigaDevice GD32 SoC.
+ */
+
+#include <device.h>
+#include <init.h>
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int gigadevice_gd32_soc_init(const struct device *arg)
+{
+	uint32_t key;
+
+	ARG_UNUSED(arg);
+
+	key = irq_lock();
+
+	SystemInit();
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	return 0;
+}
+
+SYS_INIT(gigadevice_gd32_soc_init, PRE_KERNEL_1, 0);

soc/arm/gigadevice/gd32f4/soc.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2021, ATL Electronics
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Board configuration macros
+ *
+ * This header file is used to specify and describe board-level aspects
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+#include <sys/util.h>
+
+#ifndef _ASMLANGUAGE
+
+/* Add include for DTS generated information */
+#include <devicetree.h>
+
+#if defined(CONFIG_SOC_SERIES_GD32F403)
+#include <gd32f403.h>
+#else
+#error Library does not support the specified device.
+#endif
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _SOC__H_ */