soc: remove DT_WDT_0_NAME, DT_WDT_1_NAME
There are no more in-tree users of these fixup macros. Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This commit is contained in:
parent
1de7602c7d
commit
f3b4d8a86f
24 changed files with 0 additions and 51 deletions
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@ -66,8 +66,6 @@
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#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, microchip_xec_timer))
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, microchip_xec_watchdog))
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#define DT_KSCAN_0_NAME DT_LABEL(DT_INST(0, microchip_xec_kscan))
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#define DT_SPI_XEC_QMSPI_0_LABEL \
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@ -13,8 +13,6 @@
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#define DT_SPI_0_NAME DT_NORDIC_NRF_SPI_SPI_0_LABEL
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#define DT_SPI_1_NAME DT_NORDIC_NRF_SPI_SPI_1_LABEL
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#define DT_WDT_0_NAME DT_NORDIC_NRF_WATCHDOG_WDT_0_LABEL
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#define DT_RTC_0_NAME DT_NORDIC_NRF_RTC_RTC_0_LABEL
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#define DT_RTC_1_NAME DT_NORDIC_NRF_RTC_RTC_1_LABEL
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@ -37,8 +37,6 @@
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#define DT_SPI_3_NAME DT_NORDIC_NRF_SPIM_SPI_3_LABEL
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#define DT_WDT_0_NAME DT_NORDIC_NRF_WATCHDOG_WDT_0_LABEL
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#define DT_RTC_0_NAME DT_NORDIC_NRF_RTC_RTC_0_LABEL
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#define DT_RTC_1_NAME DT_NORDIC_NRF_RTC_RTC_1_LABEL
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#define DT_RTC_2_NAME DT_NORDIC_NRF_RTC_RTC_2_LABEL
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@ -20,8 +20,6 @@
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#define DT_SPI_1_NAME DT_NORDIC_NRF_SPIM_SPI_1_LABEL
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#define DT_SPI_2_NAME DT_NORDIC_NRF_SPIM_SPI_2_LABEL
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#define DT_WDT_0_NAME DT_NORDIC_NRF_WATCHDOG_WDT_0_LABEL
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#define DT_TIMER_0_NAME DT_NORDIC_NRF_TIMER_TIMER_0_LABEL
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#define DT_TIMER_1_NAME DT_NORDIC_NRF_TIMER_TIMER_1_LABEL
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#define DT_TIMER_2_NAME DT_NORDIC_NRF_TIMER_TIMER_2_LABEL
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@ -22,8 +22,6 @@
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#define DT_SPI_2_NAME DT_NORDIC_NRF_SPIM_SPI_2_LABEL
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#define DT_SPI_3_NAME DT_NORDIC_NRF_SPIM_SPI_3_LABEL
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#define DT_WDT_0_NAME DT_NORDIC_NRF_WATCHDOG_WDT_0_LABEL
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#define DT_TIMER_0_NAME DT_NORDIC_NRF_TIMER_TIMER_0_LABEL
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#define DT_TIMER_1_NAME DT_NORDIC_NRF_TIMER_TIMER_1_LABEL
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#define DT_TIMER_2_NAME DT_NORDIC_NRF_TIMER_TIMER_2_LABEL
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@ -14,7 +14,5 @@
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#define DT_ADC_1_NAME DT_NXP_KINETIS_ADC12_40027000_LABEL
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#define DT_ADC_2_NAME DT_NXP_KINETIS_ADC12_4003C000_LABEL
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#define DT_WDT_0_NAME DT_NXP_KINETIS_WDOG32_40052000_LABEL
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#define DT_CAN_0_NAME DT_NXP_KINETIS_FLEXCAN_40024000_LABEL
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#define DT_CAN_1_NAME DT_NXP_KINETIS_FLEXCAN_40025000_LABEL
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@ -14,7 +14,4 @@
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#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, silabs_gecko_rtcc))
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, silabs_gecko_wdog))
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#define DT_WDT_1_NAME DT_LABEL(DT_INST(1, silabs_gecko_wdog))
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/* End of SoC Level DTS fixup file */
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@ -13,7 +13,4 @@
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#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_GECKO_GPIO_4000A400_LOCATION_SWO
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, silabs_gecko_wdog))
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#define DT_WDT_1_NAME DT_LABEL(DT_INST(1, silabs_gecko_wdog))
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/* End of SoC Level DTS fixup file */
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@ -13,7 +13,4 @@
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#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_GECKO_GPIO_4000A400_LOCATION_SWO
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, silabs_gecko_wdog))
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#define DT_WDT_1_NAME DT_LABEL(DT_INST(1, silabs_gecko_wdog))
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/* End of SoC Level DTS fixup file */
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@ -15,6 +15,4 @@
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#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_GECKO_GPIO_4000A400_LOCATION_SWO
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, silabs_gecko_wdog))
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/* End of SoC Level DTS fixup file */
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@ -15,7 +15,4 @@
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#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_GECKO_GPIO_4000A400_LOCATION_SWO
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, silabs_gecko_wdog))
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#define DT_WDT_1_NAME DT_LABEL(DT_INST(1, silabs_gecko_wdog))
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/* End of SoC Level DTS fixup file */
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@ -16,8 +16,6 @@
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#define DT_FLASH_DEV_NAME DT_LABEL(DT_INST(0, st_stm32f0_flash_controller))
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
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#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL
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/* End of SoC Level DTS fixup file */
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@ -2,8 +2,6 @@
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/* SoC level DTS fixup file */
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
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#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL
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#define DT_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS
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@ -2,8 +2,6 @@
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/* SoC level DTS fixup file */
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
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#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012000_LABEL
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/* End of SoC Level DTS fixup file */
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@ -6,8 +6,6 @@
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#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
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#define DT_ADC_1_NAME DT_ST_STM32_ADC_50000000_LABEL
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#define DT_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS
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@ -142,8 +142,6 @@
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#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
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#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012000_LABEL
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#define DT_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS
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@ -21,8 +21,6 @@
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#define DT_CAN_1_CLOCK_BUS DT_ST_STM32_CAN_40006400_CLOCK_BUS
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#define DT_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
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#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012000_LABEL
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/* End of SoC Level DTS fixup file */
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@ -11,6 +11,4 @@
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#define DT_PWM_STM32_3_DEV_NAME DT_ST_STM32_PWM_40000400_PWM_LABEL
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#define DT_PWM_STM32_3_PRESCALER DT_ST_STM32_PWM_40000400_PWM_ST_PRESCALER
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
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/* End of SoC Level DTS fixup file */
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@ -13,6 +13,4 @@
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#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
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/* End of SoC Level DTS fixup file */
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@ -2,8 +2,6 @@
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/* SoC level DTS fixup file */
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
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#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL
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#define DT_RTC_0_NAME DT_ST_STM32_RTC_40002800_LABEL
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@ -6,8 +6,6 @@
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/* SoC level DTS fixup file */
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
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#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL
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#define DT_RTC_0_NAME DT_LABEL(DT_INST(0, st_stm32_rtc))
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@ -21,8 +21,6 @@
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#define DT_CAN_1_CLOCK_BUS DT_ST_STM32_CAN_40006400_CLOCK_BUS
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#define DT_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
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#define DT_ADC_1_NAME DT_ST_STM32_ADC_50040000_LABEL
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#define DT_LPTIM_1_BASE_ADDRESS DT_ST_STM32_TIMERS_40007C00_BASE_ADDRESS
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@ -12,8 +12,6 @@
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#define DT_ADC_1_NAME DT_ST_STM32_ADC_50040000_LABEL
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, st_stm32_watchdog))
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#define DT_LPTIM_1_BASE_ADDRESS DT_ST_STM32_TIMERS_40007C00_BASE_ADDRESS
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#define DT_LPTIM_1_IRQ DT_ST_STM32_TIMERS_40007C00_IRQ_0
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#define DT_LPTIM_1_IRQ_PRI DT_ST_STM32_TIMERS_40007C00_IRQ_0_PRIORITY
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@ -7,5 +7,4 @@
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/* SoC level DTS fixup file */
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#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY
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#define DT_WDT_0_NAME DT_LABEL(DT_INST(0, espressif_esp32_watchdog))
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/* End of SoC Level DTS fixup file */
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