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soc: x86: Convert to new DT_INST macros

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Convert older DT_INST_ macro use the new include/devicetree.h
DT_INST macro APIs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-03-25 11:27:19 -05:00 • committed by Kumar Gala
commit e31026310d
3 changed files with 15 additions and 15 deletions
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20
soc/x86/apollo_lake/soc.c
View file

@ -24,30 +24,30 @@
MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, 4 * 1024, MMU_ENTRY_WRITE);
/* ioapic */
MMU_BOOT_REGION(DT_INST_0_INTEL_IOAPIC_BASE_ADDRESS, 1024 * 1024, MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_REG_ADDR(DT_INST(0, intel_ioapic)), 1024 * 1024, MMU_ENTRY_WRITE);
#ifdef CONFIG_HPET_TIMER
MMU_BOOT_REGION(DT_INST_0_INTEL_HPET_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_REG_ADDR(DT_INST(0, intel_hpet)), KB(4), MMU_ENTRY_WRITE);
#endif /* CONFIG_HPET_TIMER */
/* for UARTs */
#ifdef DT_INST_0_NS16550
MMU_BOOT_REGION(DT_INST_0_NS16550_BASE_ADDRESS, 0x1000,
#if DT_HAS_NODE(DT_INST(0, ns16550))
MMU_BOOT_REGION(DT_REG_ADDR(DT_INST(0, ns16550)), 0x1000,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
#endif
#ifdef DT_INST_1_NS16550
MMU_BOOT_REGION(DT_INST_1_NS16550_BASE_ADDRESS, 0x1000,
#if DT_HAS_NODE(DT_INST(1, ns16550))
MMU_BOOT_REGION(DT_REG_ADDR(DT_INST(1, ns16550)), 0x1000,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
#endif
#ifdef DT_INST_2_NS16550
MMU_BOOT_REGION(DT_INST_2_NS16550_BASE_ADDRESS, 0x1000,
#if DT_HAS_NODE(DT_INST(2, ns16550))
MMU_BOOT_REGION(DT_REG_ADDR(DT_INST(2, ns16550)), 0x1000,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
#endif
#ifdef DT_INST_3_NS16550
MMU_BOOT_REGION(DT_INST_3_NS16550_BASE_ADDRESS, 0x1000,
#if DT_HAS_NODE(DT_INST(3, ns16550))
MMU_BOOT_REGION(DT_REG_ADDR(DT_INST(3, ns16550)), 0x1000,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
#endif

4
soc/x86/atom/soc.c
View file

@ -23,7 +23,7 @@
MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, 4*1024, MMU_ENTRY_WRITE);
/*ioapic */
MMU_BOOT_REGION(DT_INST_0_INTEL_IOAPIC_BASE_ADDRESS, 1024*1024, MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_REG_ADDR(DT_INST(0, intel_ioapic)), 1024*1024, MMU_ENTRY_WRITE);
/* peripherals */
MMU_BOOT_REGION(0xB0000000, 128*1024, MMU_ENTRY_WRITE);
@ -38,7 +38,7 @@ MMU_BOOT_REGION(0xB0700000, 4*1024, MMU_ENTRY_WRITE);
MMU_BOOT_REGION(0xB0500000, 256*1024, MMU_ENTRY_WRITE);
#ifdef CONFIG_HPET_TIMER
MMU_BOOT_REGION(DT_INST_0_INTEL_HPET_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_REG_ADDR(DT_INST(0, intel_hpet)), KB(4), MMU_ENTRY_WRITE);
#endif /* CONFIG_HPET_TIMER */
#endif /* CONFIG_X86_MMU */

6
soc/x86/ia32/soc.c
View file

@ -22,14 +22,14 @@
#ifdef CONFIG_X86_MMU
MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_INST_0_INTEL_IOAPIC_BASE_ADDRESS, MB(1), MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_REG_ADDR(DT_INST(0, intel_ioapic)), MB(1), MMU_ENTRY_WRITE);
#ifdef CONFIG_HPET_TIMER
MMU_BOOT_REGION(DT_INST_0_INTEL_HPET_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_REG_ADDR(DT_INST(0, intel_hpet)), KB(4), MMU_ENTRY_WRITE);
#endif
#ifdef CONFIG_ETH_E1000
MMU_BOOT_REGION(DT_INST_0_INTEL_E1000_BASE_ADDRESS, KB(128), MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_REG_ADDR(DT_INST(0, intel_e1000)), KB(128), MMU_ENTRY_WRITE);
#endif
#endif /* CONFIG_X86_MMU*/