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drivers: gpio_gecko: convert to DT_INST defines

Browse source 
Convert the driver to use DT_INST_ defines, update all dependent dts,
soc and board files.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This commit is contained in:
Piotr Mienkowski 2020-03-23 00:47:15 +01:00 • committed by Kumar Gala
commit 8a9df52943
44 changed files with 358 additions and 561 deletions
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31
boards/arm/efm32gg_stk3701a/Kconfig.defconfig
View file

@ -15,37 +15,6 @@ config CMU_HFXO_FREQ
config CMU_LFXO_FREQ
default 32768
if GPIO_GECKO
config GPIO_GECKO_PORTA
default y
config GPIO_GECKO_PORTB
default y
config GPIO_GECKO_PORTC
default y
config GPIO_GECKO_PORTD
default y
config GPIO_GECKO_PORTE
default y
config GPIO_GECKO_PORTF
default y
config GPIO_GECKO_PORTG
default y
config GPIO_GECKO_PORTH
default y
config GPIO_GECKO_PORTI
default y
endif # GPIO_GECKO
config COUNTER_GECKO_RTCC
default y
depends on COUNTER

8
boards/arm/efm32gg_stk3701a/board.h
View file

@ -9,18 +9,18 @@
#define __INC_BOARD_H
/* This pin is used to enable the serial port using the board controller */
#define BC_ENABLE_GPIO_NAME DT_GPIO_GECKO_PORTE_NAME
#define BC_ENABLE_GPIO_NAME "GPIO_E"
#define BC_ENABLE_GPIO_PIN 1
/* Ethernet specific pins */
#ifdef CONFIG_ETH_GECKO
#define ETH_PWR_ENABLE_GPIO_NAME DT_GPIO_GECKO_PORTI_NAME
#define ETH_PWR_ENABLE_GPIO_NAME "GPIO_I"
#define ETH_PWR_ENABLE_GPIO_PIN 10
#define ETH_RESET_GPIO_NAME DT_GPIO_GECKO_PORTH_NAME
#define ETH_RESET_GPIO_NAME "GPIO_H"
#define ETH_RESET_GPIO_PIN 7
#define ETH_REF_CLK_GPIO_NAME DT_GPIO_GECKO_PORTD_NAME
#define ETH_REF_CLK_GPIO_NAME "GPIO_D"
#define ETH_REF_CLK_GPIO_PIN DT_INST_0_SILABS_GECKO_ETHERNET_LOCATION_RMII_REFCLK_2
#define ETH_REF_CLK_LOCATION DT_INST_0_SILABS_GECKO_ETHERNET_LOCATION_RMII_REFCLK_0

36
boards/arm/efm32gg_stk3701a/efm32gg_stk3701a.dts
View file

@ -97,6 +97,42 @@
status = "okay";
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
};
&gpioc {
status = "okay";
};
&gpiod {
status = "okay";
};
&gpioe {
status = "okay";
};
&gpiof {
status = "okay";
};
&gpiog {
status = "okay";
};
&gpioh {
status = "okay";
};
&gpioi {
status = "okay";
};
&eth0 {
/* local-mac-address = <>;*/

22
boards/arm/efm32hg_slstk3400a/Kconfig.defconfig
View file

@ -14,26 +14,4 @@ config CMU_HFXO_FREQ
config CMU_LFXO_FREQ
default 32768
if GPIO_GECKO
config GPIO_GECKO_PORTA
default y
config GPIO_GECKO_PORTB
default n
config GPIO_GECKO_PORTC
default y
config GPIO_GECKO_PORTD
default n
config GPIO_GECKO_PORTE
default n
config GPIO_GECKO_PORTF
default y
endif # GPIO_GECKO
endif # BOARD_EFM32HG_SLSTK3400A

2
boards/arm/efm32hg_slstk3400a/board.h
View file

@ -8,7 +8,7 @@
#define __INC_BOARD_H
/* This pin is used to enable the serial port using the board controller */
#define BC_ENABLE_GPIO_NAME DT_GPIO_GECKO_PORTA_NAME
#define BC_ENABLE_GPIO_NAME "GPIO_A"
#define BC_ENABLE_GPIO_PIN 9
#endif /* __INC_BOARD_H */

12
boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a.dts
View file

@ -58,6 +58,18 @@
clock-frequency = <24000000>;
};
&gpioa {
status = "okay";
};
&gpioc {
status = "okay";
};
&gpiof {
status = "okay";
};
&usart1 {
current-speed = <115200>;
location-rx = <GECKO_LOCATION(4) GECKO_PORT_A GECKO_PIN(0)>;

22
boards/arm/efm32pg_stk3402a/Kconfig.defconfig
View file

@ -16,28 +16,6 @@ config CMU_HFXO_FREQ
config CMU_LFXO_FREQ
default 32768
if GPIO_GECKO
config GPIO_GECKO_PORTA
default y
config GPIO_GECKO_PORTB
default y
config GPIO_GECKO_PORTC
default n
config GPIO_GECKO_PORTD
default y
config GPIO_GECKO_PORTE
default n
config GPIO_GECKO_PORTF
default y
endif # GPIO_GECKO
config COUNTER_GECKO_RTCC
default y
depends on COUNTER

2
boards/arm/efm32pg_stk3402a/board.h
View file

@ -8,7 +8,7 @@
#define __INC_BOARD_H
/* This pin is used to enable the serial port using the board controller */
#define BC_ENABLE_GPIO_NAME DT_GPIO_GECKO_PORTA_NAME
#define BC_ENABLE_GPIO_NAME "GPIO_A"
#define BC_ENABLE_GPIO_PIN 5
#endif /* __INC_BOARD_H */

16
boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_common.dtsi
View file

@ -86,6 +86,22 @@
status = "okay";
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
};
&gpiod {
status = "okay";
};
&gpiof {
status = "okay";
};
&wdog0 {
status = "okay";
};

22
boards/arm/efm32wg_stk3800/Kconfig.defconfig
View file

@ -14,26 +14,4 @@ config CMU_HFXO_FREQ
config CMU_LFXO_FREQ
default 32768
if GPIO_GECKO
config GPIO_GECKO_PORTA
default y
config GPIO_GECKO_PORTB
default y
config GPIO_GECKO_PORTC
default n
config GPIO_GECKO_PORTD
default n
config GPIO_GECKO_PORTE
default y
config GPIO_GECKO_PORTF
default y
endif # GPIO_GECKO
endif # BOARD_EFM32WG_STK3800

2
boards/arm/efm32wg_stk3800/board.h
View file

@ -8,7 +8,7 @@
#define __INC_BOARD_H
/* This pin is used to enable the serial port using the board controller */
#define BC_ENABLE_GPIO_NAME DT_GPIO_GECKO_PORTF_NAME
#define BC_ENABLE_GPIO_NAME "GPIO_F"
#define BC_ENABLE_GPIO_PIN 7
#endif /* __INC_BOARD_H */

16
boards/arm/efm32wg_stk3800/efm32wg_stk3800.dts
View file

@ -57,6 +57,22 @@
clock-frequency = <48000000>;
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
};
&gpioe {
status = "okay";
};
&gpiof {
status = "okay";
};
&uart0 {
current-speed = <115200>;
location-rx = <GECKO_LOCATION(1) GECKO_PORT_E GECKO_PIN(1)>;

22
boards/arm/efr32_radio/Kconfig.defconfig
View file

@ -22,28 +22,6 @@ config LOG_BACKEND_SWO_FREQ_HZ
endif # LOG_BACKEND_SWO
if GPIO_GECKO
config GPIO_GECKO_PORTA
default y
config GPIO_GECKO_PORTB
default y
config GPIO_GECKO_PORTC
default y
config GPIO_GECKO_PORTD
default y
config GPIO_GECKO_PORTE
default n
config GPIO_GECKO_PORTF
default y
endif # GPIO_GECKO
if SERIAL
config UART_GECKO

2
boards/arm/efr32_radio/board.c
View file

@ -9,7 +9,7 @@
#include <sys/printk.h>
/* This pin is used to enable the serial port using the board controller */
#define VCOM_ENABLE_GPIO_NAME DT_GPIO_GECKO_PORTA_NAME
#define VCOM_ENABLE_GPIO_NAME "GPIO_A"
#define VCOM_ENABLE_GPIO_PIN 5
static int efr32_radio_init(struct device *dev)

20
boards/arm/efr32_radio/efr32_radio.dtsi
View file

@ -92,6 +92,26 @@
status = "okay";
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
};
&gpioc {
status = "okay";
};
&gpiod {
status = "okay";
};
&gpiof {
status = "okay";
};
&wdog0 {
status = "okay";
};

22
boards/arm/efr32_slwstk6061a/Kconfig.defconfig
View file

@ -18,28 +18,6 @@ config LOG_BACKEND_SWO_FREQ_HZ
default 875000
depends on LOG_BACKEND_SWO
if GPIO_GECKO
config GPIO_GECKO_PORTA
default y
config GPIO_GECKO_PORTB
default y
config GPIO_GECKO_PORTC
default y
config GPIO_GECKO_PORTD
default y
config GPIO_GECKO_PORTE
default n
config GPIO_GECKO_PORTF
default y
endif # GPIO_GECKO
config COUNTER_GECKO_RTCC
default y
depends on COUNTER

2
boards/arm/efr32_slwstk6061a/board.h
View file

@ -8,7 +8,7 @@
#define __INC_BOARD_H
/* This pin is used to enable the serial port using the board controller */
#define BC_ENABLE_GPIO_NAME DT_GPIO_GECKO_PORTA_NAME
#define BC_ENABLE_GPIO_NAME "GPIO_A"
#define BC_ENABLE_GPIO_PIN 5
#endif /* __INC_BOARD_H */

20
boards/arm/efr32_slwstk6061a/efr32_slwstk6061a.dts
View file

@ -102,6 +102,26 @@
status = "okay";
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
};
&gpioc {
status = "okay";
};
&gpiod {
status = "okay";
};
&gpiof {
status = "okay";
};
&wdog0 {
status = "okay";
};

16
boards/arm/efr32mg_sltb004a/Kconfig.defconfig
View file

@ -14,22 +14,6 @@ config CMU_HFXO_FREQ
config CMU_LFXO_FREQ
default 32768
if GPIO_GECKO
config GPIO_GECKO_PORTA
default y
config GPIO_GECKO_PORTD
default y
config GPIO_GECKO_PORTF
default y
config GPIO_GECKO_PORTK
default y
endif # GPIO_GECKO
config COUNTER_GECKO_RTCC
default y
depends on COUNTER

16
boards/arm/efr32mg_sltb004a/efr32mg_sltb004a.dts
View file

@ -120,6 +120,22 @@
status = "okay";
};
&gpioa {
status = "okay";
};
&gpiod {
status = "okay";
};
&gpiof {
status = "okay";
};
&gpiok {
status = "okay";
};
&wdog0 {
status = "okay";
};

60
drivers/gpio/Kconfig.gecko
View file

@ -11,65 +11,7 @@ menuconfig GPIO_GECKO
help
Enable the Gecko gpio driver.
if GPIO_GECKO
config GPIO_GECKO_COMMON_INIT_PRIORITY
int "Common initialization priority"
depends on GPIO_GECKO
default 39
config GPIO_GECKO_PORTA
bool "Port A"
help
Enable Port A.
config GPIO_GECKO_PORTB
bool "Port B"
help
Enable Port B.
config GPIO_GECKO_PORTC
bool "Port C"
help
Enable Port C.
config GPIO_GECKO_PORTD
bool "Port D"
help
Enable Port D.
config GPIO_GECKO_PORTE
bool "Port E"
help
Enable Port E.
config GPIO_GECKO_PORTF
bool "Port F"
help
Enable Port F.
config GPIO_GECKO_PORTG
bool "Port G"
help
Enable Port G.
config GPIO_GECKO_PORTH
bool "Port H"
help
Enable Port H.
config GPIO_GECKO_PORTI
bool "Port I"
help
Enable Port I.
config GPIO_GECKO_PORTJ
bool "Port J"
help
Enable Port J.
config GPIO_GECKO_PORTK
bool "Port K"
help
Enable Port K.
endif # GPIO_GECKO

99
drivers/gpio/gpio_gecko.c
View file

@ -301,7 +301,6 @@ static const struct gpio_driver_api gpio_gecko_common_driver_api = {
.disable_callback = gpio_gecko_disable_callback,
};
#ifdef CONFIG_GPIO_GECKO
static int gpio_gecko_common_init(struct device *dev);
static const struct gpio_gecko_common_config gpio_gecko_common_config = {
@ -309,7 +308,7 @@ static const struct gpio_gecko_common_config gpio_gecko_common_config = {
static struct gpio_gecko_common_data gpio_gecko_common_data;
DEVICE_AND_API_INIT(gpio_gecko_common, DT_GPIO_GECKO_COMMON_NAME,
DEVICE_AND_API_INIT(gpio_gecko_common, DT_INST_0_SILABS_GECKO_GPIO_LABEL,
gpio_gecko_common_init,
&gpio_gecko_common_data, &gpio_gecko_common_config,
POST_KERNEL, CONFIG_GPIO_GECKO_COMMON_INIT_PRIORITY,
@ -318,10 +317,12 @@ DEVICE_AND_API_INIT(gpio_gecko_common, DT_GPIO_GECKO_COMMON_NAME,
static int gpio_gecko_common_init(struct device *dev)
{
gpio_gecko_common_data.count = 0;
IRQ_CONNECT(GPIO_EVEN_IRQn, DT_GPIO_GECKO_COMMON_EVEN_PRI,
IRQ_CONNECT(GPIO_EVEN_IRQn,
DT_INST_0_SILABS_GECKO_GPIO_IRQ_GPIO_EVEN_PRIORITY,
gpio_gecko_common_isr, DEVICE_GET(gpio_gecko_common), 0);
IRQ_CONNECT(GPIO_ODD_IRQn, DT_GPIO_GECKO_COMMON_ODD_PRI,
IRQ_CONNECT(GPIO_ODD_IRQn,
DT_INST_0_SILABS_GECKO_GPIO_IRQ_GPIO_ODD_PRIORITY,
gpio_gecko_common_isr, DEVICE_GET(gpio_gecko_common), 0);
irq_enable(GPIO_EVEN_IRQn);
@ -329,74 +330,74 @@ static int gpio_gecko_common_init(struct device *dev)
return 0;
}
#endif /* CONFIG_GPIO_GECKO */
#define GPIO_PORT_INIT(pl, pu) \
static int gpio_gecko_port##pl##_init(struct device *dev); \
#define GPIO_PORT_INIT(idx) \
static int gpio_gecko_port##idx##_init(struct device *dev); \
\
static const struct gpio_gecko_config gpio_gecko_port##pl##_config = { \
static const struct gpio_gecko_config gpio_gecko_port##idx##_config = { \
.common = { \
.port_pin_mask = (gpio_port_pins_t)(-1), \
}, \
.gpio_base = &GPIO->P[gpioPort##pu], \
.gpio_index = gpioPort##pu, \
.gpio_base = (GPIO_P_TypeDef *)DT_INST_##idx##_SILABS_GECKO_GPIO_PORT_BASE_ADDRESS, \
.gpio_index = DT_INST_##idx##_SILABS_GECKO_GPIO_PORT_PERIPHERAL_ID, \
}; \
\
static struct gpio_gecko_data gpio_gecko_port##pl##_data; \
static struct gpio_gecko_data gpio_gecko_port##idx##_data; \
\
DEVICE_AND_API_INIT(gpio_gecko_port##pl, DT_GPIO_GECKO_PORT##pu##_NAME, \
gpio_gecko_port##pl##_init, \
&gpio_gecko_port##pl##_data, \
&gpio_gecko_port##pl##_config, \
DEVICE_AND_API_INIT(gpio_gecko_port##idx, \
DT_INST_##idx##_SILABS_GECKO_GPIO_PORT_LABEL, \
gpio_gecko_port##idx##_init, \
&gpio_gecko_port##idx##_data, \
&gpio_gecko_port##idx##_config, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
&gpio_gecko_driver_api); \
\
static int gpio_gecko_port##pl##_init(struct device *dev) \
static int gpio_gecko_port##idx##_init(struct device *dev) \
{ \
gpio_gecko_add_port(&gpio_gecko_common_data, dev); \
return 0; \
}
#ifdef CONFIG_GPIO_GECKO_PORTA
GPIO_PORT_INIT(a, A)
#endif /* CONFIG_GPIO_GECKO_PORTA */
#ifdef DT_INST_0_SILABS_GECKO_GPIO_PORT
GPIO_PORT_INIT(0)
#endif /* DT_INST_0_SILABS_GECKO_GPIO_PORT */
#ifdef CONFIG_GPIO_GECKO_PORTB
GPIO_PORT_INIT(b, B)
#endif /* CONFIG_GPIO_GECKO_PORTB */
#ifdef DT_INST_1_SILABS_GECKO_GPIO_PORT
GPIO_PORT_INIT(1)
#endif /* DT_INST_1_SILABS_GECKO_GPIO_PORT */
#ifdef CONFIG_GPIO_GECKO_PORTC
GPIO_PORT_INIT(c, C)
#endif /* CONFIG_GPIO_GECKO_PORTC */
#ifdef DT_INST_2_SILABS_GECKO_GPIO_PORT
GPIO_PORT_INIT(2)
#endif /* DT_INST_2_SILABS_GECKO_GPIO_PORT */
#ifdef CONFIG_GPIO_GECKO_PORTD
GPIO_PORT_INIT(d, D)
#endif /* CONFIG_GPIO_GECKO_PORTD */
#ifdef DT_INST_3_SILABS_GECKO_GPIO_PORT
GPIO_PORT_INIT(3)
#endif /* DT_INST_3_SILABS_GECKO_GPIO_PORT */
#ifdef CONFIG_GPIO_GECKO_PORTE
GPIO_PORT_INIT(e, E)
#endif /* CONFIG_GPIO_GECKO_PORTE */
#ifdef DT_INST_4_SILABS_GECKO_GPIO_PORT
GPIO_PORT_INIT(4)
#endif /* DT_INST_4_SILABS_GECKO_GPIO_PORT */
#ifdef CONFIG_GPIO_GECKO_PORTF
GPIO_PORT_INIT(f, F)
#endif /* CONFIG_GPIO_GECKO_PORTF */
#ifdef DT_INST_5_SILABS_GECKO_GPIO_PORT
GPIO_PORT_INIT(5)
#endif /* DT_INST_5_SILABS_GECKO_GPIO_PORT */
#ifdef CONFIG_GPIO_GECKO_PORTG
GPIO_PORT_INIT(g, G)
#endif /* CONFIG_GPIO_GECKO_PORTG */
#ifdef DT_INST_6_SILABS_GECKO_GPIO_PORT
GPIO_PORT_INIT(6)
#endif /* DT_INST_6_SILABS_GECKO_GPIO_PORT */
#ifdef CONFIG_GPIO_GECKO_PORTH
GPIO_PORT_INIT(h, H)
#endif /* CONFIG_GPIO_GECKO_PORTH */
#ifdef DT_INST_7_SILABS_GECKO_GPIO_PORT
GPIO_PORT_INIT(7)
#endif /* DT_INST_7_SILABS_GECKO_GPIO_PORT */
#ifdef CONFIG_GPIO_GECKO_PORTI
GPIO_PORT_INIT(i, I)
#endif /* CONFIG_GPIO_GECKO_PORTI */
#ifdef DT_INST_8_SILABS_GECKO_GPIO_PORT
GPIO_PORT_INIT(8)
#endif /* DT_INST_8_SILABS_GECKO_GPIO_PORT */
#ifdef CONFIG_GPIO_GECKO_PORTJ
GPIO_PORT_INIT(j, J)
#endif /* CONFIG_GPIO_GECKO_PORTJ */
#ifdef DT_INST_9_SILABS_GECKO_GPIO_PORT
GPIO_PORT_INIT(9)
#endif /* DT_INST_9_SILABS_GECKO_GPIO_PORT */
#ifdef CONFIG_GPIO_GECKO_PORTK
GPIO_PORT_INIT(k, K)
#endif /* CONFIG_GPIO_GECKO_PORTK */
#ifdef DT_INST_10_SILABS_GECKO_GPIO_PORT
GPIO_PORT_INIT(10)
#endif /* DT_INST_10_SILABS_GECKO_GPIO_PORT */

46
dts/arm/silabs/efm32_jg_pg_12b.dtsi
View file

@ -121,7 +121,7 @@
};
gpio: gpio@4000a400 {
compatible = "silabs,efm32-gpio";
compatible = "silabs,gecko-gpio";
reg = <0x4000a400 0xf00>;
interrupts = <1 2 11 2>;
interrupt-names = "GPIO_EVEN", "GPIO_ODD";
@ -132,75 +132,93 @@
#size-cells = <1>;
gpioa: gpio@4000a000 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a000 0x30>;
peripheral-id = <0>;
label = "GPIO_A";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiob: gpio@4000a030 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a030 0x30>;
peripheral-id = <1>;
label = "GPIO_B";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioc: gpio@4000a060 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a060 0x30>;
peripheral-id = <2>;
label = "GPIO_C";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiod: gpio@4000a090 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a090 0x30>;
peripheral-id = <3>;
label = "GPIO_D";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioe: gpio@4000a0c0 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a0c0 0x30>;
peripheral-id = <4>;
label = "GPIO_E";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiof: gpio@4000a0f0 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a0f0 0x30>;
peripheral-id = <5>;
label = "GPIO_F";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioi: gpio@4000a180 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a180 0x30>;
peripheral-id = <8>;
label = "GPIO_I";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioj: gpio@4000a1c0 {
compatible = "silabs,efm32-gpio-port";
reg = <0x4000a1c0 0x30>;
gpioj: gpio@4000a1b0 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a1b0 0x30>;
peripheral-id = <9>;
label = "GPIO_J";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiok: gpio@4000a1f0 {
compatible = "silabs,efm32-gpio-port";
reg = <0x4000a1f0 0x30>;
gpiok: gpio@4000a1e0 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a1e0 0x30>;
peripheral-id = <10>;
label = "GPIO_K";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
wdog0: wdog@40052000 {

38
dts/arm/silabs/efm32gg11b.dtsi
View file

@ -186,7 +186,7 @@
};
gpio: gpio@40088400 {
compatible = "silabs,efm32-gpio";
compatible = "silabs,gecko-gpio";
reg = <0x40088400 0xc00>;
interrupts = <3 2 13 2>;
interrupt-names = "GPIO_EVEN", "GPIO_ODD";
@ -197,75 +197,93 @@
#size-cells = <1>;
gpioa: gpio@40088000 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x40088000 0x30>;
peripheral-id = <0>;
label = "GPIO_A";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiob: gpio@40088030 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x40088030 0x30>;
peripheral-id = <1>;
label = "GPIO_B";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioc: gpio@40088060 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x40088060 0x30>;
peripheral-id = <2>;
label = "GPIO_C";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiod: gpio@40088090 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x40088090 0x30>;
peripheral-id = <3>;
label = "GPIO_D";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioe: gpio@400880c0 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x400880c0 0x30>;
peripheral-id = <4>;
label = "GPIO_E";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiof: gpio@400880f0 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x400880f0 0x30>;
peripheral-id = <5>;
label = "GPIO_F";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiog: gpio@40088120 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x40088120 0x30>;
peripheral-id = <6>;
label = "GPIO_G";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioh: gpio@40088150 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x40088150 0x30>;
peripheral-id = <7>;
label = "GPIO_H";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioi: gpio@40088180 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x40088180 0x30>;
peripheral-id = <8>;
label = "GPIO_I";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
};
};

26
dts/arm/silabs/efm32hg.dtsi
View file

@ -79,7 +79,7 @@
};
gpio@40006100 {
compatible = "silabs,efm32-gpio";
compatible = "silabs,gecko-gpio";
reg = <0x40006100 0xf00>;
interrupts = <1 0 6 0>;
interrupt-names = "GPIO_EVEN", "GPIO_ODD";
@ -90,51 +90,63 @@
#size-cells = <1>;
gpioa: gpio@40006000 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x40006000 0x24>;
peripheral-id = <0>;
label = "GPIO_A";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiob: gpio@40006024 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x40006024 0x24>;
peripheral-id = <1>;
label = "GPIO_B";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioc: gpio@40006048 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x40006048 0x24>;
peripheral-id = <2>;
label = "GPIO_C";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiod: gpio@4000606c {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000606c 0x24>;
peripheral-id = <3>;
label = "GPIO_D";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioe: gpio@40006090 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x40006090 0x24>;
peripheral-id = <4>;
label = "GPIO_E";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiof: gpio@400060b4 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x400060b4 0x24>;
peripheral-id = <5>;
label = "GPIO_F";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
};
};

26
dts/arm/silabs/efm32wg.dtsi
View file

@ -129,7 +129,7 @@
};
gpio@40006100 {
compatible = "silabs,efm32-gpio";
compatible = "silabs,gecko-gpio";
reg = <0x40006100 0xf00>;
interrupts = <1 2 11 2>;
interrupt-names = "GPIO_EVEN", "GPIO_ODD";
@ -140,51 +140,63 @@
#size-cells = <1>;
gpioa: gpio@40006000 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x40006000 0x24>;
peripheral-id = <0>;
label = "GPIO_A";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiob: gpio@40006024 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x40006024 0x24>;
peripheral-id = <1>;
label = "GPIO_B";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioc: gpio@40006048 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x40006048 0x24>;
peripheral-id = <2>;
label = "GPIO_C";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiod: gpio@4000606c {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000606c 0x24>;
peripheral-id = <3>;
label = "GPIO_D";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioe: gpio@40006090 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x40006090 0x24>;
peripheral-id = <4>;
label = "GPIO_E";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiof: gpio@400060b4 {
compatible = "silabs,efm32-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x400060b4 0x24>;
peripheral-id = <5>;
label = "GPIO_F";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
};
};

10
dts/arm/silabs/efr32bg13p.dtsi
View file

@ -127,41 +127,51 @@
gpioa: gpio@4000a000 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a000 0x30>;
peripheral-id = <0>;
label = "GPIO_A";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiob: gpio@4000a030 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a030 0x30>;
peripheral-id = <1>;
label = "GPIO_B";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioc: gpio@4000a060 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a060 0x30>;
peripheral-id = <2>;
label = "GPIO_C";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiod: gpio@4000a090 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a090 0x30>;
peripheral-id = <3>;
label = "GPIO_D";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiof: gpio@4000a0f0 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a0f0 0x30>;
peripheral-id = <5>;
label = "GPIO_F";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
};

26
dts/arm/silabs/efr32fg1p.dtsi
View file

@ -89,7 +89,7 @@
};
gpio: gpio@4000a400 {
compatible = "silabs,efr32xg1-gpio";
compatible = "silabs,gecko-gpio";
reg = <0x4000a400 0xc00>;
interrupts = <9 2 17 2>;
interrupt-names = "GPIO_EVEN", "GPIO_ODD";
@ -100,51 +100,63 @@
#size-cells = <1>;
gpioa: gpio@4000a000 {
compatible = "silabs,efr32xg1-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a000 0x30>;
peripheral-id = <0>;
label = "GPIO_A";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiob: gpio@4000a030 {
compatible = "silabs,efr32xg1-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a030 0x30>;
peripheral-id = <1>;
label = "GPIO_B";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioc: gpio@4000a060 {
compatible = "silabs,efr32xg1-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a060 0x30>;
peripheral-id = <2>;
label = "GPIO_C";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiod: gpio@4000a090 {
compatible = "silabs,efr32xg1-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a090 0x30>;
peripheral-id = <3>;
label = "GPIO_D";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioe: gpio@4000a0c0 {
compatible = "silabs,efr32xg1-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a0c0 0x30>;
peripheral-id = <4>;
label = "GPIO_E";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiof: gpio@4000a0f0 {
compatible = "silabs,efr32xg1-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a0f0 0x30>;
peripheral-id = <5>;
label = "GPIO_F";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
};

34
dts/arm/silabs/efr32mg.dtsi
View file

@ -120,7 +120,7 @@
};
gpio: gpio@4000a400 {
compatible = "silabs,efr32mg-gpio";
compatible = "silabs,gecko-gpio";
reg = <0x4000a400 0xc00>;
interrupts = <9 2 17 2>;
interrupt-names = "GPIO_EVEN", "GPIO_ODD";
@ -131,67 +131,83 @@
#size-cells = <1>;
gpioa: gpio@4000a000 {
compatible = "silabs,efr32mg-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a000 0x30>;
peripheral-id = <0>;
label = "GPIO_A";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiob: gpio@4000a030 {
compatible = "silabs,efr32mg-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a030 0x30>;
peripheral-id = <1>;
label = "GPIO_B";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioc: gpio@4000a060 {
compatible = "silabs,efr32mg-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a060 0x30>;
peripheral-id = <2>;
label = "GPIO_C";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiod: gpio@4000a090 {
compatible = "silabs,efr32mg-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a090 0x30>;
peripheral-id = <3>;
label = "GPIO_D";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiof: gpio@4000a0f0 {
compatible = "silabs,efr32mg-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a0f0 0x30>;
peripheral-id = <5>;
label = "GPIO_F";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioi: gpio@4000a180 {
compatible = "silabs,efr32mg-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a180 0x30>;
peripheral-id = <8>;
label = "GPIO_I";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioj: gpio@4000a1b0 {
compatible = "silabs,efr32mg-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a1b0 0x30>;
peripheral-id = <9>;
label = "GPIO_J";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiok: gpio@4000a1e0 {
compatible = "silabs,efr32mg-gpio-port";
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a1e0 0x30>;
peripheral-id = <10>;
label = "GPIO_K";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
};

19
dts/bindings/gpio/silabs,efm32-gpio-port.yaml
View file

@ -1,19 +0,0 @@
description: EFM32 GPIO port node
compatible: "silabs,efm32-gpio-port"
include: [gpio-controller.yaml, base.yaml]
properties:
reg:
required: true
label:
required: true
"#gpio-cells":
const: 2
gpio-cells:
- pin
- flags

20
dts/bindings/gpio/silabs,efm32-gpio.yaml
View file

@ -1,20 +0,0 @@
description: EFM32 GPIO node
compatible: "silabs,efm32-gpio"
include: base.yaml
properties:
reg:
required: true
interrupts:
required: true
label:
required: true
location-swo:
type: int
required: false
description: Serial Wire Output (SWO) PIN location

19
dts/bindings/gpio/silabs,efr32mg12-gpio-port.yaml
View file

@ -1,19 +0,0 @@
description: EFR32MG GPIO port node
compatible: "silabs,efr32mg-gpio-port"
include: [gpio-controller.yaml, base.yaml]
properties:
reg:
required: true
label:
required: true
"#gpio-cells":
const: 2
gpio-cells:
- pin
- flags

20
dts/bindings/gpio/silabs,efr32mg12-gpio.yaml
View file

@ -1,20 +0,0 @@
description: EFR32MG GPIO node
compatible: "silabs,efr32mg-gpio"
include: base.yaml
properties:
reg:
required: true
interrupts:
required: true
label:
required: true
location-swo:
type: int
required: false
description: Serial Wire Output (SWO) PIN location

19
dts/bindings/gpio/silabs,efr32xg1-gpio-port.yaml
View file

@ -1,19 +0,0 @@
description: EFR32XG1 GPIO port node
compatible: "silabs,efr32xg1-gpio-port"
include: [gpio-controller.yaml, base.yaml]
properties:
reg:
required: true
label:
required: true
"#gpio-cells":
const: 2
gpio-cells:
- pin
- flags

20
dts/bindings/gpio/silabs,efr32xg1-gpio.yaml
View file

@ -1,20 +0,0 @@
description: EFR32XG1 GPIO node
compatible: "silabs,efr32xg1-gpio"
include: base.yaml
properties:
reg:
required: true
interrupts:
required: true
label:
required: true
location-swo:
type: int
required: false
description: Serial Wire Output (SWO) PIN location

5
dts/bindings/gpio/silabs,gecko-gpio-port.yaml
View file

@ -11,6 +11,11 @@ properties:
label:
required: true
peripheral-id:
type: int
required: true
description: peripheral ID
"#gpio-cells":
const: 2

17
soc/arm/silabs_exx32/efm32gg11b/dts_fixup.h
View file

@ -12,22 +12,7 @@
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_40000000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_40000000_LABEL
#define DT_GPIO_GECKO_COMMON_NAME DT_SILABS_EFM32_GPIO_40088400_LABEL
#define DT_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_EFM32_GPIO_40088400_IRQ_GPIO_EVEN
#define DT_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_EFM32_GPIO_40088400_IRQ_GPIO_EVEN_PRIORITY
#define DT_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_EFM32_GPIO_40088400_IRQ_GPIO_ODD
#define DT_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_EFM32_GPIO_40088400_IRQ_GPIO_ODD_PRIORITY
#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_EFM32_GPIO_40088400_LOCATION_SWO
#define DT_GPIO_GECKO_PORTA_NAME DT_SILABS_EFM32_GPIO_PORT_40088000_LABEL
#define DT_GPIO_GECKO_PORTB_NAME DT_SILABS_EFM32_GPIO_PORT_40088030_LABEL
#define DT_GPIO_GECKO_PORTC_NAME DT_SILABS_EFM32_GPIO_PORT_40088060_LABEL
#define DT_GPIO_GECKO_PORTD_NAME DT_SILABS_EFM32_GPIO_PORT_40088090_LABEL
#define DT_GPIO_GECKO_PORTE_NAME DT_SILABS_EFM32_GPIO_PORT_400880C0_LABEL
#define DT_GPIO_GECKO_PORTF_NAME DT_SILABS_EFM32_GPIO_PORT_400880F0_LABEL
#define DT_GPIO_GECKO_PORTG_NAME DT_SILABS_EFM32_GPIO_PORT_40088120_LABEL
#define DT_GPIO_GECKO_PORTH_NAME DT_SILABS_EFM32_GPIO_PORT_40088150_LABEL
#define DT_GPIO_GECKO_PORTI_NAME DT_SILABS_EFM32_GPIO_PORT_40088180_LABEL
#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_GECKO_GPIO_40088400_LOCATION_SWO
#define DT_RTC_0_NAME DT_INST_0_SILABS_GECKO_RTCC_LABEL

13
soc/arm/silabs_exx32/efm32hg/dts_fixup.h
View file

@ -14,17 +14,4 @@
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL
#define DT_GPIO_GECKO_COMMON_NAME DT_SILABS_EFM32_GPIO_40006100_LABEL
#define DT_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_EVEN
#define DT_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_EVEN_PRIORITY
#define DT_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_ODD
#define DT_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_ODD_PRIORITY
#define DT_GPIO_GECKO_PORTA_NAME DT_SILABS_EFM32_GPIO_PORT_40006000_LABEL
#define DT_GPIO_GECKO_PORTB_NAME DT_SILABS_EFM32_GPIO_PORT_40006024_LABEL
#define DT_GPIO_GECKO_PORTC_NAME DT_SILABS_EFM32_GPIO_PORT_40006048_LABEL
#define DT_GPIO_GECKO_PORTD_NAME DT_SILABS_EFM32_GPIO_PORT_4000606C_LABEL
#define DT_GPIO_GECKO_PORTE_NAME DT_SILABS_EFM32_GPIO_PORT_40006090_LABEL
#define DT_GPIO_GECKO_PORTF_NAME DT_SILABS_EFM32_GPIO_PORT_400060B4_LABEL
/* End of SoC Level DTS fixup file */

17
soc/arm/silabs_exx32/efm32jg12b/dts_fixup.h
View file

@ -12,22 +12,7 @@
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL
#define DT_GPIO_GECKO_COMMON_NAME DT_SILABS_EFM32_GPIO_4000A400_LABEL
#define DT_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_EFM32_GPIO_4000A400_IRQ_GPIO_EVEN
#define DT_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_EFM32_GPIO_4000A400_IRQ_GPIO_EVEN_PRIORITY
#define DT_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_EFM32_GPIO_4000A400_IRQ_GPIO_ODD
#define DT_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_EFM32_GPIO_4000A400_IRQ_GPIO_ODD_PRIORITY
#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_EFM32_GPIO_4000A400_LOCATION_SWO
#define DT_GPIO_GECKO_PORTA_NAME DT_SILABS_EFM32_GPIO_PORT_4000A000_LABEL
#define DT_GPIO_GECKO_PORTB_NAME DT_SILABS_EFM32_GPIO_PORT_4000A030_LABEL
#define DT_GPIO_GECKO_PORTC_NAME DT_SILABS_EFM32_GPIO_PORT_4000A060_LABEL
#define DT_GPIO_GECKO_PORTD_NAME DT_SILABS_EFM32_GPIO_PORT_4000A090_LABEL
#define DT_GPIO_GECKO_PORTE_NAME DT_SILABS_EFM32_GPIO_PORT_4000A0C0_LABEL
#define DT_GPIO_GECKO_PORTF_NAME DT_SILABS_EFM32_GPIO_PORT_4000A0F0_LABEL
#define DT_GPIO_GECKO_PORTI_NAME DT_SILABS_EFM32_GPIO_PORT_4000A180_LABEL
#define DT_GPIO_GECKO_PORTJ_NAME DT_SILABS_EFM32_GPIO_PORT_4000A1C0_LABEL
#define DT_GPIO_GECKO_PORTK_NAME DT_SILABS_EFM32_GPIO_PORT_4000A1F0_LABEL
#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_GECKO_GPIO_4000A400_LOCATION_SWO
#define DT_WDT_0_NAME DT_INST_0_SILABS_GECKO_WDOG_LABEL
#define DT_WDT_1_NAME DT_INST_1_SILABS_GECKO_WDOG_LABEL

17
soc/arm/silabs_exx32/efm32pg12b/dts_fixup.h
View file

@ -12,22 +12,7 @@
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL
#define DT_GPIO_GECKO_COMMON_NAME DT_SILABS_EFM32_GPIO_4000A400_LABEL
#define DT_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_EFM32_GPIO_4000A400_IRQ_GPIO_EVEN
#define DT_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_EFM32_GPIO_4000A400_IRQ_GPIO_EVEN_PRIORITY
#define DT_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_EFM32_GPIO_4000A400_IRQ_GPIO_ODD
#define DT_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_EFM32_GPIO_4000A400_IRQ_GPIO_ODD_PRIORITY
#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_EFM32_GPIO_4000A400_LOCATION_SWO
#define DT_GPIO_GECKO_PORTA_NAME DT_SILABS_EFM32_GPIO_PORT_4000A000_LABEL
#define DT_GPIO_GECKO_PORTB_NAME DT_SILABS_EFM32_GPIO_PORT_4000A030_LABEL
#define DT_GPIO_GECKO_PORTC_NAME DT_SILABS_EFM32_GPIO_PORT_4000A060_LABEL
#define DT_GPIO_GECKO_PORTD_NAME DT_SILABS_EFM32_GPIO_PORT_4000A090_LABEL
#define DT_GPIO_GECKO_PORTE_NAME DT_SILABS_EFM32_GPIO_PORT_4000A0C0_LABEL
#define DT_GPIO_GECKO_PORTF_NAME DT_SILABS_EFM32_GPIO_PORT_4000A0F0_LABEL
#define DT_GPIO_GECKO_PORTI_NAME DT_SILABS_EFM32_GPIO_PORT_4000A180_LABEL
#define DT_GPIO_GECKO_PORTJ_NAME DT_SILABS_EFM32_GPIO_PORT_4000A1C0_LABEL
#define DT_GPIO_GECKO_PORTK_NAME DT_SILABS_EFM32_GPIO_PORT_4000A1F0_LABEL
#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_GECKO_GPIO_4000A400_LOCATION_SWO
#define DT_WDT_0_NAME DT_INST_0_SILABS_GECKO_WDOG_LABEL
#define DT_WDT_1_NAME DT_INST_1_SILABS_GECKO_WDOG_LABEL

13
soc/arm/silabs_exx32/efm32wg/dts_fixup.h
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@ -14,17 +14,4 @@
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL
#define DT_GPIO_GECKO_COMMON_NAME DT_SILABS_EFM32_GPIO_40006100_LABEL
#define DT_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_EVEN
#define DT_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_EVEN_PRIORITY
#define DT_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_ODD
#define DT_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_ODD_PRIORITY
#define DT_GPIO_GECKO_PORTA_NAME DT_SILABS_EFM32_GPIO_PORT_40006000_LABEL
#define DT_GPIO_GECKO_PORTB_NAME DT_SILABS_EFM32_GPIO_PORT_40006024_LABEL
#define DT_GPIO_GECKO_PORTC_NAME DT_SILABS_EFM32_GPIO_PORT_40006048_LABEL
#define DT_GPIO_GECKO_PORTD_NAME DT_SILABS_EFM32_GPIO_PORT_4000606C_LABEL
#define DT_GPIO_GECKO_PORTE_NAME DT_SILABS_EFM32_GPIO_PORT_40006090_LABEL
#define DT_GPIO_GECKO_PORTF_NAME DT_SILABS_EFM32_GPIO_PORT_400060B4_LABEL
/* End of SoC Level DTS fixup file */

14
soc/arm/silabs_exx32/efr32bg13p/dts_fixup.h
View file

@ -18,20 +18,6 @@
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL
#define DT_GPIO_GECKO_COMMON_NAME DT_SILABS_GECKO_GPIO_4000A400_LABEL
#define DT_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_GECKO_GPIO_4000A400_IRQ_GPIO_EVEN
#define DT_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_GECKO_GPIO_4000A400_IRQ_GPIO_EVEN_PRIORITY
#define DT_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_GECKO_GPIO_4000A400_IRQ_GPIO_ODD
#define DT_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_GECKO_GPIO_4000A400_IRQ_GPIO_ODD_PRIORITY
#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_GECKO_GPIO_4000A400_LOCATION_SWO
#define DT_GPIO_GECKO_PORTA_NAME DT_SILABS_GECKO_GPIO_PORT_4000A000_LABEL
#define DT_GPIO_GECKO_PORTB_NAME DT_SILABS_GECKO_GPIO_PORT_4000A030_LABEL
#define DT_GPIO_GECKO_PORTC_NAME DT_SILABS_GECKO_GPIO_PORT_4000A060_LABEL
#define DT_GPIO_GECKO_PORTD_NAME DT_SILABS_GECKO_GPIO_PORT_4000A090_LABEL
#define DT_GPIO_GECKO_PORTF_NAME DT_SILABS_GECKO_GPIO_PORT_4000A0F0_LABEL
#define DT_GPIO_GECKO_PORTI_NAME DT_SILABS_GECKO_GPIO_PORT_4000A180_LABEL
#define DT_GPIO_GECKO_PORTJ_NAME DT_SILABS_GECKO_GPIO_PORT_4000A1B0_LABEL
#define DT_GPIO_GECKO_PORTK_NAME DT_SILABS_GECKO_GPIO_PORT_4000A1E0_LABEL
/* End of SoC Level DTS fixup file */

14
soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h
View file

@ -14,19 +14,7 @@
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL
#define DT_GPIO_GECKO_COMMON_NAME DT_SILABS_EFR32XG1_GPIO_4000A400_LABEL
#define DT_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_EFR32XG1_GPIO_4000A400_IRQ_GPIO_EVEN
#define DT_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_EFR32XG1_GPIO_4000A400_IRQ_GPIO_EVEN_PRIORITY
#define DT_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_EFR32XG1_GPIO_4000A400_IRQ_GPIO_ODD
#define DT_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_EFR32XG1_GPIO_4000A400_IRQ_GPIO_ODD_PRIORITY
#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_EFR32XG1_GPIO_4000A400_LOCATION_SWO
#define DT_GPIO_GECKO_PORTA_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A000_LABEL
#define DT_GPIO_GECKO_PORTB_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A030_LABEL
#define DT_GPIO_GECKO_PORTC_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A060_LABEL
#define DT_GPIO_GECKO_PORTD_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A090_LABEL
#define DT_GPIO_GECKO_PORTE_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A0C0_LABEL
#define DT_GPIO_GECKO_PORTF_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A0F0_LABEL
#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_GECKO_GPIO_4000A400_LOCATION_SWO
#define DT_WDT_0_NAME DT_INST_0_SILABS_GECKO_WDOG_LABEL

16
soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h
View file

@ -14,21 +14,7 @@
#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL
#define DT_GPIO_GECKO_COMMON_NAME DT_SILABS_EFR32MG_GPIO_4000A400_LABEL
#define DT_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_EFR32MG_GPIO_4000A400_IRQ_GPIO_EVEN
#define DT_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_EFR32MG_GPIO_4000A400_IRQ_GPIO_EVEN_PRIORITY
#define DT_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_EFR32MG_GPIO_4000A400_IRQ_GPIO_ODD
#define DT_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_EFR32MG_GPIO_4000A400_IRQ_GPIO_ODD_PRIORITY
#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_EFR32MG_GPIO_4000A400_LOCATION_SWO
#define DT_GPIO_GECKO_PORTA_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A000_LABEL
#define DT_GPIO_GECKO_PORTB_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A030_LABEL
#define DT_GPIO_GECKO_PORTC_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A060_LABEL
#define DT_GPIO_GECKO_PORTD_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A090_LABEL
#define DT_GPIO_GECKO_PORTF_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A0F0_LABEL
#define DT_GPIO_GECKO_PORTI_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A180_LABEL
#define DT_GPIO_GECKO_PORTJ_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A1B0_LABEL
#define DT_GPIO_GECKO_PORTK_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A1E0_LABEL
#define DT_GPIO_GECKO_SWO_LOCATION DT_SILABS_GECKO_GPIO_4000A400_LOCATION_SWO
#define DT_WDT_0_NAME DT_INST_0_SILABS_GECKO_WDOG_LABEL
#define DT_WDT_1_NAME DT_INST_1_SILABS_GECKO_WDOG_LABEL