drivers: pinctrl: refactor pin control support for imx rt
Refactor iMX RT pin control support to use more generic names, as the IOMUXC peripheral is present on non RT iMX application cores. Additionally, make selection of the pin control driver occur at the SOC level. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
parent
87b4759663
commit
bc841e1fb7
12 changed files with 144 additions and 120 deletions
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@ -317,7 +317,7 @@ static const struct gpio_driver_api mcux_igpio_driver_api = {
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#ifdef CONFIG_PINCTRL
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/* These macros will declare an array of pinctrl_soc_pinmux types */
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#define PINMUX_INIT(node, prop, idx) MCUX_RT_PINMUX(DT_PROP_BY_IDX(node, prop, idx)),
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#define PINMUX_INIT(node, prop, idx) MCUX_IMX_PINMUX(DT_PROP_BY_IDX(node, prop, idx)),
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#define MCUX_IGPIO_PIN_DECLARE(n) \
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const struct pinctrl_soc_pinmux mcux_igpio_pinmux_##n[] = { \
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DT_FOREACH_PROP_ELEM(DT_DRV_INST(n), pinmux, PINMUX_INIT) \
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@ -16,7 +16,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM0 pinctrl_sam0.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_STM32 pinctrl_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_KINETIS pinctrl_kinetis.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCUX_RT pinctrl_mcux_rt.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX pinctrl_imx.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOCON pinctrl_lpc_iocon.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_CC13XX_CC26XX pinctrl_cc13xx_cc26xx.c)
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@ -41,7 +41,7 @@ source "drivers/pinctrl/Kconfig.sam0"
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source "drivers/pinctrl/Kconfig.stm32"
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source "drivers/pinctrl/Kconfig.kinetis"
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source "drivers/pinctrl/Kconfig.xec"
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source "drivers/pinctrl/Kconfig.mcux"
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source "drivers/pinctrl/Kconfig.imx"
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source "drivers/pinctrl/Kconfig.sifive"
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source "drivers/pinctrl/Kconfig.lpc_iocon"
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source "drivers/pinctrl/Kconfig.cc13xx_cc26xx"
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8
drivers/pinctrl/Kconfig.imx
Normal file
8
drivers/pinctrl/Kconfig.imx
Normal file
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@ -0,0 +1,8 @@
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# Copyright (c) 2022 NXP
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_IMX
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bool "Pin controller driver for iMX MCUs"
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depends on HAS_MCUX_IOMUXC || HAS_IMX_IOMUXC
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help
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Enable pin controller driver for NXP iMX series MCUs
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@ -1,13 +0,0 @@
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# Copyright 2022, NXP
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# SPDX-License-Identifier: Apache-2.0
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DT_COMPAT_MCUX_RT_PINCTRL := nxp,mcux-rt-pinctrl
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DT_COMPAT_MCUX_RT11XX_PINCTRL := nxp,mcux-rt11xx-pinctrl
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config PINCTRL_MCUX_RT
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bool "Pin controller driver for MCUX RT1xxx MCUs"
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depends on SOC_SERIES_IMX_RT
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default $(dt_compat_enabled,$(DT_COMPAT_MCUX_RT_PINCTRL)) || \
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$(dt_compat_enabled,$(DT_COMPAT_MCUX_RT11XX_PINCTRL))
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help
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Enable pin controller driver for NXP RT1XXX series MCUs
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@ -4,12 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_mcux_rt_pinctrl
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#include <zephyr/drivers/pinctrl.h>
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#include <soc.h>
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#include <fsl_iomuxc.h>
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#include <fsl_gpio.h>
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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@ -23,6 +19,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uint32_t input_daisy = pins[i].pinmux.input_daisy;
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uint32_t config_register = pins[i].pinmux.config_register;
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uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags;
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#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) || defined(CONFIG_SOC_SERIES_IMX_RT11XX)
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volatile uint32_t *gpr_register =
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(volatile uint32_t *)pins[i].pinmux.gpr_register;
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if (gpr_register) {
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@ -34,14 +31,16 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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*gpr_register &= ~(0x1 << pins[i].pinmux.gpr_shift);
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}
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}
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IOMUXC_SetPinMux(mux_register, mux_mode, input_register,
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input_daisy, config_register,
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MCUX_RT_INPUT_ENABLE(pin_ctrl_flags));
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#endif
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*((volatile uint32_t *)mux_register) = IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) |
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IOMUXC_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags));
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if (input_register) {
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*((volatile uint32_t *)input_register) =
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IOMUXC_SELECT_INPUT_DAISY(input_daisy);
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}
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if (config_register) {
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IOMUXC_SetPinConfig(mux_register, mux_mode, input_register,
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input_daisy, config_register,
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pin_ctrl_flags & (~(0x1 << MCUX_RT_INPUT_ENABLE_SHIFT)));
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*((volatile uint32_t *)config_register) =
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pin_ctrl_flags & (~(0x1 << MCUX_IMX_INPUT_ENABLE_SHIFT));
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}
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@ -49,19 +48,22 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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return 0;
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}
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static int mcux_pinctrl_init(const struct device *dev)
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static int imx_pinctrl_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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#ifdef CONFIG_SOC_SERIES_IMX_RT
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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#ifdef CONFIG_SOC_SERIES_IMX_RT10XX
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CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
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CLOCK_EnableClock(kCLOCK_IomuxcGpr);
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#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX)
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CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr);
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#endif
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#endif /* CONFIG_SOC_SERIES_IMX_RT10XX */
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#elif defined(CONFIG_SOC_MIMX8MQ6)
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CLOCK_EnableClock(kCLOCK_Iomux);
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#endif /* CONFIG_SOC_SERIES_IMX_RT */
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return 0;
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}
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SYS_INIT(mcux_pinctrl_init, PRE_KERNEL_1, 0);
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SYS_INIT(imx_pinctrl_init, PRE_KERNEL_1, 0);
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@ -25,4 +25,9 @@ config HAS_IMX_EPIT
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help
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Set if the EPIT module is present in the SoC.
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config HAS_IMX_IOMUXC
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bool
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help
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Set if the IOMUXC module is present in the SoC.
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endif # HAS_IMX_HAL
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@ -116,6 +116,11 @@ config HAS_MCUX_IGPIO
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help
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Set if the iMX GPIO (IGPIO) module is present in the SoC.
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config HAS_MCUX_IOMUXC
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bool
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help
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Set if the iMX I/O mux controller (IOMUXC) is present in the SoC.
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config HAS_MCUX_LPI2C
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bool
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help
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@ -32,6 +32,10 @@ config GPIO_MCUX_IGPIO
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default y if HAS_MCUX_IGPIO
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depends on GPIO
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config PINCTRL_IMX
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default y if HAS_MCUX_IOMUXC
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depends on PINCTRL
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config ENTROPY_MCUX_TRNG
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default y if HAS_MCUX_TRNG
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depends on ENTROPY_GENERATOR
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@ -28,6 +28,7 @@ config SOC_MIMXRT1011
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select HAS_MCUX_GPC
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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config SOC_MIMXRT1015
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bool "SOC_MIMXRT1015"
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@ -51,6 +52,7 @@ config SOC_MIMXRT1015
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select HAS_MCUX_GPC
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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config SOC_MIMXRT1021
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bool "SOC_MIMXRT1021"
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@ -80,6 +82,7 @@ config SOC_MIMXRT1021
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select HAS_MCUX_GPC
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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config SOC_MIMXRT1024
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bool "SOC_MIMXRT1024"
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@ -109,6 +112,7 @@ config SOC_MIMXRT1024
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select HAS_MCUX_GPC
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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config SOC_MIMXRT1051
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bool "SOC_MIMXRT1051"
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@ -138,6 +142,7 @@ config SOC_MIMXRT1051
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select HAS_MCUX_GPC
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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config SOC_MIMXRT1052
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bool "SOC_MIMXRT1052"
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@ -171,6 +176,7 @@ config SOC_MIMXRT1052
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select HAS_MCUX_GPC
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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config SOC_MIMXRT1061
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bool "SOC_MIMXRT1061"
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@ -200,6 +206,7 @@ config SOC_MIMXRT1061
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select HAS_MCUX_GPC
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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config SOC_MIMXRT1062
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bool "SOC_MIMXRT1062"
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@ -235,6 +242,7 @@ config SOC_MIMXRT1062
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select HAS_MCUX_GPC
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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config SOC_MIMXRT1064
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bool "SOC_MIMXRT1064"
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@ -271,6 +279,7 @@ config SOC_MIMXRT1064
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select HAS_MCUX_GPC
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select HAS_MCUX_DCDC
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select HAS_MCUX_PMU
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select HAS_MCUX_IOMUXC
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config SOC_MIMXRT1176_CM7
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bool "SOC_MIMXRT1176_CM7"
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@ -309,6 +318,7 @@ config SOC_MIMXRT1176_CM7
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select HAS_MCUX_I2S
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select HAS_MCUX_USB_EHCI
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select HAS_MCUX_SRC_V2
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select HAS_MCUX_IOMUXC
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config SOC_MIMXRT1176_CM4
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bool "SOC_MIMXRT1176_CM4"
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select HAS_MCUX_GPC
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select HAS_MCUX_I2S
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select HAS_MCUX_SRC_V2
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select HAS_MCUX_IOMUXC
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config SOC_MIMXRT1166_CM7
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bool "SOC_MIMXRT1166_CM7"
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select HAS_MCUX_GPC
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select HAS_MCUX_USB_EHCI
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select HAS_MCUX_SRC_V2
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select HAS_MCUX_IOMUXC
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config SOC_MIMXRT1166_CM4
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select HAS_MCUX_ENET
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select HAS_MCUX_GPC
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select HAS_MCUX_SRC_V2
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select HAS_MCUX_IOMUXC
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endchoice
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@ -15,32 +15,32 @@
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extern "C" {
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#endif
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#define MCUX_RT_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT
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#define MCUX_RT_BIAS_PULL_DOWN_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT
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#define MCUX_RT_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT
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#define MCUX_RT_BIAS_BUS_HOLD_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT
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#define MCUX_RT_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT
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#define MCUX_RT_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT
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#define MCUX_RT_SPEED_SHIFT IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT
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#define MCUX_RT_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
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#define MCUX_RT_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT
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#define MCUX_RT_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
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#define MCUX_RT_INPUT_ENABLE(x) ((x >> MCUX_RT_INPUT_ENABLE_SHIFT) & 0x1)
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#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT
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#define MCUX_IMX_BIAS_PULL_DOWN_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT
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#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT
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#define MCUX_IMX_BIAS_BUS_HOLD_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT
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#define MCUX_IMX_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT
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#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT
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#define MCUX_IMX_SPEED_SHIFT IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT
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#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
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#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT
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#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
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#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
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#define Z_PINCTRL_MCUX_RT_PINCFG_INIT(node_id) \
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((DT_PROP(node_id, input_schmitt_enable) << MCUX_RT_INPUT_SCHMITT_ENABLE_SHIFT) | \
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#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \
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((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \
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IF_ENABLED(DT_PROP(node_id, bias_pull_up), (DT_ENUM_IDX(node_id, bias_pull_up_value) \
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<< MCUX_RT_BIAS_PULL_UP_SHIFT) |) \
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<< MCUX_IMX_BIAS_PULL_UP_SHIFT) |) \
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IF_ENABLED(DT_PROP(node_id, bias_pull_down), (DT_ENUM_IDX(node_id, bias_pull_down_value)\
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<< MCUX_RT_BIAS_PULL_DOWN_SHIFT) |) \
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((DT_PROP(node_id, bias_pull_down) | DT_PROP(node_id, bias_pull_up)) \
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<< MCUX_RT_BIAS_BUS_HOLD_SHIFT) | \
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((!DT_PROP(node_id, bias_disable)) << MCUX_RT_PULL_ENABLE_SHIFT) | \
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(DT_PROP(node_id, drive_open_drain) << MCUX_RT_DRIVE_OPEN_DRAIN_SHIFT) | \
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(DT_ENUM_IDX(node_id, nxp_speed) << MCUX_RT_SPEED_SHIFT) | \
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(DT_ENUM_IDX(node_id, drive_strength) << MCUX_RT_DRIVE_STRENGTH_SHIFT) | \
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(DT_ENUM_IDX(node_id, slew_rate) << MCUX_RT_SLEW_RATE_SHIFT) | \
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(DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT))
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<< MCUX_IMX_BIAS_PULL_DOWN_SHIFT) |) \
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((DT_PROP(node_id, bias_pull_down) | DT_PROP(node_id, bias_pull_up)) \
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<< MCUX_IMX_BIAS_BUS_HOLD_SHIFT) | \
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((!DT_PROP(node_id, bias_disable)) << MCUX_IMX_PULL_ENABLE_SHIFT) | \
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(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
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(DT_ENUM_IDX(node_id, nxp_speed) << MCUX_IMX_SPEED_SHIFT) | \
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(DT_ENUM_IDX(node_id, drive_strength) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \
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(DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
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(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT))
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/* This struct must be present. It is used by the mcux gpio driver */
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@ -63,7 +63,7 @@ struct pinctrl_soc_pin {
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typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
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/* This definition must be present. It is used by the mcux gpio driver */
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#define MCUX_RT_PINMUX(node_id) \
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#define MCUX_IMX_PINMUX(node_id) \
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{ \
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.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
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.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
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@ -79,12 +79,12 @@ typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
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}
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#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
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MCUX_RT_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
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MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
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#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
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{ \
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.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
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.pin_ctrl_flags = Z_PINCTRL_MCUX_RT_PINCFG_INIT(group_id), \
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#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
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{ \
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.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
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.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id), \
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},
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||||
|
||||
|
||||
|
|
|
@ -15,19 +15,19 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MCUX_RT_ODE_SHIFT 4
|
||||
#define MCUX_RT_PUS_SHIFT 3
|
||||
#define MCUX_RT_PUE_SHIFT 2
|
||||
#define MCUX_RT_DSE_SHIFT 1
|
||||
#define MCUX_RT_SRE_SHIFT 0
|
||||
#define MCUX_RT_PULL_SHIFT 2
|
||||
#define MCUX_RT_PULL_PULLDOWN 0x2
|
||||
#define MCUX_RT_PULL_PULLUP 0x1
|
||||
#define MCUX_RT_PDRV_SHIFT 1
|
||||
#define MCUX_RT_LPSR_ODE_SHIFT 5
|
||||
#define MCUX_RT_SNVS_ODE_SHIFT 6
|
||||
#define MCUX_RT_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
|
||||
#define MCUX_RT_INPUT_ENABLE(x) ((x >> MCUX_RT_INPUT_ENABLE_SHIFT) & 0x1)
|
||||
#define MCUX_IMX_ODE_SHIFT 4
|
||||
#define MCUX_IMX_PUS_SHIFT 3
|
||||
#define MCUX_IMX_PUE_SHIFT 2
|
||||
#define MCUX_IMX_DSE_SHIFT 1
|
||||
#define MCUX_IMX_SRE_SHIFT 0
|
||||
#define MCUX_IMX_PULL_SHIFT 2
|
||||
#define MCUX_IMX_PULL_PULLDOWN 0x2
|
||||
#define MCUX_IMX_PULL_PULLUP 0x1
|
||||
#define MCUX_IMX_PDRV_SHIFT 1
|
||||
#define MCUX_IMX_LPSR_ODE_SHIFT 5
|
||||
#define MCUX_IMX_SNVS_ODE_SHIFT 6
|
||||
#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
|
||||
#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
|
||||
|
||||
|
||||
/*
|
||||
|
@ -39,55 +39,55 @@ extern "C" {
|
|||
* pue_pus_snvs: in SNVS domain, shifted ode field
|
||||
*/
|
||||
|
||||
#define MCUX_RT_PUS_PUE 0
|
||||
#define MCUX_RT_PDRV_PULL 1
|
||||
#define MCUX_RT_LPSR 2
|
||||
#define MCUX_RT_SNVS 3
|
||||
#define MCUX_IMX_PUS_PUE 0
|
||||
#define MCUX_IMX_PDRV_PULL 1
|
||||
#define MCUX_IMX_LPSR 2
|
||||
#define MCUX_IMX_SNVS 3
|
||||
|
||||
/*
|
||||
* Macro for MCUX_RT_PULL_NOPULL, which needs to set field to 0x3 if two
|
||||
* Macro for MCUX_IMX_PULL_NOPULL, which needs to set field to 0x3 if two
|
||||
* properties are false
|
||||
*/
|
||||
#define MCUX_RT_NOPULL(node_id) \
|
||||
#define MCUX_IMX_NOPULL(node_id) \
|
||||
((0x2 & ((!DT_PROP(node_id, bias_pull_down) && !DT_PROP(node_id, bias_pull_up)) << 1)) |\
|
||||
(0x1 & ((!DT_PROP(node_id, bias_pull_down) && !DT_PROP(node_id, bias_pull_up)) << 0))) \
|
||||
|
||||
#define Z_PINCTRL_MCUX_RT_PDRV(node_id) \
|
||||
#define Z_PINCTRL_MCUX_IMX_PDRV(node_id) \
|
||||
IF_ENABLED(DT_PROP(node_id, bias_pull_down), \
|
||||
(MCUX_RT_PULL_PULLDOWN << MCUX_RT_PULL_SHIFT) |) \
|
||||
(MCUX_IMX_PULL_PULLDOWN << MCUX_IMX_PULL_SHIFT) |) \
|
||||
IF_ENABLED(DT_PROP(node_id, bias_pull_up), \
|
||||
(MCUX_RT_PULL_PULLUP << MCUX_RT_PULL_SHIFT) |) \
|
||||
(MCUX_RT_NOPULL(node_id) << MCUX_RT_PULL_SHIFT) | \
|
||||
(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_RT_PDRV_SHIFT) | \
|
||||
(DT_PROP(node_id, drive_open_drain) << MCUX_RT_ODE_SHIFT) | \
|
||||
(DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT)
|
||||
(MCUX_IMX_PULL_PULLUP << MCUX_IMX_PULL_SHIFT) |) \
|
||||
(MCUX_IMX_NOPULL(node_id) << MCUX_IMX_PULL_SHIFT) | \
|
||||
(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_PDRV_SHIFT) | \
|
||||
(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_ODE_SHIFT) | \
|
||||
(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)
|
||||
|
||||
#define Z_PINCTRL_MCUX_RT_PUE_PUS(node_id) \
|
||||
(DT_PROP(node_id, bias_pull_up) << MCUX_RT_PUS_SHIFT) | \
|
||||
#define Z_PINCTRL_MCUX_IMX_PUE_PUS(node_id) \
|
||||
(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_PUS_SHIFT) | \
|
||||
((DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down)) \
|
||||
<< MCUX_RT_PUE_SHIFT) | \
|
||||
(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_RT_DSE_SHIFT) | \
|
||||
(DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_RT_SRE_SHIFT) | \
|
||||
(DT_PROP(node_id, drive_open_drain) << MCUX_RT_ODE_SHIFT) | \
|
||||
(DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT)
|
||||
<< MCUX_IMX_PUE_SHIFT) | \
|
||||
(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_DSE_SHIFT) | \
|
||||
(DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_IMX_SRE_SHIFT) | \
|
||||
(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_ODE_SHIFT) | \
|
||||
(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)
|
||||
|
||||
#define Z_PINCTRL_MCUX_RT_LPSR(node_id) \
|
||||
(DT_PROP(node_id, bias_pull_up) << MCUX_RT_PUS_SHIFT) | \
|
||||
#define Z_PINCTRL_MCUX_IMX_LPSR(node_id) \
|
||||
(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_PUS_SHIFT) | \
|
||||
((DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down)) \
|
||||
<< MCUX_RT_PUE_SHIFT) | \
|
||||
(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_RT_DSE_SHIFT) | \
|
||||
(DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_RT_SRE_SHIFT) | \
|
||||
(DT_PROP(node_id, drive_open_drain) << MCUX_RT_LPSR_ODE_SHIFT) | \
|
||||
(DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT)
|
||||
<< MCUX_IMX_PUE_SHIFT) | \
|
||||
(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_DSE_SHIFT) | \
|
||||
(DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_IMX_SRE_SHIFT) | \
|
||||
(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_LPSR_ODE_SHIFT) | \
|
||||
(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)
|
||||
|
||||
#define Z_PINCTRL_MCUX_RT_SNVS(node_id) \
|
||||
(DT_PROP(node_id, bias_pull_up) << MCUX_RT_PUS_SHIFT) | \
|
||||
#define Z_PINCTRL_MCUX_IMX_SNVS(node_id) \
|
||||
(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_PUS_SHIFT) | \
|
||||
((DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down)) \
|
||||
<< MCUX_RT_PUE_SHIFT) | \
|
||||
(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_RT_DSE_SHIFT) | \
|
||||
(DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_RT_SRE_SHIFT) | \
|
||||
(DT_PROP(node_id, drive_open_drain) << MCUX_RT_SNVS_ODE_SHIFT) | \
|
||||
(DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT)
|
||||
<< MCUX_IMX_PUE_SHIFT) | \
|
||||
(DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_DSE_SHIFT) | \
|
||||
(DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_IMX_SRE_SHIFT) | \
|
||||
(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_SNVS_ODE_SHIFT) | \
|
||||
(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)
|
||||
|
||||
/* This struct must be present. It is used by the mcux gpio driver */
|
||||
struct pinctrl_soc_pinmux {
|
||||
|
@ -113,7 +113,7 @@ struct pinctrl_soc_pin {
|
|||
typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
||||
|
||||
/* This definition must be present. It is used by the mcux gpio driver */
|
||||
#define MCUX_RT_PINMUX(node_id) \
|
||||
#define MCUX_IMX_PINMUX(node_id) \
|
||||
{ \
|
||||
.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
|
||||
.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
|
||||
|
@ -133,19 +133,19 @@ typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
|
|||
}
|
||||
|
||||
#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
|
||||
MCUX_RT_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
|
||||
MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
|
||||
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
|
||||
{ \
|
||||
.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
|
||||
IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pue), \
|
||||
(.pin_ctrl_flags = Z_PINCTRL_MCUX_RT_PUE_PUS(group_id),)) \
|
||||
IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pdrv), \
|
||||
(.pin_ctrl_flags = Z_PINCTRL_MCUX_RT_PDRV(group_id),)) \
|
||||
IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_lpsr), \
|
||||
(.pin_ctrl_flags = Z_PINCTRL_MCUX_RT_LPSR(group_id),)) \
|
||||
IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_snvs), \
|
||||
(.pin_ctrl_flags = Z_PINCTRL_MCUX_RT_SNVS(group_id),)) \
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
|
||||
{ \
|
||||
.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
|
||||
IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pue), \
|
||||
(.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PUE_PUS(group_id),)) \
|
||||
IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pdrv), \
|
||||
(.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PDRV(group_id),)) \
|
||||
IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_lpsr), \
|
||||
(.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_LPSR(group_id),)) \
|
||||
IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_snvs), \
|
||||
(.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_SNVS(group_id),)) \
|
||||
},
|
||||
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue