riscv: linker: replace DT_FLASH_{BASE_ADDRESS,SIZE} with new macros
The riscv linker scripts utilize DT_FLASH_BASE_ADDRESS and DT_FLASH_SIZE, as we want to phase out the old generator we need to replace these defines with macros from devicetree.h. We support two flash configurations at this point, either a QSPI flash like on the hifive board or a SoC flash like on the rv32m1_vega. We update the linker scripts to check the compat of the zephyr,flash node and based on if its 'jedec,spi-nor' or 'soc-nv-flash' we determine how to extract the "flash" base address and size. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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3afd12c146
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2 changed files with 16 additions and 3 deletions
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@ -12,6 +12,7 @@
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*/
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#include <soc.h>
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#include <devicetree.h>
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#include <autoconf.h>
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#include <linker/sections.h>
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@ -33,7 +34,19 @@
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MEMORY
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{
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#ifdef CONFIG_XIP
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ROM (rx) : ORIGIN = DT_FLASH_BASE_ADDRESS, LENGTH = KB(DT_FLASH_SIZE)
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#if DT_NODE_HAS_COMPAT(DT_CHOSEN(zephyr_flash), soc_nv_flash)
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#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
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#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
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#elif DT_NODE_HAS_COMPAT(DT_CHOSEN(zephyr_flash), jedec_spi_nor)
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/* For jedec,spi-nor we expect the spi controller to memory map the flash
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* and for that mapping to be the second register property of the spi
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* controller.
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*/
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#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))
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#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)
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#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)
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#endif
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ROM (rx) : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
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#endif
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RAM (rwx) : ORIGIN = CONFIG_SRAM_BASE_ADDRESS, LENGTH = KB(CONFIG_SRAM_SIZE)
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/* Used by and documented in include/linker/intlist.ld */
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@ -49,8 +49,8 @@
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#else
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#define ROM_BASE DT_FLASH_BASE_ADDRESS
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#define ROM_SIZE (KB(DT_FLASH_SIZE) - VECTOR_SIZE)
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#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
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#define ROM_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) - VECTOR_SIZE)
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#define VECTOR_BASE (ROM_BASE + ROM_SIZE)
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