riscv: Use IRQ vector table for vectored mode
For vectored interrupts use the generated IRQ vector table instead of relying on a custom-generated table. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
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4 changed files with 17 additions and 16 deletions
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@ -421,6 +421,7 @@ config ARCH_IRQ_VECTOR_TABLE_ALIGN
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choice IRQ_VECTOR_TABLE_TYPE
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prompt "IRQ vector table type"
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depends on GEN_IRQ_VECTOR_TABLE
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default IRQ_VECTOR_TABLE_JUMP_BY_CODE if RISCV
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default IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS
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config IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS
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@ -199,6 +199,12 @@ config CMSIS_THREAD_MAX_STACK_SIZE
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config CMSIS_V2_THREAD_MAX_STACK_SIZE
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default 1024 if 64BIT
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config ARCH_IRQ_VECTOR_TABLE_ALIGN
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default 256
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config GEN_IRQ_VECTOR_TABLE
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select RISCV_MTVEC_VECTORED_MODE if SOC_FAMILY_RISCV_PRIVILEGE
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rsource "Kconfig.isa"
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rsource "Kconfig.core"
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@ -169,6 +169,10 @@
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extern "C" {
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#endif
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#ifdef CONFIG_IRQ_VECTOR_TABLE_JUMP_BY_CODE
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#define ARCH_IRQ_VECTOR_JUMP_CODE(v) "j " STRINGIFY(v)
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#endif
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/* Kernel macros for memory attribution
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* (access permissions and cache-ability).
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*
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@ -28,15 +28,15 @@ SECTION_FUNC(vectors, __start)
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#if defined(CONFIG_RISCV_MTVEC_VECTORED_MODE)
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/*
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* Set mtvec (Machine Trap-Vector Base-Address Register)
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* to __ivt (interrupt vector table). Add 1 to base
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* address of __ivt to indicate that vectored mode
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* to _irq_vector_table (interrupt vector table). Add 1 to base
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* address of _irq_vector_table to indicate that vectored mode
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* is used (LSB = 0x1). CPU will mask the LSB out of
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* the address so that base address of __ivt is used.
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* the address so that base address of _irq_vector_table is used.
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*
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* NOTE: __ivt is 256-byte aligned. Incorrect alignment
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* of __ivt breaks this code.
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* NOTE: _irq_vector_table is 256-byte aligned. Incorrect alignment
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* of _irq_vector_table breaks this code.
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*/
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la t0, __ivt /* Load address of interrupt vector table */
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la t0, _irq_vector_table /* Load address of interrupt vector table */
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addi t0, t0, 1 /* Enable vectored mode by setting LSB */
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/* MTVEC_DIRECT_MODE */
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@ -52,13 +52,3 @@ SECTION_FUNC(vectors, __start)
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/* Jump to __reset */
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tail __reset
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#if defined(CONFIG_RISCV_MTVEC_VECTORED_MODE)
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SECTION_FUNC(reset, __ivt)
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.option push
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.option norvc
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.balign 0x100 /* must be 256 byte aligned per specification */
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.rept (CONFIG_NUM_IRQS)
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j _isr_wrapper
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.endr
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#endif
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