soc: nxp: k2x: move clk divider options to device tree
Use kinetis SIM clock divider options set in device tree instead of kconfig Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
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3 changed files with 38 additions and 33 deletions
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@ -83,8 +83,35 @@
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compatible = "nxp,kinetis-sim";
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reg = <0x40047000 0x1060>;
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label = "SIM";
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#clock-cells = <3>;
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core_clk {
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compatible = "fixed-factor-clock";
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clocks = <&mcg KINETIS_MCG_OUT_CLK>;
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clock-div = <1>;
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#clock-cells = <0>;
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};
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bus_clk {
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compatible = "fixed-factor-clock";
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clocks = <&mcg KINETIS_MCG_OUT_CLK>;
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clock-div = <2>;
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#clock-cells = <0>;
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};
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flexbus_clk {
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compatible = "fixed-factor-clock";
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clocks = <&mcg KINETIS_MCG_OUT_CLK>;
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clock-div = <3>;
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#clock-cells = <0>;
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};
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flash_clk {
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compatible = "fixed-factor-clock";
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clocks = <&mcg KINETIS_MCG_OUT_CLK>;
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clock-div = <3>;
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#clock-cells = <0>;
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};
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};
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ftfe: flash-controller@40020000 {
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@ -43,32 +43,4 @@ config SOC_PART_NUMBER_KINETIS_K2X
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that you should not set directly. The part number selection choice defines
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the default value for this string.
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config K22_CORE_CLOCK_DIVIDER
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int "Freescale K22 core clock divider"
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default 1
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help
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This option specifies the divide value for the K22 processor core clock
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from the system clock.
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config K22_BUS_CLOCK_DIVIDER
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int "Freescale K22 bus clock divider"
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default 2
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help
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This option specifies the divide value for the K22 bus clock from the
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system clock.
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config K22_FLEXBUS_CLOCK_DIVIDER
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int "Freescale K22 FlexBus clock divider"
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default 3
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help
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This option specifies the divide value for the K22 FlexBus clock from the
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system clock.
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config K22_FLASH_CLOCK_DIVIDER
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int "Freescale K22 flash clock divider"
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default 3
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help
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This option specifies the divide value for the K64 flash clock from the
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system clock.
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endif # SOC_SERIES_KINETIS_K2X
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@ -27,6 +27,12 @@
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#define TIMESRC_OSCERCLK (2)
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#define CLOCK_NODEID(clk) \
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DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
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#define CLOCK_DIVIDER(clk) \
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DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
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static const osc_config_t oscConfig = {
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.freq = CONFIG_OSC_XTAL0_FREQ,
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.capLoad = 0,
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@ -56,10 +62,10 @@ static const mcg_pll_config_t pll0Config = {
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static const sim_clock_config_t simConfig = {
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.pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
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.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
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.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CONFIG_K22_CORE_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV2(CONFIG_K22_BUS_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV3(CONFIG_K22_FLEXBUS_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV4(CONFIG_K22_FLASH_CLOCK_DIVIDER - 1),
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.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
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SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
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SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |
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SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
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};
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/**
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