drivers: gpio: ite_it8xxx2: enable more gpio groups
This change enables A, C, D, E, G, H, I, J, K, and L groups, and fix gpio interrupt function. This change also pull (and rename) dt-bindings/irq.h to dt-bindings/interrupt-controller/ite-intc.h, because it is chip-specific. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Ifee039981c2cc4cf5980e663702a9921e629fc1e
This commit is contained in:
Dino Li
Anas Nashif
parent
d93297b3d0
commit
0ab51ff657
10 changed files with 783 additions and 687 deletions
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@ -23,12 +23,6 @@
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&adc0 {
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status = "okay";
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};
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&gpiob {
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status = "okay";
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};
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&gpiof {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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@ -7,112 +7,42 @@
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#include <errno.h>
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#include <device.h>
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#include <drivers/gpio.h>
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#include <dt-bindings/interrupt-controller/ite-intc.h>
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#include <zephyr/types.h>
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#include <sys/util.h>
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#include <string.h>
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#include <logging/log.h>
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#include "gpio_utils.h"
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#define DT_DRV_COMPAT ite_it8xxx2_gpio
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#define GPIO_LOW 0
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#define GPIO_HIGH 1
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#define NUM_IO_MAX 8
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#define CURR_SUPP_GPIO_SET 2
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#define DT_DRV_COMPAT ite_it8xxx2_gpio
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/*
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* this two function be used to enable/disable specific irq interrupt
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*/
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extern void ite_intc_irq_enable(unsigned int irq);
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extern void ite_intc_irq_disable(unsigned int irq);
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#define GPIO_GPDRB (DT_REG_ADDR_BY_IDX(DT_NODELABEL(gpiob), 0))
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#define GPIO_GPDRF (DT_REG_ADDR_BY_IDX(DT_NODELABEL(gpiof), 0))
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#define GPIO_GPDRM (DT_REG_ADDR_BY_IDX(DT_NODELABEL(gpiom), 0))
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#define GPCR_OFFSET 0x10
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#define GPIO_DIR_INPUT 0x80
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#define GPIO_DIR_OUTPUT 0x40
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struct gpio_ite_wui {
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volatile uint8_t *reg_addr;
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volatile uint8_t *clear_addr;
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volatile uint8_t *bothedge_addr;
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uint32_t pin;
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uint32_t irq;
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};
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static const struct gpio_ite_wui GPIO_GPDRB_wui[NUM_IO_MAX] = {
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{ &WUEMR10, &WUESR10, &WUBEMR10, BIT(5), 106 }, /* gpb0, */
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{ &WUEMR10, &WUESR10, &WUBEMR10, BIT(6), 107 }, /* gpb1, */
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{ &WUEMR8, &WUESR8, &WUBEMR8, BIT(4), 92 }, /* gpb2, */
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{ &WUEMR10, &WUESR10, &WUBEMR10, BIT(7), 108 }, /* gpb3, */
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{ &WUEMR9, &WUESR9, &WUBEMR9, BIT(6), 99 }, /* gpb4, */
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{ &WUEMR11, &WUESR11, &WUBEMR11, BIT(0), 109 }, /* gpb5, */
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{ &WUEMR11, &WUESR11, &WUBEMR11, BIT(1), 110 }, /* gpb6, */
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{ &WUEMR11, &WUESR11, &WUBEMR11, BIT(2), 111 }, /* gpb7, */
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};
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static const struct gpio_ite_wui GPIO_GPDRF_wui[NUM_IO_MAX] = {
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{ &WUEMR10, &WUESR10, &WUBEMR10, BIT(0), 101 }, /* gpf0, */
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{ &WUEMR10, &WUESR10, &WUBEMR10, BIT(1), 102 }, /* gpf1, */
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{ &WUEMR10, &WUESR10, &WUBEMR10, BIT(2), 103 }, /* gpf2, */
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{ &WUEMR10, &WUESR10, &WUBEMR10, BIT(3), 104 }, /* gpf3, */
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{ &WUEMR6, &WUESR6, &WUBEMR6, BIT(4), 52 }, /* gpf4, */
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{ &WUEMR6, &WUESR6, &WUBEMR6, BIT(5), 53 }, /* gpf5, */
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{ &WUEMR6, &WUESR6, &WUBEMR6, BIT(6), 54 }, /* gpf6, */
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{ &WUEMR6, &WUESR6, &WUBEMR6, BIT(7), 55 }, /* gpf7, */
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};
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/* struct gpio_ite_reg_table is record different gpio port's register set
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* base_addr: base address of gpio set
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* wui[]: wui register group
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*/
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struct gpio_ite_reg_table {
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uint32_t base_addr;
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const struct gpio_ite_wui *wui;
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};
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struct gpio_ite_reg_table gpiox_reg[CURR_SUPP_GPIO_SET] = {
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{GPIO_GPDRB, GPIO_GPDRB_wui}, /* GPIO GROPU B */
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{GPIO_GPDRF, GPIO_GPDRF_wui}, /* GPIO GROPU F */
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};
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/* edge/level trigger register */
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static volatile uint8_t *const reg_ielmr[] = {
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&IELMR0, &IELMR1, &IELMR2, &IELMR3,
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&IELMR4, &IELMR5, &IELMR6, &IELMR7,
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&IELMR8, &IELMR9, &IELMR10, &IELMR11,
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&IELMR12, &IELMR13, &IELMR14, &IELMR15,
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&IELMR16, &IELMR17, &IELMR18, &IELMR19,
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&IELMR20
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};
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/* high/low trigger register */
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static volatile uint8_t *const reg_ipolr[] = {
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&IPOLR0, &IPOLR1, &IPOLR2, &IPOLR3,
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&IPOLR4, &IPOLR5, &IPOLR6, &IPOLR7,
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&IPOLR8, &IPOLR9, &IPOLR10, &IPOLR11,
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&IPOLR12, &IPOLR13, &IPOLR14, &IPOLR15,
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&IPOLR16, &IPOLR17, &IPOLR18, &IPOLR19,
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&IPOLR20
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};
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#define GPCR_PORT_PIN_MODE_INPUT BIT(7)
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#define GPCR_PORT_PIN_MODE_OUTPUT BIT(6)
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#define GPCR_PORT_PIN_MODE_PULLUP BIT(2)
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#define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1)
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/*
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* Strcture gpio_ite_cfg is about the setting of gpio
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* this config will be used at initial time
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*/
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struct gpio_ite_cfg {
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uint32_t reg_addr; /* gpio register base address */
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uint8_t gpio_irq[8]; /* gpio's irq */
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/* gpio port data register (bit mapping to pin) */
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uintptr_t reg_gpdr;
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/* gpio port control register (byte mapping to pin) */
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uintptr_t reg_gpcr;
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/* gpio port data mirror register (bit mapping to pin) */
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uintptr_t reg_gpdmr;
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/* gpio port output type register (bit mapping to pin) */
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uintptr_t reg_gpotr;
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uint8_t ngpios;
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/* gpio's irq */
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uint8_t gpio_irq[8];
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};
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/*
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* Strcture gpio_ite_data is about callback function
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*/
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/* Strcture gpio_ite_data is about callback function */
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struct gpio_ite_data {
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struct gpio_driver_data common;
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sys_slist_t callbacks;
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uint32_t pin_callback_enables;
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};
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/* dev macros for GPIO */
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@ -123,139 +53,308 @@ struct gpio_ite_data {
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((const struct gpio_ite_cfg *)(dev)->config)
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/**
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* functions for bit / port access
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* Convert wake-up controller (WUC) group to the corresponding wake-up edge
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* sense register (WUESR). Return pointer to the register.
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*
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* @param grp WUC group.
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*
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* @return Pointer to corresponding WUESR register.
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*/
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static inline void set_bit(const struct gpio_ite_cfg *config,
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uint8_t bit, bool val)
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static volatile uint8_t *wuesr(uint8_t grp)
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{
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uint8_t regv, new_regv;
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regv = ite_read(config->reg_addr, 1);
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new_regv = (regv & ~BIT(bit)) | (val << bit);
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ite_write(config->reg_addr, 1, new_regv);
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/*
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* From WUESR1-WUESR4, the address increases by ones. From WUESR5 on
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* the address increases by fours.
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*/
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return (grp <= 4) ?
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(volatile uint8_t *)(IT8XXX2_WUC_WUESR1 + grp-1) :
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(volatile uint8_t *)(IT8XXX2_WUC_WUESR5 + 4*(grp-5));
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}
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static inline uint8_t get_bit(const struct gpio_ite_cfg *config, uint8_t bit)
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/**
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* Convert wake-up controller (WUC) group to the corresponding wake-up edge
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* mode register (WUEMR). Return pointer to the register.
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*
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* @param grp WUC group.
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*
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* @return Pointer to corresponding WUEMR register.
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*/
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static volatile uint8_t *wuemr(uint8_t grp)
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{
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uint8_t regv = ite_read(config->reg_addr, 1);
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return !!(regv & BIT(bit));
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/*
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* From WUEMR1-WUEMR4, the address increases by ones. From WUEMR5 on
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* the address increases by fours.
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*/
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return (grp <= 4) ?
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(volatile uint8_t *)(IT8XXX2_WUC_WUEMR1 + grp-1) :
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(volatile uint8_t *)(IT8XXX2_WUC_WUEMR5 + 4*(grp-5));
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}
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static inline void set_port(const struct gpio_ite_cfg *config, uint8_t value)
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/**
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* Convert wake-up controller (WUC) group to the corresponding wake-up both edge
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* mode register (WUBEMR). Return pointer to the register.
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*
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* @param grp WUC group.
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*
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* @return Pointer to corresponding WUBEMR register.
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*/
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static volatile uint8_t *wubemr(uint8_t grp)
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{
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ite_write(config->reg_addr, 1, value);
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/*
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* From WUBEMR1-WUBEMR4, the address increases by ones. From WUBEMR5 on
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* the address increases by fours.
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*/
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return (grp <= 4) ?
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(volatile uint8_t *)(IT8XXX2_WUC_WUBEMR1 + grp-1) :
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(volatile uint8_t *)(IT8XXX2_WUC_WUBEMR5 + 4*(grp-5));
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}
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static inline uint8_t get_port(const struct gpio_ite_cfg *config)
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{
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uint8_t regv = ite_read(config->reg_addr, 1);
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return regv;
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}
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/*
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* Array to store the corresponding GPIO WUC group and mask
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* for each WUC interrupt. This allows GPIO interrupts coming in through WUC
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* to easily identify which pin caused the interrupt.
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*/
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static const struct {
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uint8_t gpio_mask;
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uint8_t wuc_group;
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uint8_t wuc_mask;
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} gpio_irqs[] = {
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/* irq gpio_mask, wuc_group, wuc_mask */
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[IT8XXX2_IRQ_WU20] = {BIT(0), 2, BIT(0)},
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[IT8XXX2_IRQ_WU21] = {BIT(1), 2, BIT(1)},
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[IT8XXX2_IRQ_WU22] = {BIT(4), 2, BIT(2)},
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[IT8XXX2_IRQ_WU23] = {BIT(6), 2, BIT(3)},
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[IT8XXX2_IRQ_WU24] = {BIT(2), 2, BIT(4)},
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[IT8XXX2_IRQ_WU40] = {BIT(5), 4, BIT(0)},
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[IT8XXX2_IRQ_WU45] = {BIT(6), 4, BIT(5)},
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[IT8XXX2_IRQ_WU46] = {BIT(7), 4, BIT(6)},
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[IT8XXX2_IRQ_WU50] = {BIT(0), 5, BIT(0)},
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[IT8XXX2_IRQ_WU51] = {BIT(1), 5, BIT(1)},
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[IT8XXX2_IRQ_WU52] = {BIT(2), 5, BIT(2)},
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[IT8XXX2_IRQ_WU53] = {BIT(3), 5, BIT(3)},
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[IT8XXX2_IRQ_WU54] = {BIT(4), 5, BIT(4)},
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[IT8XXX2_IRQ_WU55] = {BIT(5), 5, BIT(5)},
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[IT8XXX2_IRQ_WU56] = {BIT(6), 5, BIT(6)},
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[IT8XXX2_IRQ_WU57] = {BIT(7), 5, BIT(7)},
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[IT8XXX2_IRQ_WU60] = {BIT(0), 6, BIT(0)},
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[IT8XXX2_IRQ_WU61] = {BIT(1), 6, BIT(1)},
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[IT8XXX2_IRQ_WU62] = {BIT(2), 6, BIT(2)},
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[IT8XXX2_IRQ_WU63] = {BIT(3), 6, BIT(3)},
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[IT8XXX2_IRQ_WU64] = {BIT(4), 6, BIT(4)},
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[IT8XXX2_IRQ_WU65] = {BIT(5), 6, BIT(5)},
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[IT8XXX2_IRQ_WU65] = {BIT(6), 6, BIT(6)},
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[IT8XXX2_IRQ_WU67] = {BIT(7), 6, BIT(7)},
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[IT8XXX2_IRQ_WU70] = {BIT(0), 7, BIT(0)},
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[IT8XXX2_IRQ_WU71] = {BIT(1), 7, BIT(1)},
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[IT8XXX2_IRQ_WU72] = {BIT(2), 7, BIT(2)},
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[IT8XXX2_IRQ_WU73] = {BIT(3), 7, BIT(3)},
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[IT8XXX2_IRQ_WU74] = {BIT(4), 7, BIT(4)},
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[IT8XXX2_IRQ_WU75] = {BIT(5), 7, BIT(5)},
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[IT8XXX2_IRQ_WU76] = {BIT(6), 7, BIT(6)},
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[IT8XXX2_IRQ_WU77] = {BIT(7), 7, BIT(7)},
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[IT8XXX2_IRQ_WU80] = {BIT(3), 8, BIT(0)},
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[IT8XXX2_IRQ_WU81] = {BIT(4), 8, BIT(1)},
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[IT8XXX2_IRQ_WU82] = {BIT(5), 8, BIT(2)},
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[IT8XXX2_IRQ_WU83] = {BIT(6), 8, BIT(3)},
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[IT8XXX2_IRQ_WU84] = {BIT(2), 8, BIT(4)},
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[IT8XXX2_IRQ_WU85] = {BIT(0), 8, BIT(5)},
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[IT8XXX2_IRQ_WU86] = {BIT(7), 8, BIT(6)},
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[IT8XXX2_IRQ_WU87] = {BIT(7), 8, BIT(7)},
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[IT8XXX2_IRQ_WU88] = {BIT(4), 9, BIT(0)},
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[IT8XXX2_IRQ_WU89] = {BIT(5), 9, BIT(1)},
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[IT8XXX2_IRQ_WU90] = {BIT(6), 9, BIT(2)},
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[IT8XXX2_IRQ_WU91] = {BIT(0), 9, BIT(3)},
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[IT8XXX2_IRQ_WU92] = {BIT(1), 9, BIT(4)},
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[IT8XXX2_IRQ_WU93] = {BIT(2), 9, BIT(5)},
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[IT8XXX2_IRQ_WU94] = {BIT(4), 9, BIT(6)},
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[IT8XXX2_IRQ_WU95] = {BIT(2), 9, BIT(7)},
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[IT8XXX2_IRQ_WU96] = {BIT(0), 10, BIT(0)},
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[IT8XXX2_IRQ_WU97] = {BIT(1), 10, BIT(1)},
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[IT8XXX2_IRQ_WU98] = {BIT(2), 10, BIT(2)},
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[IT8XXX2_IRQ_WU99] = {BIT(3), 10, BIT(3)},
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[IT8XXX2_IRQ_WU100] = {BIT(7), 10, BIT(4)},
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[IT8XXX2_IRQ_WU101] = {BIT(0), 10, BIT(5)},
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[IT8XXX2_IRQ_WU102] = {BIT(1), 10, BIT(6)},
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[IT8XXX2_IRQ_WU103] = {BIT(3), 10, BIT(7)},
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[IT8XXX2_IRQ_WU104] = {BIT(5), 11, BIT(0)},
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[IT8XXX2_IRQ_WU105] = {BIT(6), 11, BIT(1)},
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[IT8XXX2_IRQ_WU106] = {BIT(7), 11, BIT(2)},
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[IT8XXX2_IRQ_WU107] = {BIT(1), 11, BIT(3)},
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[IT8XXX2_IRQ_WU108] = {BIT(3), 11, BIT(4)},
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[IT8XXX2_IRQ_WU109] = {BIT(5), 11, BIT(5)},
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[IT8XXX2_IRQ_WU110] = {BIT(3), 11, BIT(6)},
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[IT8XXX2_IRQ_WU111] = {BIT(4), 11, BIT(7)},
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[IT8XXX2_IRQ_WU112] = {BIT(5), 12, BIT(0)},
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[IT8XXX2_IRQ_WU113] = {BIT(6), 12, BIT(1)},
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[IT8XXX2_IRQ_WU114] = {BIT(4), 12, BIT(2)},
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[IT8XXX2_IRQ_WU115] = {BIT(0), 12, BIT(3)},
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[IT8XXX2_IRQ_WU116] = {BIT(1), 12, BIT(4)},
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[IT8XXX2_IRQ_WU117] = {BIT(2), 12, BIT(5)},
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[IT8XXX2_IRQ_WU118] = {BIT(6), 12, BIT(6)},
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[IT8XXX2_IRQ_WU119] = {BIT(0), 12, BIT(7)},
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[IT8XXX2_IRQ_WU120] = {BIT(1), 13, BIT(0)},
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[IT8XXX2_IRQ_WU121] = {BIT(2), 13, BIT(1)},
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[IT8XXX2_IRQ_WU122] = {BIT(3), 13, BIT(2)},
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[IT8XXX2_IRQ_WU123] = {BIT(3), 13, BIT(3)},
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[IT8XXX2_IRQ_WU124] = {BIT(4), 13, BIT(4)},
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[IT8XXX2_IRQ_WU125] = {BIT(5), 13, BIT(5)},
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[IT8XXX2_IRQ_WU126] = {BIT(7), 13, BIT(6)},
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[IT8XXX2_IRQ_WU128] = {BIT(0), 14, BIT(0)},
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[IT8XXX2_IRQ_WU129] = {BIT(1), 14, BIT(1)},
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[IT8XXX2_IRQ_WU130] = {BIT(2), 14, BIT(2)},
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[IT8XXX2_IRQ_WU131] = {BIT(3), 14, BIT(3)},
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[IT8XXX2_IRQ_WU132] = {BIT(4), 14, BIT(4)},
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[IT8XXX2_IRQ_WU133] = {BIT(5), 14, BIT(5)},
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[IT8XXX2_IRQ_WU134] = {BIT(6), 14, BIT(6)},
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[IT8XXX2_IRQ_WU135] = {BIT(7), 14, BIT(7)},
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[IT8XXX2_IRQ_WU136] = {BIT(0), 15, BIT(0)},
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[IT8XXX2_IRQ_WU137] = {BIT(1), 15, BIT(1)},
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[IT8XXX2_IRQ_WU138] = {BIT(2), 15, BIT(2)},
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[IT8XXX2_IRQ_WU139] = {BIT(3), 15, BIT(3)},
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[IT8XXX2_IRQ_WU140] = {BIT(4), 15, BIT(4)},
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[IT8XXX2_IRQ_WU141] = {BIT(5), 15, BIT(5)},
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[IT8XXX2_IRQ_WU142] = {BIT(6), 15, BIT(6)},
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[IT8XXX2_IRQ_WU143] = {BIT(7), 15, BIT(7)},
|
||||
[IT8XXX2_IRQ_WU144] = {BIT(0), 16, BIT(0)},
|
||||
[IT8XXX2_IRQ_WU145] = {BIT(1), 16, BIT(1)},
|
||||
[IT8XXX2_IRQ_WU146] = {BIT(2), 16, BIT(2)},
|
||||
[IT8XXX2_IRQ_WU147] = {BIT(3), 16, BIT(3)},
|
||||
[IT8XXX2_IRQ_WU148] = {BIT(4), 16, BIT(4)},
|
||||
[IT8XXX2_IRQ_WU149] = {BIT(5), 16, BIT(5)},
|
||||
[IT8XXX2_IRQ_WU150] = {BIT(6), 16, BIT(6)},
|
||||
[IT8XXX2_IRQ_COUNT] = { 0, 0, 0},
|
||||
};
|
||||
BUILD_ASSERT(ARRAY_SIZE(gpio_irqs) == IT8XXX2_IRQ_COUNT + 1);
|
||||
|
||||
/**
|
||||
* Driver functions
|
||||
*/
|
||||
static int gpio_ite_configure(const struct device *dev,
|
||||
gpio_pin_t pin, gpio_flags_t flags)
|
||||
gpio_pin_t pin,
|
||||
gpio_flags_t flags)
|
||||
{
|
||||
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
|
||||
unsigned int gpcr_offset = GPCR_OFFSET;
|
||||
uint32_t gpcr_reg;
|
||||
uint32_t gpcr_reg_addr;
|
||||
|
||||
/* counting the gpio control register's base address */
|
||||
gpcr_reg = ((gpio_config->reg_addr & 0xff) - 1) * NUM_IO_MAX
|
||||
+ gpcr_offset;
|
||||
gpcr_reg_addr = gpcr_reg | (gpio_config->reg_addr & 0xffffff00);
|
||||
if (!(flags & GPIO_SINGLE_ENDED)) {
|
||||
/* Pin open-source/open-drain is not supported */
|
||||
return -ENOTSUP;
|
||||
}
|
||||
if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) {
|
||||
/* Pin cannot be configured as input and output */
|
||||
return -ENOTSUP;
|
||||
} else if (!(flags & (GPIO_INPUT | GPIO_OUTPUT))) {
|
||||
/* Pin has to be configuread as input or output */
|
||||
return -ENOTSUP;
|
||||
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
|
||||
volatile uint8_t *reg_gpcr = (uint8_t *)(gpio_config->reg_gpcr + pin);
|
||||
volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr;
|
||||
uint8_t mask = BIT(pin);
|
||||
|
||||
if (pin >= gpio_config->ngpios) {
|
||||
printk("Invalid GPIO pin! (%s%d)\n", dev->name, pin);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Select open drain first, so that we don't glitch the signal
|
||||
* when changing the line to an output.
|
||||
*/
|
||||
if (flags & GPIO_OPEN_DRAIN)
|
||||
*reg_gpotr |= mask;
|
||||
else
|
||||
*reg_gpotr &= ~mask;
|
||||
|
||||
/* If output, set level before changing type to an output. */
|
||||
if (flags & GPIO_OUTPUT) {
|
||||
if (flags & GPIO_OUTPUT_INIT_HIGH) {
|
||||
set_bit(gpio_config, pin, GPIO_HIGH);
|
||||
} else if (flags & GPIO_OUTPUT_INIT_LOW) {
|
||||
set_bit(gpio_config, pin, GPIO_LOW);
|
||||
}
|
||||
ite_write(gpcr_reg_addr + pin, 1, GPIO_DIR_OUTPUT);
|
||||
} else {
|
||||
if ((flags & GPIO_PULL_DOWN) || (flags & GPIO_PULL_UP)) {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
ite_write(gpcr_reg_addr + pin, 1, GPIO_DIR_INPUT);
|
||||
if (flags & GPIO_OUTPUT_INIT_HIGH)
|
||||
*reg_gpdr |= mask;
|
||||
else if (flags & GPIO_OUTPUT_INIT_LOW)
|
||||
*reg_gpdr &= ~mask;
|
||||
}
|
||||
|
||||
/* Set input or output. */
|
||||
if (flags & GPIO_OUTPUT)
|
||||
*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_OUTPUT) &
|
||||
~GPCR_PORT_PIN_MODE_INPUT;
|
||||
else
|
||||
*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
|
||||
~GPCR_PORT_PIN_MODE_OUTPUT;
|
||||
|
||||
/* Handle pullup / pulldown */
|
||||
if (flags & GPIO_PULL_UP) {
|
||||
*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLUP) &
|
||||
~GPCR_PORT_PIN_MODE_PULLDOWN;
|
||||
} else if (flags & GPIO_PULL_DOWN) {
|
||||
*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLDOWN) &
|
||||
~GPCR_PORT_PIN_MODE_PULLUP;
|
||||
} else {
|
||||
/* No pull up/down */
|
||||
*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_PULLUP |
|
||||
GPCR_PORT_PIN_MODE_PULLDOWN);
|
||||
}
|
||||
|
||||
/*
|
||||
* TODO: There are some gpios are 1.8v input at default.
|
||||
* Is there a configuration flag for 1.8/3.3v selection.
|
||||
*/
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_ite_port_get_raw(const struct device *dev,
|
||||
gpio_port_value_t *value)
|
||||
gpio_port_value_t *value)
|
||||
{
|
||||
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
|
||||
volatile uint8_t *reg_gpdmr = (uint8_t *)gpio_config->reg_gpdmr;
|
||||
|
||||
/* Get raw bits of GPIO mirror register */
|
||||
*value = *reg_gpdmr;
|
||||
|
||||
*value = ite_read(gpio_config->reg_addr, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_ite_port_set_masked_raw(const struct device *dev,
|
||||
gpio_port_pins_t mask, gpio_port_value_t value)
|
||||
gpio_port_pins_t mask,
|
||||
gpio_port_value_t value)
|
||||
{
|
||||
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
|
||||
uint32_t port_val;
|
||||
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
|
||||
uint8_t out = *reg_gpdr;
|
||||
|
||||
*reg_gpdr = ((out & ~mask) | (value & mask));
|
||||
|
||||
port_val = get_port(gpio_config);
|
||||
port_val = (port_val & ~mask) | (value & mask);
|
||||
set_port(gpio_config, port_val);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_ite_port_set_bits_raw(const struct device *dev,
|
||||
gpio_port_pins_t pins)
|
||||
gpio_port_pins_t pins)
|
||||
{
|
||||
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
|
||||
uint32_t port_val;
|
||||
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
|
||||
|
||||
/* Set raw bits of GPIO data register */
|
||||
*reg_gpdr |= pins;
|
||||
|
||||
port_val = get_port(gpio_config);
|
||||
port_val |= pins;
|
||||
set_port(gpio_config, port_val);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_ite_port_clear_bits_raw(const struct device *dev,
|
||||
gpio_port_pins_t pins)
|
||||
gpio_port_pins_t pins)
|
||||
{
|
||||
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
|
||||
uint32_t port_val;
|
||||
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
|
||||
|
||||
/* Clear raw bits of GPIO data register */
|
||||
*reg_gpdr &= ~pins;
|
||||
|
||||
port_val = get_port(gpio_config);
|
||||
port_val &= ~pins;
|
||||
set_port(gpio_config, port_val);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_ite_port_toggle_bits(const struct device *dev,
|
||||
gpio_port_pins_t pins)
|
||||
gpio_port_pins_t pins)
|
||||
{
|
||||
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
|
||||
uint32_t port_val;
|
||||
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
|
||||
|
||||
/* Toggle raw bits of GPIO data register */
|
||||
*reg_gpdr ^= pins;
|
||||
|
||||
port_val = get_port(gpio_config);
|
||||
port_val ^= pins;
|
||||
set_port(gpio_config, port_val);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_ite_manage_callback(const struct device *dev,
|
||||
struct gpio_callback *callback,
|
||||
bool set)
|
||||
struct gpio_callback *callback,
|
||||
bool set)
|
||||
{
|
||||
struct gpio_ite_data *data = DEV_GPIO_DATA(dev);
|
||||
|
||||
|
|
@ -264,89 +363,63 @@ static int gpio_ite_manage_callback(const struct device *dev,
|
|||
|
||||
static void gpio_ite_isr(const void *arg)
|
||||
{
|
||||
int irq_index = 0;
|
||||
int gpio_index = 0;
|
||||
uint8_t irq = ite_intc_get_irq_num();
|
||||
const struct device *dev = arg;
|
||||
struct gpio_ite_wui *wui_local;
|
||||
struct gpio_ite_reg_table *gpio_tab_local = NULL;
|
||||
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
|
||||
struct gpio_ite_data *data = DEV_GPIO_DATA(dev);
|
||||
uint8_t gpio_mask = gpio_irqs[irq].gpio_mask;
|
||||
|
||||
|
||||
for (gpio_index = 0; gpio_index < CURR_SUPP_GPIO_SET; gpio_index++) {
|
||||
if (gpio_config->reg_addr == gpiox_reg[gpio_index].base_addr) {
|
||||
gpio_tab_local = &gpiox_reg[gpio_index];
|
||||
}
|
||||
}
|
||||
for (irq_index = 0; irq_index < NUM_IO_MAX; irq_index++) {
|
||||
wui_local = (struct gpio_ite_wui *)&
|
||||
gpio_tab_local->wui[irq_index];
|
||||
if ((*wui_local->clear_addr)&wui_local->pin) {
|
||||
SET_MASK(*wui_local->clear_addr, wui_local->pin);
|
||||
gpio_fire_callbacks(&data->callbacks, dev,
|
||||
BIT(wui_local->pin));
|
||||
}
|
||||
if (gpio_irqs[irq].wuc_group) {
|
||||
/* Clear the WUC status register. */
|
||||
*(wuesr(gpio_irqs[irq].wuc_group)) = gpio_irqs[irq].wuc_mask;
|
||||
gpio_fire_callbacks(&data->callbacks, dev, gpio_mask);
|
||||
}
|
||||
}
|
||||
|
||||
static int gpio_ite_pin_interrupt_configure(const struct device *dev,
|
||||
gpio_pin_t pin, enum gpio_int_mode mode, enum gpio_int_trig trig)
|
||||
gpio_pin_t pin,
|
||||
enum gpio_int_mode mode,
|
||||
enum gpio_int_trig trig)
|
||||
{
|
||||
int ret = 0;
|
||||
int gpio_index = 0;
|
||||
uint32_t g, i;
|
||||
uint8_t both_tri_en = 0;
|
||||
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
|
||||
struct gpio_ite_wui *wui_local;
|
||||
volatile uint8_t *trig_mode;
|
||||
volatile uint8_t *hl_trig;
|
||||
uint8_t gpio_irq = gpio_config->gpio_irq[pin];
|
||||
|
||||
g = gpio_config->gpio_irq[pin] / NUM_IO_MAX;
|
||||
i = gpio_config->gpio_irq[pin] % NUM_IO_MAX;
|
||||
trig_mode = reg_ielmr[g];
|
||||
hl_trig = reg_ipolr[g];
|
||||
|
||||
if (mode & GPIO_INT_MODE_DISABLED) {
|
||||
/* Disables interrupt for a pin. */
|
||||
ite_intc_irq_disable(gpio_config->gpio_irq[pin]);
|
||||
return ret;
|
||||
} else if (mode & GPIO_INT_MODE_EDGE) {
|
||||
/* edge trigger */
|
||||
SET_MASK(*trig_mode, BIT(i));
|
||||
} else {
|
||||
/* level trigger */
|
||||
CLEAR_MASK(*trig_mode, BIT(i));
|
||||
}
|
||||
/* both */
|
||||
if ((trig & GPIO_INT_TRIG_LOW) && (trig & GPIO_INT_TRIG_HIGH)) {
|
||||
both_tri_en = 1;
|
||||
} else {
|
||||
if (trig & GPIO_INT_TRIG_LOW) {
|
||||
SET_MASK(*hl_trig, BIT(i));
|
||||
} else if (trig & GPIO_INT_TRIG_HIGH) {
|
||||
CLEAR_MASK(*hl_trig, BIT(i));
|
||||
}
|
||||
if (mode == GPIO_INT_MODE_DISABLED) {
|
||||
/* Disable GPIO interrupt */
|
||||
irq_disable(gpio_irq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* set wui , only gpiob gpiof, currently */
|
||||
for (gpio_index = 0; gpio_index < CURR_SUPP_GPIO_SET; gpio_index++) {
|
||||
if (gpio_config->reg_addr ==
|
||||
gpiox_reg[gpio_index].base_addr) {
|
||||
wui_local = (struct gpio_ite_wui *)
|
||||
&(gpiox_reg[gpio_index].wui[pin]);
|
||||
SET_MASK(*wui_local->reg_addr, wui_local->pin);
|
||||
SET_MASK(*wui_local->clear_addr, wui_local->pin);
|
||||
if (both_tri_en == 1) {
|
||||
SET_MASK(*wui_local->reg_addr, wui_local->pin);
|
||||
}
|
||||
}
|
||||
if (mode == GPIO_INT_MODE_LEVEL) {
|
||||
printk("Level trigger mode not supported.\r\n");
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/* Enable IRQ */
|
||||
ret = irq_connect_dynamic(
|
||||
gpio_config->gpio_irq[pin], 0, gpio_ite_isr, dev, 0);
|
||||
ite_intc_irq_enable(gpio_config->gpio_irq[pin]);
|
||||
return ret;
|
||||
if (trig & GPIO_INT_TRIG_BOTH) {
|
||||
uint8_t wuc_group = gpio_irqs[gpio_irq].wuc_group;
|
||||
uint8_t wuc_mask = gpio_irqs[gpio_irq].wuc_mask;
|
||||
|
||||
/* Set both edges interrupt. */
|
||||
if ((trig & GPIO_INT_TRIG_BOTH) == GPIO_INT_TRIG_BOTH)
|
||||
*(wubemr(wuc_group)) |= wuc_mask;
|
||||
else
|
||||
*(wubemr(wuc_group)) &= ~wuc_mask;
|
||||
|
||||
if (trig & GPIO_INT_TRIG_LOW)
|
||||
*(wuemr(wuc_group)) |= wuc_mask;
|
||||
else
|
||||
*(wuemr(wuc_group)) &= ~wuc_mask;
|
||||
/*
|
||||
* Always write 1 to clear the WUC status register after
|
||||
* modifying edge mode selection register (WUBEMR and WUEMR).
|
||||
*/
|
||||
*(wuesr(wuc_group)) = wuc_mask;
|
||||
}
|
||||
|
||||
/* Enable GPIO interrupt */
|
||||
irq_connect_dynamic(gpio_irq, 0, gpio_ite_isr, dev, 0);
|
||||
irq_enable(gpio_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct gpio_driver_api gpio_ite_driver_api = {
|
||||
|
|
@ -362,34 +435,33 @@ static const struct gpio_driver_api gpio_ite_driver_api = {
|
|||
|
||||
static int gpio_ite_init(const struct device *dev)
|
||||
{
|
||||
const struct gpio_ite_cfg *gpio_config = DEV_GPIO_CFG(dev);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < NUM_IO_MAX; i++) {
|
||||
/* init disable intc */
|
||||
ite_intc_irq_disable(gpio_config->gpio_irq[i]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define GPIO_ITE_DEV_CFG_DATA(n, idx) \
|
||||
static struct gpio_ite_data gpio_ite_data_##n##_##idx; \
|
||||
static const struct gpio_ite_cfg gpio_ite_cfg_##n##_##idx = { \
|
||||
.reg_addr = DT_INST_REG_ADDR(idx),\
|
||||
.gpio_irq[0] = DT_INST_IRQ_BY_IDX(idx, 0, irq), \
|
||||
}; \
|
||||
DEVICE_DT_DEFINE(DT_NODELABEL(n), \
|
||||
gpio_ite_init, \
|
||||
device_pm_control_nop, \
|
||||
&gpio_ite_data_##n##_##idx, \
|
||||
&gpio_ite_cfg_##n##_##idx, \
|
||||
POST_KERNEL, \
|
||||
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
|
||||
&gpio_ite_driver_api)
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay)
|
||||
GPIO_ITE_DEV_CFG_DATA(gpiob, 0);
|
||||
#endif /* gpiob */
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpiof), okay)
|
||||
GPIO_ITE_DEV_CFG_DATA(gpiof, 1);
|
||||
#endif /* gpiof */
|
||||
#define GPIO_ITE_DEV_CFG_DATA(inst) \
|
||||
static struct gpio_ite_data gpio_ite_data_##inst; \
|
||||
static const struct gpio_ite_cfg gpio_ite_cfg_##inst = { \
|
||||
.reg_gpdr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
|
||||
.reg_gpcr = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
|
||||
.reg_gpdmr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
|
||||
.reg_gpotr = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
|
||||
.ngpios = DT_PROP(DT_INST(inst, ite_it8xxx2_gpio), ngpios),\
|
||||
.gpio_irq[0] = DT_INST_IRQ_BY_IDX(inst, 0, irq), \
|
||||
.gpio_irq[1] = DT_INST_IRQ_BY_IDX(inst, 1, irq), \
|
||||
.gpio_irq[2] = DT_INST_IRQ_BY_IDX(inst, 2, irq), \
|
||||
.gpio_irq[3] = DT_INST_IRQ_BY_IDX(inst, 3, irq), \
|
||||
.gpio_irq[4] = DT_INST_IRQ_BY_IDX(inst, 4, irq), \
|
||||
.gpio_irq[5] = DT_INST_IRQ_BY_IDX(inst, 5, irq), \
|
||||
.gpio_irq[6] = DT_INST_IRQ_BY_IDX(inst, 6, irq), \
|
||||
.gpio_irq[7] = DT_INST_IRQ_BY_IDX(inst, 7, irq), \
|
||||
}; \
|
||||
DEVICE_DT_INST_DEFINE(inst, \
|
||||
gpio_ite_init, \
|
||||
device_pm_control_nop, \
|
||||
&gpio_ite_data_##inst, \
|
||||
&gpio_ite_cfg_##inst, \
|
||||
POST_KERNEL, \
|
||||
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
|
||||
&gpio_ite_driver_api);
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(GPIO_ITE_DEV_CFG_DATA)
|
||||
|
|
|
|||
|
|
@ -15,22 +15,25 @@
|
|||
#define IVECT_OFFSET_WITH_IRQ 0x10
|
||||
#define SOFT_INTC_IRQ 161 /* software interrupt */
|
||||
|
||||
static volatile uint8_t *const reg_status[MAX_ISR_REG_NUM] = {
|
||||
/* Interrupt number of INTC module */
|
||||
static uint8_t intc_irq;
|
||||
|
||||
static volatile uint8_t *const reg_status[] = {
|
||||
&ISR0, &ISR1, &ISR2, &ISR3,
|
||||
&ISR4, &ISR5, &ISR6, &ISR7,
|
||||
&ISR8, &ISR9, &ISR10, &ISR11,
|
||||
&ISR12, &ISR13, &ISR14, &ISR15,
|
||||
&ISR16, &ISR17, &ISR18, &ISR19,
|
||||
&ISR20
|
||||
&ISR20, &ISR21, &ISR22, &ISR23
|
||||
};
|
||||
|
||||
static volatile uint8_t *const reg_enable[MAX_ISR_REG_NUM] = {
|
||||
static volatile uint8_t *const reg_enable[] = {
|
||||
&IER0, &IER1, &IER2, &IER3,
|
||||
&IER4, &IER5, &IER6, &IER7,
|
||||
&IER8, &IER9, &IER10, &IER11,
|
||||
&IER12, &IER13, &IER14, &IER15,
|
||||
&IER16, &IER17, &IER18, &IER19,
|
||||
&IER20
|
||||
&IER20, &IER21, &IER22, &IER23
|
||||
};
|
||||
|
||||
/* edge/level trigger register */
|
||||
|
|
@ -40,7 +43,7 @@ static volatile uint8_t *const reg_ielmr[] = {
|
|||
&IELMR8, &IELMR9, &IELMR10, &IELMR11,
|
||||
&IELMR12, &IELMR13, &IELMR14, &IELMR15,
|
||||
&IELMR16, &IELMR17, &IELMR18, &IELMR19,
|
||||
&IELMR20
|
||||
&IELMR20, &IELMR21, &IELMR22, &IELMR23,
|
||||
};
|
||||
|
||||
/* high/low trigger register */
|
||||
|
|
@ -50,7 +53,7 @@ static volatile uint8_t *const reg_ipolr[] = {
|
|||
&IPOLR8, &IPOLR9, &IPOLR10, &IPOLR11,
|
||||
&IPOLR12, &IPOLR13, &IPOLR14, &IPOLR15,
|
||||
&IPOLR16, &IPOLR17, &IPOLR18, &IPOLR19,
|
||||
&IPOLR20
|
||||
&IPOLR20, &IPOLR21, &IPOLR22, &IPOLR23
|
||||
};
|
||||
|
||||
inline void set_csr(unsigned long bit)
|
||||
|
|
@ -147,16 +150,20 @@ int ite_intc_irq_is_enable(unsigned int irq)
|
|||
return IS_MASK_SET(*en, BIT(i));
|
||||
}
|
||||
|
||||
uint8_t ite_intc_get_irq_num(void)
|
||||
{
|
||||
return intc_irq;
|
||||
}
|
||||
|
||||
void ite_intc_irq_handler(const void *arg)
|
||||
{
|
||||
ARG_UNUSED(arg);
|
||||
uint8_t irq = IVECT1 - IVECT_OFFSET_WITH_IRQ;
|
||||
struct _isr_table_entry *ite;
|
||||
|
||||
struct _isr_table_entry *ite;
|
||||
/* software interrupt isr*/
|
||||
if ((irq < CONFIG_NUM_IRQS) && (irq > 0)) {
|
||||
ite = (struct _isr_table_entry *)&_sw_isr_table[irq];
|
||||
ite_intc_isr_clear(irq);
|
||||
if ((intc_irq < CONFIG_NUM_IRQS) && (intc_irq > 0)) {
|
||||
ite = (struct _isr_table_entry *)&_sw_isr_table[intc_irq];
|
||||
ite_intc_isr_clear(intc_irq);
|
||||
ite->isr(ite->arg);
|
||||
} else {
|
||||
z_irq_spurious(NULL);
|
||||
|
|
@ -166,10 +173,10 @@ void ite_intc_irq_handler(const void *arg)
|
|||
uint8_t get_irq(void *arg)
|
||||
{
|
||||
ARG_UNUSED(arg);
|
||||
uint8_t irq = IVECT1 - IVECT_OFFSET_WITH_IRQ;
|
||||
intc_irq = IVECT - IVECT_OFFSET_WITH_IRQ;
|
||||
|
||||
ite_intc_isr_clear(irq);
|
||||
return irq;
|
||||
ite_intc_isr_clear(intc_irq);
|
||||
return intc_irq;
|
||||
}
|
||||
|
||||
static int ite_intc_init(const struct device *dev)
|
||||
|
|
@ -178,6 +185,10 @@ static int ite_intc_init(const struct device *dev)
|
|||
ite_intc_irq_enable(SOFT_INTC_IRQ);
|
||||
irq_unlock(0);
|
||||
|
||||
/* Ensure interrupts of soc are disabled at default */
|
||||
for (int i = 0; i < ARRAY_SIZE(reg_enable); i++)
|
||||
*reg_enable[i] = 0;
|
||||
|
||||
/* GIE enable */
|
||||
set_csr(MIP_MEIP);
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -3,10 +3,10 @@
|
|||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef INTC_ITE_IT8XXX2
|
||||
#define INTC_ITE_IT8XXX2
|
||||
#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_ITE_IT8XXX2_H_
|
||||
#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_ITE_IT8XXX2_H_
|
||||
|
||||
#include <dt-bindings/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/ite-intc.h>
|
||||
#include <soc.h>
|
||||
|
||||
#endif /* INTC_ITE_IT8XXX2 */
|
||||
#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_ITE_IT8XXX2_H_ */
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <dt-bindings/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/ite-intc.h>
|
||||
#include <dt-bindings/i2c/i2c.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -89,52 +89,280 @@
|
|||
80 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-parent = <&intc>;
|
||||
};
|
||||
|
||||
gpioa: gpio@f01601 {
|
||||
compatible = "ite,it8xxx2-gpio";
|
||||
reg = <0x00f01601 1 /* GPDR (set) */
|
||||
0x00f01610 8 /* GPCR */
|
||||
0x00f01661 1 /* GPDMR (get) */
|
||||
0x00f01671 1>; /* GPOTR */
|
||||
ngpios = <8>;
|
||||
label = "GPIO_A";
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU91 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU92 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU93 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU80 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU81 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU82 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU83 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpiob: gpio@f01602 {
|
||||
compatible = "ite,it8xxx2-gpio";
|
||||
reg = <0x00f01602 0x0001>;
|
||||
reg = <0x00f01602 1 /* GPDR (set) */
|
||||
0x00f01618 8 /* GPCR */
|
||||
0x00f01662 1 /* GPDMR (get) */
|
||||
0x00f01672 1>; /* GPOTR */
|
||||
ngpios = <8>;
|
||||
label = "GPDRB";
|
||||
status = "disabled";
|
||||
label = "GPIO_B";
|
||||
gpio-controller;
|
||||
interrupts = <106 IRQ_TYPE_LEVEL_HIGH
|
||||
107 IRQ_TYPE_LEVEL_HIGH
|
||||
92 IRQ_TYPE_LEVEL_HIGH
|
||||
108 IRQ_TYPE_LEVEL_HIGH
|
||||
99 IRQ_TYPE_LEVEL_HIGH
|
||||
109 IRQ_TYPE_LEVEL_HIGH
|
||||
110 IRQ_TYPE_LEVEL_HIGH
|
||||
111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <IT8XXX2_IRQ_WU101 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU102 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU84 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU103 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU94 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU104 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU105 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioc: gpio@f01603 {
|
||||
compatible = "ite,it8xxx2-gpio";
|
||||
reg = <0x00f01603 1 /* GPDR (set) */
|
||||
0x00f01620 8 /* GPCR */
|
||||
0x00f01663 1 /* GPDMR (get) */
|
||||
0x00f01673 1>; /* GPOTR */
|
||||
ngpios = <8>;
|
||||
label = "GPIO_C";
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU85 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU107 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU95 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU108 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU22 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU109 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU23 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpiod: gpio@f01604 {
|
||||
compatible = "ite,it8xxx2-gpio";
|
||||
reg = <0x00f01604 1 /* GPDR (set) */
|
||||
0x00f01628 8 /* GPCR */
|
||||
0x00f01664 1 /* GPDMR (get) */
|
||||
0x00f01674 1>; /* GPOTR */
|
||||
ngpios = <8>;
|
||||
label = "GPIO_D";
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU20 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU21 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU24 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU110 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU111 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU112 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU113 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioe: gpio@f01605 {
|
||||
compatible = "ite,it8xxx2-gpio";
|
||||
reg = <0x00f01605 1 /* GPDR (set) */
|
||||
0x00f01630 8 /* GPCR */
|
||||
0x00f01665 1 /* GPDMR (get) */
|
||||
0x00f01675 1>; /* GPOTR */
|
||||
ngpios = <8>;
|
||||
label = "GPIO_E";
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU70 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU71 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU72 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU73 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU114 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU40 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU45 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpiof: gpio@f01606 {
|
||||
compatible = "ite,it8xxx2-gpio";
|
||||
reg = <0x00f01606 0x0001>;
|
||||
reg = <0x00f01606 1 /* GPDR (set) */
|
||||
0x00f01638 8 /* GPCR */
|
||||
0x00f01666 1 /* GPDMR (get) */
|
||||
0x00f01676 1>; /* GPOTR */
|
||||
ngpios = <8>;
|
||||
label = "GPDRF";
|
||||
status = "disabled";
|
||||
label = "GPIO_F";
|
||||
gpio-controller;
|
||||
interrupts = <101 IRQ_TYPE_LEVEL_HIGH
|
||||
102 IRQ_TYPE_LEVEL_HIGH
|
||||
103 IRQ_TYPE_LEVEL_HIGH
|
||||
104 IRQ_TYPE_LEVEL_HIGH
|
||||
52 IRQ_TYPE_LEVEL_HIGH
|
||||
53 IRQ_TYPE_LEVEL_HIGH
|
||||
54 IRQ_TYPE_LEVEL_HIGH
|
||||
55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <IT8XXX2_IRQ_WU96 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU97 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU98 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU99 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU64 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU65 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU66 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
gpiom: gpio@f0160D {
|
||||
|
||||
gpiog: gpio@f01607 {
|
||||
compatible = "ite,it8xxx2-gpio";
|
||||
reg = <0x00f0160D 0x0001>;
|
||||
reg = <0x00f01607 1 /* GPDR (set) */
|
||||
0x00f01640 8 /* GPCR */
|
||||
0x00f01667 1 /* GPDMR (get) */
|
||||
0x00f01677 1>; /* GPOTR */
|
||||
ngpios = <8>;
|
||||
label = "GPDRM";
|
||||
status = "disabled";
|
||||
label = "GPIO_G";
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU115 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU116 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU117 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU123 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU124 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU125 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU118 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioh: gpio@f01608 {
|
||||
compatible = "ite,it8xxx2-gpio";
|
||||
reg = <0x00f01608 1 /* GPDR (set) */
|
||||
0x00f01648 8 /* GPCR */
|
||||
0x00f01668 1 /* GPDMR (get) */
|
||||
0x00f01678 1>; /* GPOTR */
|
||||
ngpios = <8>;
|
||||
label = "GPIO_H";
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU60 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU61 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU62 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU63 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU88 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU89 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU90 IRQ_TYPE_LEVEL_HIGH
|
||||
0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioi: gpio@f01609 {
|
||||
compatible = "ite,it8xxx2-gpio";
|
||||
reg = <0x00f01609 1 /* GPDR (set) */
|
||||
0x00f01650 8 /* GPCR */
|
||||
0x00f01669 1 /* GPDMR (get) */
|
||||
0x00f01679 1>; /* GPOTR */
|
||||
ngpios = <8>;
|
||||
label = "GPIO_I";
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU119 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU120 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU121 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU122 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU74 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU75 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU76 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioj: gpio@f0160a {
|
||||
compatible = "ite,it8xxx2-gpio";
|
||||
reg = <0x00f0160a 1 /* GPDR (set) */
|
||||
0x00f01658 8 /* GPCR */
|
||||
0x00f0166a 1 /* GPDMR (get) */
|
||||
0x00f0167a 1>; /* GPOTR */
|
||||
ngpios = <8>;
|
||||
label = "GPIO_J";
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU128 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU129 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU130 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU131 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU132 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU133 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU134 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU135 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpiok: gpio@f0160b {
|
||||
compatible = "ite,it8xxx2-gpio";
|
||||
reg = <0x00f0160b 1 /* GPDR (set) */
|
||||
0x00f01690 8 /* GPCR */
|
||||
0x00f0166b 1 /* GPDMR (get) */
|
||||
0x00f0167b 1>; /* GPOTR */
|
||||
ngpios = <8>;
|
||||
label = "GPIO_K";
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU50 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU51 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU52 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU53 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU54 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU55 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU56 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpiol: gpio@f0160c {
|
||||
compatible = "ite,it8xxx2-gpio";
|
||||
reg = <0x00f0160c 1 /* GPDR (set) */
|
||||
0x00f01698 8 /* GPCR */
|
||||
0x00f0166c 1 /* GPDMR (get) */
|
||||
0x00f0167c 1>; /* GPOTR */
|
||||
ngpios = <8>;
|
||||
label = "GPIO_L";
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU136 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU137 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU138 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU139 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU140 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU141 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU142 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpiom: gpio@f0160d {
|
||||
compatible = "ite,it8xxx2-gpio";
|
||||
reg = <0x00f0160d 1 /* GPDR (set) */
|
||||
0x00f016a0 8 /* GPCR */
|
||||
0x00f0166d 1 /* GPDMR (get) */
|
||||
0x00f0167d 1>; /* GPOTR */
|
||||
ngpios = <7>;
|
||||
label = "GPIO_M";
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU144 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU145 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU146 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU147 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU148 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU149 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU150 IRQ_TYPE_LEVEL_HIGH
|
||||
0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
spi0:spi@f02600 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
142
include/dt-bindings/interrupt-controller/ite-intc.h
Normal file
142
include/dt-bindings/interrupt-controller/ite-intc.h
Normal file
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_
|
||||
|
||||
#define IRQ_TYPE_NONE 0
|
||||
#define IRQ_TYPE_EDGE_RISING 1
|
||||
#define IRQ_TYPE_EDGE_FALLING 2
|
||||
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
|
||||
#define IRQ_TYPE_LEVEL_HIGH 4
|
||||
#define IRQ_TYPE_LEVEL_LOW 8
|
||||
|
||||
/* IRQ numbers of WUC */
|
||||
/* Group 0 of INTC */
|
||||
#define IT8XXX2_IRQ_WU20 1
|
||||
#define IT8XXX2_IRQ_WU23 6
|
||||
/* Group 1 */
|
||||
#define IT8XXX2_IRQ_WU26 12
|
||||
#define IT8XXX2_IRQ_WU25 14
|
||||
/* Group 2 */
|
||||
#define IT8XXX2_IRQ_WU24 17
|
||||
#define IT8XXX2_IRQ_WU22 21
|
||||
/* Group 3 */
|
||||
#define IT8XXX2_IRQ_WU21 31
|
||||
/* Group 5 */
|
||||
#define IT8XXX2_IRQ_WU50 40
|
||||
#define IT8XXX2_IRQ_WU51 41
|
||||
#define IT8XXX2_IRQ_WU52 42
|
||||
#define IT8XXX2_IRQ_WU53 43
|
||||
#define IT8XXX2_IRQ_WU54 44
|
||||
#define IT8XXX2_IRQ_WU55 45
|
||||
#define IT8XXX2_IRQ_WU56 46
|
||||
#define IT8XXX2_IRQ_WU57 47
|
||||
/* Group 6 */
|
||||
#define IT8XXX2_IRQ_WU60 48
|
||||
#define IT8XXX2_IRQ_WU61 49
|
||||
#define IT8XXX2_IRQ_WU62 50
|
||||
#define IT8XXX2_IRQ_WU63 51
|
||||
#define IT8XXX2_IRQ_WU64 52
|
||||
#define IT8XXX2_IRQ_WU65 53
|
||||
#define IT8XXX2_IRQ_WU66 54
|
||||
#define IT8XXX2_IRQ_WU67 55
|
||||
/* Group 9 */
|
||||
#define IT8XXX2_IRQ_WU70 72
|
||||
#define IT8XXX2_IRQ_WU71 73
|
||||
#define IT8XXX2_IRQ_WU72 74
|
||||
#define IT8XXX2_IRQ_WU73 75
|
||||
#define IT8XXX2_IRQ_WU74 76
|
||||
#define IT8XXX2_IRQ_WU75 77
|
||||
#define IT8XXX2_IRQ_WU76 78
|
||||
#define IT8XXX2_IRQ_WU77 79
|
||||
/* Group 10 */
|
||||
#define IT8XXX2_IRQ_WU88 85
|
||||
#define IT8XXX2_IRQ_WU89 86
|
||||
#define IT8XXX2_IRQ_WU90 87
|
||||
/* Group 11 */
|
||||
#define IT8XXX2_IRQ_WU80 88
|
||||
#define IT8XXX2_IRQ_WU81 89
|
||||
#define IT8XXX2_IRQ_WU82 90
|
||||
#define IT8XXX2_IRQ_WU83 91
|
||||
#define IT8XXX2_IRQ_WU84 92
|
||||
#define IT8XXX2_IRQ_WU85 93
|
||||
#define IT8XXX2_IRQ_WU86 94
|
||||
#define IT8XXX2_IRQ_WU87 95
|
||||
/* Group 12 */
|
||||
#define IT8XXX2_IRQ_WU91 96
|
||||
#define IT8XXX2_IRQ_WU92 97
|
||||
#define IT8XXX2_IRQ_WU93 98
|
||||
#define IT8XXX2_IRQ_WU94 99
|
||||
#define IT8XXX2_IRQ_WU95 100
|
||||
#define IT8XXX2_IRQ_WU96 101
|
||||
#define IT8XXX2_IRQ_WU97 102
|
||||
#define IT8XXX2_IRQ_WU98 103
|
||||
/* Group 13 */
|
||||
#define IT8XXX2_IRQ_WU99 104
|
||||
#define IT8XXX2_IRQ_WU100 105
|
||||
#define IT8XXX2_IRQ_WU101 106
|
||||
#define IT8XXX2_IRQ_WU102 107
|
||||
#define IT8XXX2_IRQ_WU103 108
|
||||
#define IT8XXX2_IRQ_WU104 109
|
||||
#define IT8XXX2_IRQ_WU105 110
|
||||
#define IT8XXX2_IRQ_WU106 111
|
||||
/* Group 14 */
|
||||
#define IT8XXX2_IRQ_WU107 112
|
||||
#define IT8XXX2_IRQ_WU108 113
|
||||
#define IT8XXX2_IRQ_WU109 114
|
||||
#define IT8XXX2_IRQ_WU110 115
|
||||
#define IT8XXX2_IRQ_WU111 116
|
||||
#define IT8XXX2_IRQ_WU112 117
|
||||
#define IT8XXX2_IRQ_WU113 118
|
||||
#define IT8XXX2_IRQ_WU114 119
|
||||
/* Group 15 */
|
||||
#define IT8XXX2_IRQ_WU115 120
|
||||
#define IT8XXX2_IRQ_WU116 121
|
||||
#define IT8XXX2_IRQ_WU117 122
|
||||
#define IT8XXX2_IRQ_WU118 123
|
||||
#define IT8XXX2_IRQ_WU119 124
|
||||
#define IT8XXX2_IRQ_WU120 125
|
||||
#define IT8XXX2_IRQ_WU121 126
|
||||
#define IT8XXX2_IRQ_WU122 127
|
||||
/* Group 16 */
|
||||
#define IT8XXX2_IRQ_WU128 128
|
||||
#define IT8XXX2_IRQ_WU129 129
|
||||
#define IT8XXX2_IRQ_WU130 130
|
||||
#define IT8XXX2_IRQ_WU131 131
|
||||
#define IT8XXX2_IRQ_WU132 132
|
||||
#define IT8XXX2_IRQ_WU133 133
|
||||
#define IT8XXX2_IRQ_WU134 134
|
||||
#define IT8XXX2_IRQ_WU135 135
|
||||
/* Group 17 */
|
||||
#define IT8XXX2_IRQ_WU136 136
|
||||
#define IT8XXX2_IRQ_WU137 137
|
||||
#define IT8XXX2_IRQ_WU138 138
|
||||
#define IT8XXX2_IRQ_WU139 139
|
||||
#define IT8XXX2_IRQ_WU140 140
|
||||
#define IT8XXX2_IRQ_WU141 141
|
||||
#define IT8XXX2_IRQ_WU142 142
|
||||
#define IT8XXX2_IRQ_WU143 143
|
||||
/* Group 18 */
|
||||
#define IT8XXX2_IRQ_WU123 144
|
||||
#define IT8XXX2_IRQ_WU124 145
|
||||
#define IT8XXX2_IRQ_WU125 146
|
||||
#define IT8XXX2_IRQ_WU126 147
|
||||
/* Group 22 */
|
||||
#define IT8XXX2_IRQ_WU40 176
|
||||
#define IT8XXX2_IRQ_WU45 177
|
||||
#define IT8XXX2_IRQ_WU46 178
|
||||
#define IT8XXX2_IRQ_WU144 179
|
||||
#define IT8XXX2_IRQ_WU145 180
|
||||
#define IT8XXX2_IRQ_WU146 181
|
||||
#define IT8XXX2_IRQ_WU147 182
|
||||
#define IT8XXX2_IRQ_WU148 183
|
||||
/* Group 23 */
|
||||
#define IT8XXX2_IRQ_WU149 184
|
||||
#define IT8XXX2_IRQ_WU150 185
|
||||
|
||||
#define IT8XXX2_IRQ_COUNT (CONFIG_NUM_IRQS + 1)
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_ */
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDING_IRQ_H
|
||||
#define __DT_BINDING_IRQ_H
|
||||
|
||||
#define IRQ_TYPE_NONE 0
|
||||
#define IRQ_TYPE_EDGE_RISING 1
|
||||
#define IRQ_TYPE_EDGE_FALLING 2
|
||||
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
|
||||
#define IRQ_TYPE_LEVEL_HIGH 4
|
||||
#define IRQ_TYPE_LEVEL_LOW 8
|
||||
|
||||
#endif
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
/*
|
||||
/*
|
||||
* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -297,7 +297,6 @@
|
|||
* (11xxh) Interrupt controller (INTC)
|
||||
*
|
||||
*/
|
||||
#define MAX_ISR_REG_NUM 24
|
||||
#define ISR0 ECREG(EC_REG_BASE_ADDR + 0x3F00)
|
||||
#define ISR1 ECREG(EC_REG_BASE_ADDR + 0x3F01)
|
||||
#define ISR2 ECREG(EC_REG_BASE_ADDR + 0x3F02)
|
||||
|
|
@ -319,6 +318,9 @@
|
|||
#define ISR18 ECREG(EC_REG_BASE_ADDR + 0x3F4C)
|
||||
#define ISR19 ECREG(EC_REG_BASE_ADDR + 0x3F50)
|
||||
#define ISR20 ECREG(EC_REG_BASE_ADDR + 0x3F54)
|
||||
#define ISR21 ECREG(EC_REG_BASE_ADDR + 0x3F58)
|
||||
#define ISR22 ECREG(EC_REG_BASE_ADDR + 0x3F5C)
|
||||
#define ISR23 ECREG(EC_REG_BASE_ADDR + 0x3F90)
|
||||
|
||||
#define IER0 ECREG(EC_REG_BASE_ADDR + 0x3F04)
|
||||
#define IER1 ECREG(EC_REG_BASE_ADDR + 0x3F05)
|
||||
|
|
@ -341,6 +343,9 @@
|
|||
#define IER18 ECREG(EC_REG_BASE_ADDR + 0x3F4D)
|
||||
#define IER19 ECREG(EC_REG_BASE_ADDR + 0x3F51)
|
||||
#define IER20 ECREG(EC_REG_BASE_ADDR + 0x3F55)
|
||||
#define IER21 ECREG(EC_REG_BASE_ADDR + 0x3F59)
|
||||
#define IER22 ECREG(EC_REG_BASE_ADDR + 0x3F5D)
|
||||
#define IER23 ECREG(EC_REG_BASE_ADDR + 0x3F91)
|
||||
|
||||
#define IELMR0 ECREG(EC_REG_BASE_ADDR + 0x3F08)
|
||||
#define IELMR1 ECREG(EC_REG_BASE_ADDR + 0x3F09)
|
||||
|
|
@ -363,6 +368,9 @@
|
|||
#define IELMR18 ECREG(EC_REG_BASE_ADDR + 0x3F4E)
|
||||
#define IELMR19 ECREG(EC_REG_BASE_ADDR + 0x3F52)
|
||||
#define IELMR20 ECREG(EC_REG_BASE_ADDR + 0x3F56)
|
||||
#define IELMR21 ECREG(EC_REG_BASE_ADDR + 0x3F5A)
|
||||
#define IELMR22 ECREG(EC_REG_BASE_ADDR + 0x3F5E)
|
||||
#define IELMR23 ECREG(EC_REG_BASE_ADDR + 0x3F92)
|
||||
|
||||
#define IPOLR0 ECREG(EC_REG_BASE_ADDR + 0x3F0C)
|
||||
#define IPOLR1 ECREG(EC_REG_BASE_ADDR + 0x3F0D)
|
||||
|
|
@ -385,217 +393,11 @@
|
|||
#define IPOLR18 ECREG(EC_REG_BASE_ADDR + 0x3F4F)
|
||||
#define IPOLR19 ECREG(EC_REG_BASE_ADDR + 0x3F53)
|
||||
#define IPOLR20 ECREG(EC_REG_BASE_ADDR + 0x3F57)
|
||||
#define IPOLR21 ECREG(EC_REG_BASE_ADDR + 0x3F5B)
|
||||
#define IPOLR22 ECREG(EC_REG_BASE_ADDR + 0x3F5F)
|
||||
#define IPOLR23 ECREG(EC_REG_BASE_ADDR + 0x3F93)
|
||||
|
||||
#define IVECT0 ECREG(EC_REG_BASE_ADDR + 0x3F80)
|
||||
#define IVECT1 ECREG(EC_REG_BASE_ADDR + 0x3F81)
|
||||
#define IVECT2 ECREG(EC_REG_BASE_ADDR + 0x3F82)
|
||||
#define IVECT3 ECREG(EC_REG_BASE_ADDR + 0x3F83)
|
||||
#define IVECT4 ECREG(EC_REG_BASE_ADDR + 0x3F84)
|
||||
#define IVECT5 ECREG(EC_REG_BASE_ADDR + 0x3F85)
|
||||
#define IVECT6 ECREG(EC_REG_BASE_ADDR + 0x3F86)
|
||||
#define IVECT7 ECREG(EC_REG_BASE_ADDR + 0x3F87)
|
||||
#define IVECT8 ECREG(EC_REG_BASE_ADDR + 0x3F88)
|
||||
#define IVECT9 ECREG(EC_REG_BASE_ADDR + 0x3F89)
|
||||
#define IVECT10 ECREG(EC_REG_BASE_ADDR + 0x3F8A)
|
||||
#define IVECT11 ECREG(EC_REG_BASE_ADDR + 0x3F8B)
|
||||
#define IVECT12 ECREG(EC_REG_BASE_ADDR + 0x3F8C)
|
||||
#define IVECT13 ECREG(EC_REG_BASE_ADDR + 0x3F8D)
|
||||
#define IVECT14 ECREG(EC_REG_BASE_ADDR + 0x3F8E)
|
||||
#define IVECT15 ECREG(EC_REG_BASE_ADDR + 0x3F8F)
|
||||
#define IVECT ECREG(EC_REG_BASE_ADDR + 0x3F10)
|
||||
#define INT0ST ECREG(EC_REG_BASE_ADDR + 0x3F11)
|
||||
#define PFAILR ECREG(EC_REG_BASE_ADDR + 0x3F12)
|
||||
#define IGER0 ECREG(EC_REG_BASE_ADDR + 0x3F60)
|
||||
#define IGER1 ECREG(EC_REG_BASE_ADDR + 0x3F61)
|
||||
#define IGER2 ECREG(EC_REG_BASE_ADDR + 0x3F62)
|
||||
#define IGER3 ECREG(EC_REG_BASE_ADDR + 0x3F63)
|
||||
#define IGER4 ECREG(EC_REG_BASE_ADDR + 0x3F64)
|
||||
#define IGER5 ECREG(EC_REG_BASE_ADDR + 0x3F65)
|
||||
#define IGER6 ECREG(EC_REG_BASE_ADDR + 0x3F66)
|
||||
#define IGER7 ECREG(EC_REG_BASE_ADDR + 0x3F67)
|
||||
#define IGER8 ECREG(EC_REG_BASE_ADDR + 0x3F68)
|
||||
#define IGER9 ECREG(EC_REG_BASE_ADDR + 0x3F69)
|
||||
#define IGER10 ECREG(EC_REG_BASE_ADDR + 0x3F6A)
|
||||
#define IGER11 ECREG(EC_REG_BASE_ADDR + 0x3F6B)
|
||||
#define IGER12 ECREG(EC_REG_BASE_ADDR + 0x3F6C)
|
||||
#define IGER13 ECREG(EC_REG_BASE_ADDR + 0x3F6D)
|
||||
#define IGER14 ECREG(EC_REG_BASE_ADDR + 0x3F6E)
|
||||
#define IGER15 ECREG(EC_REG_BASE_ADDR + 0x3F6F)
|
||||
#define IGER16 ECREG(EC_REG_BASE_ADDR + 0x3F70)
|
||||
#define IGER17 ECREG(EC_REG_BASE_ADDR + 0x3F71)
|
||||
#define IGER18 ECREG(EC_REG_BASE_ADDR + 0x3F72)
|
||||
#define IGER19 ECREG(EC_REG_BASE_ADDR + 0x3F73)
|
||||
#define IGER20 ECREG(EC_REG_BASE_ADDR + 0x3F74)
|
||||
|
||||
/* IER0 */
|
||||
#define INT_WKO20 BIT(1)
|
||||
#define INT_KBCOBFE BIT(2)
|
||||
#define INT_PMCOBFE BIT(3)
|
||||
#define INT_SMBUS3 BIT(4)
|
||||
#define INT_WKINTAD BIT(5)
|
||||
#define INT_WKO23 BIT(6)
|
||||
#define INT_PWM BIT(7)
|
||||
|
||||
/* IER1 */
|
||||
#define INT_ADC BIT(0)
|
||||
#define INT_SMBUS0 BIT(1)
|
||||
#define INT_SMBUS1 BIT(2)
|
||||
#define INT_KB BIT(3)
|
||||
#define INT_WKO26 BIT(4)
|
||||
#define INT_WKINTC BIT(5)
|
||||
#define INT_WKO25 BIT(6)
|
||||
#define INT_CIR BIT(7)
|
||||
|
||||
/* IER2 */
|
||||
#define INT_SMBUS2 BIT(0)
|
||||
#define INT_WKO24 BIT(1)
|
||||
#define INT_PS2_2 BIT(2)
|
||||
#define INT_PS2_1 BIT(3)
|
||||
#define INT_PS2_0 BIT(4)
|
||||
#define INT_WKO22 BIT(5)
|
||||
#define SMFIS BIT(6)
|
||||
|
||||
/* IER3 */
|
||||
#define INT_KBCIBF BIT(0)
|
||||
#define INT_PMCIBF BIT(1)
|
||||
#define INT_PMC2OBE BIT(2)
|
||||
#define INT_PMC2IBF BIT(3)
|
||||
#define INT_GINT BIT(4)
|
||||
#define INT_EGPC BIT(5)
|
||||
#define INT_EXTIMER BIT(6)
|
||||
#define INT_WKO21 BIT(7)
|
||||
|
||||
/* IER4 */
|
||||
#define INT_GPINT0 BIT(0)
|
||||
#define INT_GPINT1 BIT(1)
|
||||
#define INT_GPINT2 BIT(2)
|
||||
#define INT_GPINT3 BIT(3)
|
||||
#define INT_CIRGPINT BIT(4)
|
||||
#define INT_SSPI BIT(5)
|
||||
#define INT_UART1 BIT(6)
|
||||
#define INT_UART2 BIT(7)
|
||||
|
||||
/* IER6 */
|
||||
#define INT_WKO60 BIT(0)
|
||||
#define INT_WKO61 BIT(1)
|
||||
#define INT_WKO62 BIT(2)
|
||||
#define INT_WKO63 BIT(3)
|
||||
#define INT_WKO64 BIT(4)
|
||||
#define INT_WKO65 BIT(5)
|
||||
#define INT_WKO66 BIT(6)
|
||||
#define INT_WKO67 BIT(7)
|
||||
|
||||
/* IER7 */
|
||||
#define INT_RTCTALARM1 BIT(0)
|
||||
#define INT_RTCTALARM2 BIT(1)
|
||||
#define INT_ET2INTR BIT(2)
|
||||
#define INT_TMRINTA0 BIT(4)
|
||||
#define INT_TMRINTA1 BIT(5)
|
||||
#define INT_TMRINTB0 BIT(6)
|
||||
#define INT_TMRINTB1 BIT(7)
|
||||
|
||||
/* IER8 */
|
||||
#define INT_PMC2EXOBE BIT(0)
|
||||
#define INT_PMC2EXIBF BIT(1)
|
||||
#define INT_PMC3OBE BIT(2)
|
||||
#define INT_PMC3IBF BIT(3)
|
||||
#define INT_PMC4OBE BIT(4)
|
||||
#define INT_PMC4IBF BIT(5)
|
||||
#define INT_I2BRAM BIT(7)
|
||||
|
||||
/* IER9 */
|
||||
#define INT_WKO70 BIT(0)
|
||||
#define INT_WKO71 BIT(1)
|
||||
#define INT_WKO72 BIT(2)
|
||||
#define INT_WKO73 BIT(3)
|
||||
#define INT_WKO74 BIT(4)
|
||||
#define INT_WKO75 BIT(5)
|
||||
#define INT_WKO76 BIT(6)
|
||||
#define INT_WKO77 BIT(7)
|
||||
|
||||
/* IER10 */
|
||||
#define INT_ET8INTR BIT(0)
|
||||
#define INT_SMBUSCHINER BIT(1)
|
||||
#define INT_CEC BIT(2)
|
||||
#define INT_H2RAMLPC BIT(3)
|
||||
#define INT_KBSDVINTR BIT(4)
|
||||
#define INT_WKO88 BIT(5)
|
||||
#define INT_WKO89 BIT(6)
|
||||
#define INT_WKO90 BIT(7)
|
||||
|
||||
/* IER11 */
|
||||
#define INT_WKO80 BIT(0)
|
||||
#define INT_WKO81 BIT(1)
|
||||
#define INT_WKO82 BIT(2)
|
||||
#define INT_WKO83 BIT(3)
|
||||
#define INT_WKO84 BIT(4)
|
||||
#define INT_WKO85 BIT(5)
|
||||
#define INT_WKO86 BIT(6)
|
||||
#define INT_WKO87 BIT(7)
|
||||
|
||||
/* IER12 */
|
||||
#define INT_WKO91 BIT(0)
|
||||
#define INT_WKO92 BIT(1)
|
||||
#define INT_WKO93 BIT(2)
|
||||
#define INT_WKO94 BIT(3)
|
||||
#define INT_WKO95 BIT(4)
|
||||
#define INT_WKO96 BIT(5)
|
||||
#define INT_WKO97 BIT(6)
|
||||
#define INT_WKO98 BIT(7)
|
||||
|
||||
/* IER13 */
|
||||
#define INT_WKO99 BIT(0)
|
||||
#define INT_WKO100 BIT(1)
|
||||
#define INT_WKO101 BIT(2)
|
||||
#define INT_WKO102 BIT(3)
|
||||
#define INT_WKO103 BIT(4)
|
||||
#define INT_WKO104 BIT(5)
|
||||
#define INT_WKO105 BIT(6)
|
||||
#define INT_WKO106 BIT(7)
|
||||
|
||||
/* IER14 */
|
||||
#define INT_WKO107 BIT(0)
|
||||
#define INT_WKO108 BIT(1)
|
||||
#define INT_WKO109 BIT(2)
|
||||
#define INT_WKO110 BIT(3)
|
||||
#define INT_WKO111 BIT(4)
|
||||
#define INT_WKO112 BIT(5)
|
||||
#define INT_WKO113 BIT(6)
|
||||
#define INT_WKO114 BIT(7)
|
||||
|
||||
/* IER15 */
|
||||
#define INT_WKO115 BIT(0)
|
||||
#define INT_WKO116 BIT(1)
|
||||
#define INT_WKO117 BIT(2)
|
||||
#define INT_WKO118 BIT(3)
|
||||
#define INT_WKO119 BIT(4)
|
||||
#define INT_WKO120 BIT(5)
|
||||
#define INT_WKO121 BIT(6)
|
||||
#define INT_WKO122 BIT(7)
|
||||
|
||||
/* IER16 */
|
||||
#define INT_WKO128 BIT(0)
|
||||
#define INT_WKO129 BIT(1)
|
||||
#define INT_WKO130 BIT(2)
|
||||
#define INT_WKO131 BIT(3)
|
||||
#define INT_WKO132 BIT(4)
|
||||
#define INT_WKO133 BIT(5)
|
||||
#define INT_WKO134 BIT(6)
|
||||
|
||||
/* IER18 */
|
||||
#define INT_PMC5OBE BIT(5)
|
||||
#define INT_PMC5IBE BIT(6)
|
||||
#define INT_VCI BIT(7)
|
||||
|
||||
/* IER19 */
|
||||
#define INT_SMBUSE BIT(0)
|
||||
#define INT_SMBUSF BIT(1)
|
||||
#define INT_OSCDMAINTER BIT(2)
|
||||
#define INT_ET3INTR BIT(3)
|
||||
#define INT_ET4INTR BIT(4)
|
||||
#define INT_ET5INTR BIT(5)
|
||||
#define INT_ET6INTR BIT(6)
|
||||
#define INT_ET7INTR BIT(7)
|
||||
|
||||
/**
|
||||
*
|
||||
|
|
@ -855,105 +657,20 @@
|
|||
#define GCR19 ECREG(EC_REG_BASE_ADDR + 0x16E4)
|
||||
#define GCR20 ECREG(EC_REG_BASE_ADDR + 0x16E5)
|
||||
#define GCR21 ECREG(EC_REG_BASE_ADDR + 0x16E6)
|
||||
#define GPDRA ECREG(EC_REG_BASE_ADDR + 0x1601)
|
||||
#define GPDRB ECREG(EC_REG_BASE_ADDR + 0x1602)
|
||||
#define GPDRC ECREG(EC_REG_BASE_ADDR + 0x1603)
|
||||
#define GPDRD ECREG(EC_REG_BASE_ADDR + 0x1604)
|
||||
#define GPDRE ECREG(EC_REG_BASE_ADDR + 0x1605)
|
||||
#define GPDRF ECREG(EC_REG_BASE_ADDR + 0x1606)
|
||||
#define GPDRG ECREG(EC_REG_BASE_ADDR + 0x1607)
|
||||
#define GPDRH ECREG(EC_REG_BASE_ADDR + 0x1608)
|
||||
#define GPDRI ECREG(EC_REG_BASE_ADDR + 0x1609)
|
||||
#define GPDRJ ECREG(EC_REG_BASE_ADDR + 0x160A)
|
||||
#define GPDRM ECREG(EC_REG_BASE_ADDR + 0x160D)
|
||||
|
||||
/*
|
||||
* TODO: use pinmux driver to enable uart function so we can remove these
|
||||
* registers' declaration.
|
||||
*/
|
||||
/* GPIO control register */
|
||||
#define GPCRA0 ECREG(EC_REG_BASE_ADDR + 0x1610)
|
||||
#define GPCRA1 ECREG(EC_REG_BASE_ADDR + 0x1611)
|
||||
#define GPCRA2 ECREG(EC_REG_BASE_ADDR + 0x1612)
|
||||
#define GPCRA3 ECREG(EC_REG_BASE_ADDR + 0x1613)
|
||||
#define GPCRA4 ECREG(EC_REG_BASE_ADDR + 0x1614)
|
||||
#define GPCRA5 ECREG(EC_REG_BASE_ADDR + 0x1615)
|
||||
#define GPCRA6 ECREG(EC_REG_BASE_ADDR + 0x1616)
|
||||
#define GPCRA7 ECREG(EC_REG_BASE_ADDR + 0x1617)
|
||||
#define GPCRB0 ECREG(EC_REG_BASE_ADDR + 0x1618)
|
||||
#define GPCRB1 ECREG(EC_REG_BASE_ADDR + 0x1619)
|
||||
#define GPCRB2 ECREG(EC_REG_BASE_ADDR + 0x161A)
|
||||
#define GPCRB3 ECREG(EC_REG_BASE_ADDR + 0x161B)
|
||||
#define GPCRB4 ECREG(EC_REG_BASE_ADDR + 0x161C)
|
||||
#define GPCRB5 ECREG(EC_REG_BASE_ADDR + 0x161D)
|
||||
#define GPCRB6 ECREG(EC_REG_BASE_ADDR + 0x161E)
|
||||
#define GPCRB7 ECREG(EC_REG_BASE_ADDR + 0x161F)
|
||||
#define GPCRC0 ECREG(EC_REG_BASE_ADDR + 0x1620)
|
||||
#define GPCRC1 ECREG(EC_REG_BASE_ADDR + 0x1621)
|
||||
#define GPCRC2 ECREG(EC_REG_BASE_ADDR + 0x1622)
|
||||
#define GPCRC3 ECREG(EC_REG_BASE_ADDR + 0x1623)
|
||||
#define GPCRC4 ECREG(EC_REG_BASE_ADDR + 0x1624)
|
||||
#define GPCRC5 ECREG(EC_REG_BASE_ADDR + 0x1625)
|
||||
#define GPCRC6 ECREG(EC_REG_BASE_ADDR + 0x1626)
|
||||
#define GPCRC7 ECREG(EC_REG_BASE_ADDR + 0x1627)
|
||||
#define GPCRD0 ECREG(EC_REG_BASE_ADDR + 0x1628)
|
||||
#define GPCRD1 ECREG(EC_REG_BASE_ADDR + 0x1629)
|
||||
#define GPCRD2 ECREG(EC_REG_BASE_ADDR + 0x162A)
|
||||
#define GPCRD3 ECREG(EC_REG_BASE_ADDR + 0x162B)
|
||||
#define GPCRD4 ECREG(EC_REG_BASE_ADDR + 0x162C)
|
||||
#define GPCRD5 ECREG(EC_REG_BASE_ADDR + 0x162D)
|
||||
#define GPCRD6 ECREG(EC_REG_BASE_ADDR + 0x162E)
|
||||
#define GPCRD7 ECREG(EC_REG_BASE_ADDR + 0x162F)
|
||||
#define GPCRE0 ECREG(EC_REG_BASE_ADDR + 0x1630)
|
||||
#define GPCRE1 ECREG(EC_REG_BASE_ADDR + 0x1631)
|
||||
#define GPCRE2 ECREG(EC_REG_BASE_ADDR + 0x1632)
|
||||
#define GPCRE3 ECREG(EC_REG_BASE_ADDR + 0x1633)
|
||||
#define GPCRE4 ECREG(EC_REG_BASE_ADDR + 0x1634)
|
||||
#define GPCRE5 ECREG(EC_REG_BASE_ADDR + 0x1635)
|
||||
#define GPCRE6 ECREG(EC_REG_BASE_ADDR + 0x1636)
|
||||
#define GPCRE7 ECREG(EC_REG_BASE_ADDR + 0x1637)
|
||||
#define GPCRF0 ECREG(EC_REG_BASE_ADDR + 0x1638)
|
||||
#define GPCRF1 ECREG(EC_REG_BASE_ADDR + 0x1639)
|
||||
#define GPCRF2 ECREG(EC_REG_BASE_ADDR + 0x163A)
|
||||
#define GPCRF3 ECREG(EC_REG_BASE_ADDR + 0x163B)
|
||||
#define GPCRF4 ECREG(EC_REG_BASE_ADDR + 0x163C)
|
||||
#define GPCRF5 ECREG(EC_REG_BASE_ADDR + 0x163D)
|
||||
#define GPCRF6 ECREG(EC_REG_BASE_ADDR + 0x163E)
|
||||
#define GPCRF7 ECREG(EC_REG_BASE_ADDR + 0x163F)
|
||||
#define GPCRG0 ECREG(EC_REG_BASE_ADDR + 0x1640)
|
||||
#define GPCRG1 ECREG(EC_REG_BASE_ADDR + 0x1641)
|
||||
#define GPCRG2 ECREG(EC_REG_BASE_ADDR + 0x1642)
|
||||
#define GPCRG3 ECREG(EC_REG_BASE_ADDR + 0x1643)
|
||||
#define GPCRG4 ECREG(EC_REG_BASE_ADDR + 0x1644)
|
||||
#define GPCRG5 ECREG(EC_REG_BASE_ADDR + 0x1645)
|
||||
#define GPCRG6 ECREG(EC_REG_BASE_ADDR + 0x1646)
|
||||
#define GPCRG7 ECREG(EC_REG_BASE_ADDR + 0x1647)
|
||||
#define GPCRH0 ECREG(EC_REG_BASE_ADDR + 0x1648)
|
||||
#define GPCRH1 ECREG(EC_REG_BASE_ADDR + 0x1649)
|
||||
#define GPCRH2 ECREG(EC_REG_BASE_ADDR + 0x164A)
|
||||
#define GPCRH3 ECREG(EC_REG_BASE_ADDR + 0x164B)
|
||||
#define GPCRH4 ECREG(EC_REG_BASE_ADDR + 0x164C)
|
||||
#define GPCRH5 ECREG(EC_REG_BASE_ADDR + 0x164D)
|
||||
#define GPCRH6 ECREG(EC_REG_BASE_ADDR + 0x164E)
|
||||
#define GPCRI0 ECREG(EC_REG_BASE_ADDR + 0x1650)
|
||||
#define GPCRI1 ECREG(EC_REG_BASE_ADDR + 0x1651)
|
||||
#define GPCRI2 ECREG(EC_REG_BASE_ADDR + 0x1652)
|
||||
#define GPCRI3 ECREG(EC_REG_BASE_ADDR + 0x1653)
|
||||
#define GPCRI4 ECREG(EC_REG_BASE_ADDR + 0x1654)
|
||||
#define GPCRI5 ECREG(EC_REG_BASE_ADDR + 0x1655)
|
||||
#define GPCRI6 ECREG(EC_REG_BASE_ADDR + 0x1656)
|
||||
#define GPCRI7 ECREG(EC_REG_BASE_ADDR + 0x1657)
|
||||
#define GPCRJ0 ECREG(EC_REG_BASE_ADDR + 0x1658)
|
||||
#define GPCRJ1 ECREG(EC_REG_BASE_ADDR + 0x1659)
|
||||
#define GPCRJ2 ECREG(EC_REG_BASE_ADDR + 0x165A)
|
||||
#define GPCRJ3 ECREG(EC_REG_BASE_ADDR + 0x165B)
|
||||
#define GPCRJ4 ECREG(EC_REG_BASE_ADDR + 0x165C)
|
||||
#define GPCRJ5 ECREG(EC_REG_BASE_ADDR + 0x165D)
|
||||
#define GPCRJ6 ECREG(EC_REG_BASE_ADDR + 0x165E)
|
||||
#define GPCRJ7 ECREG(EC_REG_BASE_ADDR + 0x165F)
|
||||
#define GPCRM0 ECREG(EC_REG_BASE_ADDR + 0x16A0)
|
||||
#define GPCRM1 ECREG(EC_REG_BASE_ADDR + 0x16A1)
|
||||
#define GPCRM2 ECREG(EC_REG_BASE_ADDR + 0x16A2)
|
||||
#define GPCRM3 ECREG(EC_REG_BASE_ADDR + 0x16A3)
|
||||
#define GPCRM4 ECREG(EC_REG_BASE_ADDR + 0x16A4)
|
||||
#define GPCRM5 ECREG(EC_REG_BASE_ADDR + 0x16A5)
|
||||
#define GPCRM6 ECREG(EC_REG_BASE_ADDR + 0x16A6)
|
||||
|
||||
/* Port Data Mirror Register */
|
||||
#define GPDMRA ECREG(EC_REG_BASE_ADDR + 0x1661)
|
||||
|
|
@ -967,13 +684,6 @@
|
|||
#define GPDMRI ECREG(EC_REG_BASE_ADDR + 0x1669)
|
||||
#define GPDMRJ ECREG(EC_REG_BASE_ADDR + 0x166A)
|
||||
#define GPDMRM ECREG(EC_REG_BASE_ADDR + 0x166D)
|
||||
#define GPOTA ECREG(EC_REG_BASE_ADDR + 0x1671)
|
||||
#define GPOTB ECREG(EC_REG_BASE_ADDR + 0x1672)
|
||||
#define GPOTD ECREG(EC_REG_BASE_ADDR + 0x1674)
|
||||
#define GPOTE ECREG(EC_REG_BASE_ADDR + 0x1675)
|
||||
#define GPOTF ECREG(EC_REG_BASE_ADDR + 0x1676)
|
||||
#define GPOTH ECREG(EC_REG_BASE_ADDR + 0x1678)
|
||||
#define GPOTJ ECREG(EC_REG_BASE_ADDR + 0x167A)
|
||||
|
||||
/**
|
||||
*
|
||||
|
|
@ -1137,61 +847,15 @@
|
|||
#define PORSREGA ECREG(EC_REG_BASE_ADDR + 0x1A14)
|
||||
#define PORSREGB ECREG(EC_REG_BASE_ADDR + 0x1A15)
|
||||
|
||||
/**
|
||||
*
|
||||
* (1Bxxh) Wack-Up control (WUC)
|
||||
*
|
||||
*/
|
||||
#define WUEMR1 ECREG(EC_REG_BASE_ADDR + 0x1B00)
|
||||
#define WUEMR2 ECREG(EC_REG_BASE_ADDR + 0x1B01)
|
||||
#define WUEMR3 ECREG(EC_REG_BASE_ADDR + 0x1B02)
|
||||
#define WUEMR4 ECREG(EC_REG_BASE_ADDR + 0x1B03)
|
||||
#define WUEMR6 ECREG(EC_REG_BASE_ADDR + 0x1B10)
|
||||
#define WUEMR7 ECREG(EC_REG_BASE_ADDR + 0x1B14)
|
||||
#define WUEMR8 ECREG(EC_REG_BASE_ADDR + 0x1B18)
|
||||
#define WUEMR9 ECREG(EC_REG_BASE_ADDR + 0x1B1C)
|
||||
#define WUEMR10 ECREG(EC_REG_BASE_ADDR + 0x1B20)
|
||||
#define WUEMR11 ECREG(EC_REG_BASE_ADDR + 0x1B24)
|
||||
#define WUEMR12 ECREG(EC_REG_BASE_ADDR + 0x1B28)
|
||||
#define WUEMR13 ECREG(EC_REG_BASE_ADDR + 0x1B2C)
|
||||
#define WUEMR14 ECREG(EC_REG_BASE_ADDR + 0x1B30)
|
||||
#define WUESR1 ECREG(EC_REG_BASE_ADDR + 0x1B04)
|
||||
#define WUESR2 ECREG(EC_REG_BASE_ADDR + 0x1B05)
|
||||
#define WUESR3 ECREG(EC_REG_BASE_ADDR + 0x1B06)
|
||||
#define WUESR4 ECREG(EC_REG_BASE_ADDR + 0x1B07)
|
||||
#define WUESR6 ECREG(EC_REG_BASE_ADDR + 0x1B11)
|
||||
#define WUESR7 ECREG(EC_REG_BASE_ADDR + 0x1B15)
|
||||
#define WUESR8 ECREG(EC_REG_BASE_ADDR + 0x1B19)
|
||||
#define WUESR9 ECREG(EC_REG_BASE_ADDR + 0x1B1D)
|
||||
#define WUESR10 ECREG(EC_REG_BASE_ADDR + 0x1B21)
|
||||
#define WUESR11 ECREG(EC_REG_BASE_ADDR + 0x1B25)
|
||||
#define WUESR12 ECREG(EC_REG_BASE_ADDR + 0x1B29)
|
||||
#define WUESR13 ECREG(EC_REG_BASE_ADDR + 0x1B2D)
|
||||
#define WUESR14 ECREG(EC_REG_BASE_ADDR + 0x1B31)
|
||||
#define WUENR1 ECREG(EC_REG_BASE_ADDR + 0x1B08)
|
||||
#define WUENR2 ECREG(EC_REG_BASE_ADDR + 0x1B09)
|
||||
#define WUENR3 ECREG(EC_REG_BASE_ADDR + 0x1B0A)
|
||||
#define WUENR4 ECREG(EC_REG_BASE_ADDR + 0x1B0B)
|
||||
#define WUENR6 ECREG(EC_REG_BASE_ADDR + 0x1B12)
|
||||
#define WUENR7 ECREG(EC_REG_BASE_ADDR + 0x1B16)
|
||||
#define WUENR8 ECREG(EC_REG_BASE_ADDR + 0x1B1A)
|
||||
#define WUENR9 ECREG(EC_REG_BASE_ADDR + 0x1B1E)
|
||||
/* --- Wake-Up Control (WUC) --- */
|
||||
#define IT8XXX2_WUC_BASE 0x00F01B00
|
||||
|
||||
#define WUEMR6_BASE (EC_REG_BASE_ADDR + 0x1B10)
|
||||
#define WUESR6_BASE (EC_REG_BASE_ADDR + 0x1B11)
|
||||
#define WUBEMR6 ECREG(EC_REG_BASE_ADDR + 0x1B13)
|
||||
#define WUEMR8_BASE (EC_REG_BASE_ADDR + 0x1B18)
|
||||
#define WUESR8_BASE (EC_REG_BASE_ADDR + 0x1B19)
|
||||
#define WUBEMR8 ECREG(EC_REG_BASE_ADDR + 0x1B1B)
|
||||
#define WUEMR9_BASE (EC_REG_BASE_ADDR + 0x1B1C)
|
||||
#define WUESR9_BASE (EC_REG_BASE_ADDR + 0x1B1D)
|
||||
#define WUBEMR9 ECREG(EC_REG_BASE_ADDR + 0x1B1F)
|
||||
#define WUEMR10_BASE (EC_REG_BASE_ADDR + 0x1B20)
|
||||
#define WUESR10_BASE (EC_REG_BASE_ADDR + 0x1B21)
|
||||
#define WUBEMR10 ECREG(EC_REG_BASE_ADDR + 0x1B23)
|
||||
#define WUEMR11_BASE (EC_REG_BASE_ADDR + 0x1B24)
|
||||
#define WUESR11_BASE (EC_REG_BASE_ADDR + 0x1B25)
|
||||
#define WUBEMR11 ECREG(EC_REG_BASE_ADDR + 0x1B27)
|
||||
#define IT8XXX2_WUC_WUEMR1 (IT8XXX2_WUC_BASE + 0x00)
|
||||
#define IT8XXX2_WUC_WUEMR5 (IT8XXX2_WUC_BASE + 0x0c)
|
||||
#define IT8XXX2_WUC_WUESR1 (IT8XXX2_WUC_BASE + 0x04)
|
||||
#define IT8XXX2_WUC_WUESR5 (IT8XXX2_WUC_BASE + 0x0d)
|
||||
#define IT8XXX2_WUC_WUBEMR1 (IT8XXX2_WUC_BASE + 0x3c)
|
||||
#define IT8XXX2_WUC_WUBEMR5 (IT8XXX2_WUC_BASE + 0x0f)
|
||||
|
||||
/**
|
||||
*
|
||||
|
|
|
|||
|
|
@ -73,6 +73,7 @@ int riscv_plic_get_irq(void);
|
|||
#if CONFIG_ITE_IT8XXX2_INTC
|
||||
extern void ite_intc_irq_enable(unsigned int irq);
|
||||
extern void ite_intc_irq_disable(unsigned int irq);
|
||||
extern uint8_t ite_intc_get_irq_num(void);
|
||||
extern int ite_intc_irq_is_enable(unsigned int irq);
|
||||
extern void ite_intc_irq_priority_set(unsigned int irq,
|
||||
unsigned int prio, unsigned int flags);
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
|
|||
|
||||
if ITE_IT8XXX2_INTC
|
||||
config NUM_IRQS
|
||||
default 162
|
||||
default 185
|
||||
|
||||
config DYNAMIC_INTERRUPTS
|
||||
default y
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue