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drivers: memc: stm32: initial support for stm32 FMC

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This commit adds a new driver category for memory controller
peripherals. There is no API involved for now, as it has not been found
necessary for first implementation.

STM32 Flexible Memory Controller (FMC) is the only controller supported
for now. This peripheral allows to access multiple types of external
memories, e.g. SDRAM, NAND, NOR Flash...

The initial implementation adds support for the SDRAM controller only.
The HAL API is used, so the implementation should be portable to other
STM32 series. It has only been tested on H7 series, so for now it can
only be enabled when working on H7.

Linker facilities have also been added in order to allow applications to
easily define a variable in SDRAM.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas 2020-11-01 20:48:15 +01:00 • committed by Carles Cufí
commit e671d363b8
16 changed files with 574 additions and 0 deletions
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1
drivers/CMakeLists.txt
View file

@ -40,6 +40,7 @@ add_subdirectory_ifdef(CONFIG_EEPROM eeprom)
add_subdirectory_ifdef(CONFIG_LORA lora)
add_subdirectory_ifdef(CONFIG_PECI peci)
add_subdirectory_ifdef(CONFIG_REGULATOR regulator)
add_subdirectory_ifdef(CONFIG_MEMC memc)
add_subdirectory_ifdef(CONFIG_FLASH_HAS_DRIVER_ENABLED flash)
add_subdirectory_ifdef(CONFIG_SERIAL_HAS_DRIVER serial)

2
drivers/Kconfig
View file

@ -101,4 +101,6 @@ source "drivers/peci/Kconfig"
source "drivers/regulator/Kconfig"
source "drivers/memc/Kconfig"
endmenu

3
drivers/memc/CMakeLists.txt Normal file
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@ -0,0 +1,3 @@
zephyr_sources_ifdef(CONFIG_MEMC_STM32 memc_stm32.c)
zephyr_sources_ifdef(CONFIG_MEMC_STM32_SDRAM memc_stm32_sdram.c)
zephyr_linker_sources_ifdef(CONFIG_MEMC_STM32_SDRAM SECTIONS memc_stm32_sdram.ld)

25
drivers/memc/Kconfig Normal file
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@ -0,0 +1,25 @@
# Memory controller configuration options
# Copyright (c) 2020 Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0
menuconfig MEMC
bool "Memory controllers [EXPERIMENTAL]"
help
Add support for memory controllers
if MEMC
module = MEMC
module-str = memc
source "subsys/logging/Kconfig.template.log_config"
config MEMC_INIT_PRIORITY
int "Initialization priority"
default 0
help
Memory controllers initialization priority.
source "drivers/memc/Kconfig.stm32"
endif

19
drivers/memc/Kconfig.stm32 Normal file
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@ -0,0 +1,19 @@
# Copyright (c) 2020 Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0
config MEMC_STM32
bool "Enable STM32 Flexible Memory Controller (FMC)"
depends on SOC_SERIES_STM32H7X
help
Enable STM32 Flexible Memory Controller.
DT_COMPAT_ST_STM32_FMC_SDRAM := st,stm32-fmc-sdram
config MEMC_STM32_SDRAM
bool "Enable STM32 FMC SDRAM controller"
depends on MEMC_STM32
default $(dt_compat_enabled,$(DT_COMPAT_ST_STM32_FMC_SDRAM))
select USE_STM32_LL_FMC
select USE_STM32_HAL_SDRAM
help
Enable STM32 FMC SDRAM controller.

63
drivers/memc/memc_stm32.c Normal file
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@ -0,0 +1,63 @@
/*
* Copyright (c) 2020 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT st_stm32_fmc
#include <device.h>
#include <drivers/clock_control/stm32_clock_control.h>
#include <pinmux/stm32/pinmux_stm32.h>
#include <logging/log.h>
LOG_MODULE_REGISTER(memc_stm32, CONFIG_MEMC_LOG_LEVEL);
struct memc_stm32_config {
uint32_t fmc;
struct stm32_pclken pclken;
const struct soc_gpio_pinctrl *pinctrl;
size_t pinctrl_len;
};
static int memc_stm32_init(const struct device *dev)
{
const struct memc_stm32_config *config = dev->config;
int r;
const struct device *clk;
/* configure pinmux */
r = stm32_dt_pinctrl_configure(config->pinctrl, config->pinctrl_len,
config->fmc);
if (r < 0) {
LOG_ERR("FMC pinctrl setup failed (%d)", r);
return r;
}
/* enable FMC peripheral clock */
clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
__ASSERT_NO_MSG(clk);
r = clock_control_on(clk, (clock_control_subsys_t *)&config->pclken);
if (r < 0) {
LOG_ERR("Could not initialize FMC clock (%d)", r);
return r;
}
return 0;
}
static const struct soc_gpio_pinctrl pinctrl[] = ST_STM32_DT_INST_PINCTRL(0, 0);
static const struct memc_stm32_config config = {
.fmc = DT_INST_REG_ADDR(0),
.pclken = { .bus = DT_INST_CLOCKS_CELL(0, bus),
.enr = DT_INST_CLOCKS_CELL(0, bits) },
.pinctrl = pinctrl,
.pinctrl_len = ARRAY_SIZE(pinctrl),
};
DEVICE_DEFINE(memc_stm32, DT_INST_LABEL(0), memc_stm32_init, NULL, NULL,
&config, POST_KERNEL, CONFIG_MEMC_INIT_PRIORITY, NULL);

133
drivers/memc/memc_stm32_sdram.c Normal file
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@ -0,0 +1,133 @@
/*
* Copyright (c) 2020 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT st_stm32_fmc_sdram
#include <device.h>
#include <soc.h>
#include <logging/log.h>
LOG_MODULE_REGISTER(memc_stm32_sdram, CONFIG_MEMC_LOG_LEVEL);
/** SDRAM controller register offset. */
#define SDRAM_OFFSET 0x140U
/** FMC SDRAM controller bank configuration fields. */
struct memc_stm32_sdram_bank_config {
FMC_SDRAM_InitTypeDef init;
FMC_SDRAM_TimingTypeDef timing;
};
/** FMC SDRAM controller configuration fields. */
struct memc_stm32_sdram_config {
FMC_SDRAM_TypeDef *sdram;
uint32_t power_up_delay;
uint8_t num_auto_refresh;
uint16_t mode_register;
uint16_t refresh_rate;
const struct memc_stm32_sdram_bank_config *banks;
size_t banks_len;
};
static int memc_stm32_sdram_init(const struct device *dev)
{
const struct memc_stm32_sdram_config *config = dev->config;
SDRAM_HandleTypeDef sdram = { 0 };
FMC_SDRAM_CommandTypeDef sdram_cmd = { 0 };
sdram.Instance = config->sdram;
for (size_t i = 0U; i < config->banks_len; i++) {
sdram.State = HAL_SDRAM_STATE_RESET;
memcpy(&sdram.Init, &config->banks[i].init, sizeof(sdram.Init));
(void)HAL_SDRAM_Init(
&sdram,
(FMC_SDRAM_TimingTypeDef *)&config->banks[i].timing);
}
/* SDRAM initialization sequence */
if (config->banks_len == 2U) {
sdram_cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1_2;
} else if (config->banks[0].init.SDBank == FMC_SDRAM_BANK1) {
sdram_cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
} else {
sdram_cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
}
sdram_cmd.AutoRefreshNumber = config->num_auto_refresh;
sdram_cmd.ModeRegisterDefinition = config->mode_register;
/* enable clock */
sdram_cmd.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
(void)HAL_SDRAM_SendCommand(&sdram, &sdram_cmd, 0U);
k_usleep(config->power_up_delay);
/* pre-charge all */
sdram_cmd.CommandMode = FMC_SDRAM_CMD_PALL;
(void)HAL_SDRAM_SendCommand(&sdram, &sdram_cmd, 0U);
/* auto-refresh */
sdram_cmd.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
(void)HAL_SDRAM_SendCommand(&sdram, &sdram_cmd, 0U);
/* load mode */
sdram_cmd.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
(void)HAL_SDRAM_SendCommand(&sdram, &sdram_cmd, 0U);
/* program refresh count */
(void)HAL_SDRAM_ProgramRefreshRate(&sdram, config->refresh_rate);
return 0;
}
/** SDRAM bank/s configuration initialization macro. */
#define BANK_CONFIG(node_id) \
{ .init = { \
.SDBank = DT_REG_ADDR(node_id), \
.ColumnBitsNumber = DT_PROP_BY_IDX(node_id, st_sdram_control, 0), \
.RowBitsNumber = DT_PROP_BY_IDX(node_id, st_sdram_control, 1), \
.MemoryDataWidth = DT_PROP_BY_IDX(node_id, st_sdram_control, 2), \
.InternalBankNumber = DT_PROP_BY_IDX(node_id, st_sdram_control, 3),\
.CASLatency = DT_PROP_BY_IDX(node_id, st_sdram_control, 4), \
.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE, \
.SDClockPeriod = DT_PROP_BY_IDX(node_id, st_sdram_control, 5), \
.ReadBurst = DT_PROP_BY_IDX(node_id, st_sdram_control, 6), \
.ReadPipeDelay = DT_PROP_BY_IDX(node_id, st_sdram_control, 7), \
}, \
.timing = { \
.LoadToActiveDelay = DT_PROP_BY_IDX(node_id, st_sdram_timing, 0), \
.ExitSelfRefreshDelay = \
DT_PROP_BY_IDX(node_id, st_sdram_timing, 1), \
.SelfRefreshTime = DT_PROP_BY_IDX(node_id, st_sdram_timing, 2), \
.RowCycleDelay = DT_PROP_BY_IDX(node_id, st_sdram_timing, 3), \
.WriteRecoveryTime = DT_PROP_BY_IDX(node_id, st_sdram_timing, 4), \
.RPDelay = DT_PROP_BY_IDX(node_id, st_sdram_timing, 5), \
.RCDDelay = DT_PROP_BY_IDX(node_id, st_sdram_timing, 6), \
} \
},
/** SDRAM bank/s configuration. */
static const struct memc_stm32_sdram_bank_config bank_config[] = {
DT_INST_FOREACH_CHILD(0, BANK_CONFIG)
};
/** SDRAM configuration. */
static const struct memc_stm32_sdram_config config = {
.sdram = (FMC_SDRAM_TypeDef *)(DT_REG_ADDR(DT_PARENT(DT_DRV_INST(0))) +
SDRAM_OFFSET),
.power_up_delay = DT_INST_PROP(0, power_up_delay),
.num_auto_refresh = DT_INST_PROP(0, num_auto_refresh),
.mode_register = DT_INST_PROP(0, mode_register),
.refresh_rate = DT_INST_PROP(0, refresh_rate),
.banks = bank_config,
.banks_len = ARRAY_SIZE(bank_config),
};
DEVICE_DEFINE(memc_stm32_sdram, DT_INST_LABEL(0), memc_stm32_sdram_init, NULL,
NULL, &config, POST_KERNEL, CONFIG_MEMC_INIT_PRIORITY, NULL);

29
drivers/memc/memc_stm32_sdram.ld Normal file
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@ -0,0 +1,29 @@
/*
* Copyright (c) 2020 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram1), okay)
GROUP_START(SDRAM1)
SECTION_PROLOGUE(_STM32_SDRAM1_SECTION_NAME, (NOLOAD),)
{
*(.stm32_sdram1)
*(".stm32_sdram1.*")
} GROUP_LINK_IN(SDRAM1)
GROUP_END(SDRAM1)
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram2), okay)
GROUP_START(SDRAM2)
SECTION_PROLOGUE(_STM32_SDRAM2_SECTION_NAME, (NOLOAD),)
{
*(.stm32_sdram2)
*(".stm32_sdram2.*")
} GROUP_LINK_IN(SDRAM2)
GROUP_END(SDRAM2)
#endif

17
dts/arm/st/h7/stm32h7.dtsi
View file

@ -11,6 +11,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/memory-controller/stm32-fmc-sdram.h>
/ {
chosen {
@ -698,6 +699,22 @@
<&rcc STM32_CLOCK_BUS_AHB1 0x00020000>;
status = "disabled";
};
fmc: memory-controller@52004000 {
compatible = "st,stm32-fmc";
reg = <0x52004000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00001000>;
label = "STM32_FMC";
status = "disabled";
sdram: sdram {
compatible = "st,stm32-fmc-sdram";
#address-cells = <1>;
#size-cells = <0>;
label = "STM32_FMC_SDRAM";
status = "disabled";
};
};
};
};

165
dts/bindings/memory-controllers/st,stm32-fmc-sdram.yaml Normal file
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@ -0,0 +1,165 @@
# Copyright (c) 2020, Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0
description: |
STM32 Flexible Memory Controller (SDRAM controller).
The FMC SDRAM controller can be used to interface with external SDRAM
memories. Up to 2 SDRAM banks are supported with independent configuration. It
is worth to note that while settings are independent, some are shared or are
required to be set according to the most constraining device. Refer to the
properties description or the datasheet for more details.
The FMC SDRAM controller is defined below the FMC node and SDRAM banks are
defined as child nodes of the FMC SDRAM node. You can either have bank 1 (@0),
bank 2 (@1) or both. You can enable the FMC SDRAM controller in your board
DeviceTree file like this:
&fmc {
status = "okay";
pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;
sdram {
status = "okay";
power-up-delay = <100>;
num-auto-refresh = <8>;
mode-register = <0x220>;
refresh-rate = <603>;
bank@0 {
reg = <0>;
st,sdram-control = <STM32_FMC_SDRAM_NC_9
STM32_FMC_SDRAM_NR_12
STM32_FMC_SDRAM_MWID_32
STM32_FMC_SDRAM_NB_4
STM32_FMC_SDRAM_CAS_2
STM32_FMC_SDRAM_SDCLK_PERIOD_2
STM32_FMC_SDRAM_RBURST_ENABLE
STM32_FMC_SDRAM_RPIPE_0>;
st,sdram-timing = <2 6 4 6 2 2 2>;
};
bank@1 {
reg = <1>;
...
};
};
};
Note that you will find definitions for the st,sdram-control field at
dt-bindings/memory-controller/stm32-fmc-sdram.h. This file is already included
in the SoC DeviceTree files.
Finally, in order to make the memory available you will need to define new
memory device/s in DeviceTree:
sdram1: sdram@c0000000 {
device_type = "memory";
reg = <0xc000000 DT_SIZE_M(X)>;
};
sdram2: sdram@d0000000 {
device_type = "memory";
reg = <0xd000000 DT_SIZE_M(X)>;
};
It is important to use sdram1 and sdram2 node labels for bank 1 and bank 2
respectively. Memory addresses are 0xc0000000 and 0xd0000000 for bank 1 and
bank 2 respectively.
compatible: "st,stm32-fmc-sdram"
include: base.yaml
properties:
label:
required: true
"#address-cells":
required: true
const: 1
"#size-cells":
required: true
const: 0
power-up-delay:
type: int
default: 100
description: Power-up delay in microseconds.
num-auto-refresh:
type: int
default: 8
description: Number of auto-refresh commands issued.
mode-register:
type: int
required: true
description:
A 14-bit field that defines the SDRAM Mode Register content. The mode
register bits are also used to program the extended mode register for
mobile SDRAM.
refresh-rate:
type: int
required: true
description:
A 13-bit field defines the refresh rate of the SDRAM device. It is
expressed in number of memory clock cycles. It must be set at least to
41 SDRAM clock cycles.
child-binding:
description: SDRAM bank.
properties:
reg:
type: int
required: true
st,sdram-control:
type: array
required: true
description: |
SDRAM control configuration. Expected fields, in order, are,
- NC: Number of bits of a column address.
- NR: Number of bits of a row address.
- MWID: Memory device width.
- NB: Number of internal banks.
- CAS: SDRAM CAS latency in number of memory clock cycles.
- SDCLK: SDRAM clock period. If two SDRAM devices are used both should
have the same value.
- RBURST: Enable burst read mode. If two SDRAM devices are used both
should have the same value.
- RPIPE: Delay, in fmc_ker_ck clock cycles, for reading data after CAS
latency. If two SDRAM devices are used both should have the same
value.
st,sdram-timing:
type: array
required: true
description: |
SDRAM timing configuration. Expected fields, in order, are,
- TMRD: Delay between a Load Mode Register command and an Active or
Refresh command in number of memory clock cycles.
- TXSR: Delay from releasing the Self-refresh command to issuing the
Activate command in number of memory clock cycles. If two SDRAM
devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with
the same TXSR timing corresponding to the slowest SDRAM device
- TRAS: Minimum Self-refresh period in number of memory clock cycles.
- TRC: Delay between the Refresh command and the Activate command, as
well as the delay between two consecutive Refresh commands. It is
expressed in number of memory clock cycles. If two SDRAM devices are
used, the TRC must be programmed with the timings of the slowest
device in both banks.
- TWP: Delay between a Write and a Precharge command in number of memory
clock cycles
- TRP: Delay between a Precharge command and another command in number
of memory clock cycles. If two SDRAM devices are used, the TRP must be
programmed with the timing of the slowest device in both banks.
- TRCD: Delay between the Activate command and a Read/Write command in
number of memory clock cycles.

51
dts/bindings/memory-controllers/st,stm32-fmc.yaml Normal file
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@ -0,0 +1,51 @@
# Copyright (c) 2020, Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0
description: |
STM32 Flexible Memory Controller (FMC).
The FMC allows to interface with static-memory mapped external devices such as
SRAM, NOR Flash, NAND Flash, SDRAM...
All external memories share the addresses, data and control signals with the
controller. Each external device is accessed by means of a unique chip select.
The FMC performs only one access at a time to an external device.
The flexible memory controller includes three memory controllers:
- NOR/PSRAM memory controller
- NAND memory controller (some devices also support PC Card)
- Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
Each memory controller is defined below the FMC DeviceTree node and is managed
by a separate Zephyr device. However, because signals are shared the FMC
device handles the signals and the peripheral clocks. FMC can be enabled
in your board DeviceTree file like this:
&fmc {
status = "okay";
pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;
};
compatible: "st,stm32-fmc"
include: base.yaml
properties:
reg:
required: true
label:
required: true
clocks:
required: true
pinctrl-0:
type: phandles
required: false
description: |
GPIO pin configuration for FMC signals. We expect that the phandles
will reference pinctrl nodes, e.g.
pinctrl-0 = <&fmc_a0_pf0 &fmc_a1_pf1...>;

8
include/arch/arm/aarch32/cortex_m/scripts/linker.ld
View file

@ -105,6 +105,14 @@ MEMORY
#ifdef CONFIG_BT_STM32_IPM
SRAM1 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE
SRAM2 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE
#endif
#ifdef CONFIG_MEMC_STM32_SDRAM
#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram1), okay)
SDRAM1 (rw) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram1)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram1))
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram2), okay)
SDRAM2 (rw) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram2)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram2))
#endif
#endif
/* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K

49
include/dt-bindings/memory-controller/stm32-fmc-sdram.h Normal file
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@ -0,0 +1,49 @@
/*
* Copyright (c) 2020 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SDRAM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SDRAM_H_
/* Number of column address bits */
#define STM32_FMC_SDRAM_NC_8 0x00000000UL
#define STM32_FMC_SDRAM_NC_9 0x00000001UL
#define STM32_FMC_SDRAM_NC_10 0x00000002UL
#define STM32_FMC_SDRAM_NC_11 0x00000003UL
/* Number of row address bits */
#define STM32_FMC_SDRAM_NR_11 0x00000000UL
#define STM32_FMC_SDRAM_NR_12 0x00000004UL
#define STM32_FMC_SDRAM_NR_13 0x00000008UL
/* Memory data bus width. */
#define STM32_FMC_SDRAM_MWID_8 0x00000000UL
#define STM32_FMC_SDRAM_MWID_16 0x00000010UL
#define STM32_FMC_SDRAM_MWID_32 0x00000020UL
/* Number of internal banks */
#define STM32_FMC_SDRAM_NB_2 0x00000000UL
#define STM32_FMC_SDRAM_NB_4 0x00000040UL
/* CAS Latency */
#define STM32_FMC_SDRAM_CAS_1 0x00000080UL
#define STM32_FMC_SDRAM_CAS_2 0x00000100UL
#define STM32_FMC_SDRAM_CAS_3 0x00000180UL
/* SDRAM clock configuration */
#define STM32_FMC_SDRAM_SDCLK_DISABLE 0x00000000UL
#define STM32_FMC_SDRAM_SDCLK_PERIOD_2 0x00000800UL
#define STM32_FMC_SDRAM_SDCLK_PERIOD_3 0x00000C00UL
/* Burst read */
#define STM32_FMC_SDRAM_RBURST_DISABLE 0x00000000UL
#define STM32_FMC_SDRAM_RBURST_ENABLE 0x00001000UL
/* Read pipe */
#define STM32_FMC_SDRAM_RPIPE_0 0x00000000UL
#define STM32_FMC_SDRAM_RPIPE_1 0x00002000UL
#define STM32_FMC_SDRAM_RPIPE_2 0x00004000UL
#endif

2
include/linker/section_tags.h
View file

@ -30,6 +30,8 @@
#define __imx_boot_data_section Z_GENERIC_SECTION(_IMX_BOOT_DATA_SECTION_NAME)
#define __imx_boot_ivt_section Z_GENERIC_SECTION(_IMX_BOOT_IVT_SECTION_NAME)
#define __imx_boot_dcd_section Z_GENERIC_SECTION(_IMX_BOOT_DCD_SECTION_NAME)
#define __stm32_sdram1_section Z_GENERIC_SECTION(_STM32_SDRAM1_SECTION_NAME)
#define __stm32_sdram2_section Z_GENERIC_SECTION(_STM32_SDRAM2_SECTION_NAME)
#endif /* CONFIG_ARM */
#if defined(CONFIG_NOCACHE_MEMORY)

3
include/linker/sections.h
View file

@ -53,6 +53,9 @@
#define _IMX_BOOT_IVT_SECTION_NAME .boot_hdr.ivt
#define _IMX_BOOT_DCD_SECTION_NAME .boot_hdr.dcd_data
#define _STM32_SDRAM1_SECTION_NAME .stm32_sdram1
#define _STM32_SDRAM2_SECTION_NAME .stm32_sdram2
#ifdef CONFIG_NOCACHE_MEMORY
#define _NOCACHE_SECTION_NAME nocache
#endif

4
soc/arm/st_stm32/common/Kconfig.defconfig.series
View file

@ -81,4 +81,8 @@ config HEAP_MEM_POOL_SIZE
endif # DMA
config MEMC_STM32
default y
depends on MEMC
endif # SOC_FAMILY_STM32