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Revert "arch: riscv: added support for custom initialization of gp register"

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This reverts commit 7b09d031fa. Because
context save of GP register is removed, we don't need to initialize GP
at thread init. GP will be a constant value so that it could only be
initialized at program start.

Signed-off-by: Jim Shu <cwshu@andestech.com>
This commit is contained in:
Jim Shu 2021-08-03 01:53:19 +08:00 • committed by Christopher Friedt
commit 97fa203330
4 changed files with 0 additions and 18 deletions
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6
arch/riscv/Kconfig
View file

@ -90,12 +90,6 @@ config RISCV_SOC_INTERRUPT_INIT
Enable SOC-based interrupt initialization
(call soc_interrupt_init, within _IntLibInit when enabled)
config RISCV_SOC_INIT_GP_VALUE
bool "Enable SOC-based global pointer register initialization"
help
Enable SOC-based pointer register initialization
(call __soc_get_gp_initial_value when initializing a thread)
config RISCV_GENERIC_TOOLCHAIN
bool "Compile using generic riscv32 toolchain"
default y

4
arch/riscv/core/thread.c
View file

@ -47,10 +47,6 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
stack_init->a2 = (ulong_t)p2;
stack_init->a3 = (ulong_t)p3;
#ifdef CONFIG_RISCV_SOC_INIT_GP_VALUE
stack_init->gp = __soc_get_gp_initial_value();
#endif
#ifdef CONFIG_THREAD_LOCAL_STORAGE
stack_init->tp = (ulong_t)thread->tls;
#endif

6
soc/riscv/esp32c3/soc.c
View file

@ -186,9 +186,3 @@ int arch_irq_is_enabled(unsigned int irq)
{
return (REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG) & (1 << irq));
}
ulong_t __soc_get_gp_initial_value(void)
{
extern uint32_t __global_pointer$;
return (ulong_t)&__global_pointer$;
}

2
soc/riscv/esp32c3/soc.h
View file

@ -41,8 +41,6 @@ extern STATUS esp_rom_uart_tx_one_char(uint8_t chr);
extern STATUS esp_rom_uart_rx_one_char(uint8_t *chr);
extern void esp_rom_ets_set_user_start(uint32_t start);
ulong_t __soc_get_gp_initial_value(void);
#endif /* _ASMLANGUAGE */
#endif /* __SOC_H__ */