drivers: adc: added support adc driver for lpcexpresso55s69
Added shim driver for the LPADC for lpcexpresso55s69 board. Fixes #22703. Signed-off-by: Toby Firth <tobyjfirth@gmail.com>
This commit is contained in:
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14 changed files with 531 additions and 0 deletions
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@ -72,6 +72,8 @@ features:
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+-----------+------------+-------------------------------------+
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| TrustZone | on-chip | Trusted Firmware-M |
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+-----------+------------+-------------------------------------+
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| ADC | on-chip | adc |
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+-----------+------------+-------------------------------------+
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The default configuration file
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``boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0_defconfig``
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@ -80,3 +80,7 @@
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&wwdt0 {
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status = "okay";
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};
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&adc0 {
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status = "okay";
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};
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@ -15,6 +15,7 @@ toolchain:
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- gnuarmemb
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- xtools
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supported:
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- adc
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- arduino_i2c
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- arduino_spi
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- gpio
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@ -84,3 +84,7 @@
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&wwdt0 {
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status = "okay";
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};
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&adc0 {
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status = "okay";
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};
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@ -15,6 +15,7 @@ toolchain:
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- gnuarmemb
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- xtools
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supported:
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- adc
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- arduino_spi
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- gpio
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- spi
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@ -6,6 +6,7 @@ zephyr_library_sources_ifdef(CONFIG_ADC adc_common.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_SHELL adc_shell.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC12 adc_mcux_adc12.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC16 adc_mcux_adc16.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_LPADC adc_mcux_lpadc.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_SAM_AFEC adc_sam_afec.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_NRFX_ADC adc_nrfx_adc.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_NRFX_SAADC adc_nrfx_saadc.c)
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@ -15,6 +15,12 @@ config ADC_MCUX_ADC16
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help
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Enable the MCUX ADC16 driver.
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config ADC_MCUX_LPADC
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bool "MCUX LPADC driver"
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depends on HAS_MCUX_LPADC
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help
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Enable the MCUX LPADC driver.
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if ADC_MCUX_ADC16
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choice
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@ -48,3 +54,13 @@ config ADC_MCUX_ADC16_VREF_ALTERNATE
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endchoice
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endif # ADC_MCUX_ADC16
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if ADC_MCUX_LPADC
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config LPADC_DO_OFFSET_CALIBRATION
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bool "Do offset calibration"
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help
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Do offset calibration
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endif # ADC_MCUX_LPADC
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411
drivers/adc/adc_mcux_lpadc.c
Normal file
411
drivers/adc/adc_mcux_lpadc.c
Normal file
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@ -0,0 +1,411 @@
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/*
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* Copyright (c) 2020 Toby Firth
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*
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* Based on adc_mcux_adc16.c and adc_mcux_adc12.c, which are:
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* Copyright (c) 2017-2018, NXP
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* Copyright (c) 2019 Vestas Wind Systems A/S
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_lpc_lpadc
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#include <errno.h>
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#include <drivers/adc.h>
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#include <fsl_lpadc.h>
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#include <fsl_power.h>
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#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(nxp_mcux_lpadc);
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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struct mcux_lpadc_config {
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ADC_Type *base;
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uint32_t clock_div;
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uint32_t clock_source;
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lpadc_reference_voltage_source_t voltage_ref;
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#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS)\
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&& FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
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lpadc_conversion_average_mode_t calibration_average;
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#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
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lpadc_power_level_mode_t power_level;
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uint32_t offset_a;
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uint32_t offset_b;
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void (*irq_config_func)(const struct device *dev);
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};
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struct mcux_lpadc_data {
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const struct device *dev;
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struct adc_context ctx;
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uint16_t *buffer;
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uint16_t *repeat_buffer;
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uint32_t channels;
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uint8_t channel_id;
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lpadc_hardware_average_mode_t average;
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#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) \
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&& FSL_FEATURE_LPADC_HAS_CMDL_MODE
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lpadc_conversion_resolution_mode_t resolution;
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#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
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};
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static int mcux_lpadc_channel_setup(const struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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uint8_t channel_id = channel_cfg->channel_id;
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if (channel_id > 31) {
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LOG_ERR("Channel %d is not valid", channel_id);
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return -EINVAL;
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}
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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LOG_ERR("Invalid channel acquisition time");
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return -EINVAL;
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}
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if (channel_cfg->differential) {
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LOG_ERR("Differential channels are not supported");
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return -EINVAL;
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}
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if (channel_cfg->gain != ADC_GAIN_1) {
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LOG_ERR("Invalid channel gain");
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return -EINVAL;
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}
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if (channel_cfg->reference != ADC_REF_EXTERNAL0) {
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LOG_ERR("Invalid channel reference");
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return -EINVAL;
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}
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return 0;
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}
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static int mcux_lpadc_start_read(const struct device *dev,
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const struct adc_sequence *sequence)
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{
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struct mcux_lpadc_data *data = dev->data;
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#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) \
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&& FSL_FEATURE_LPADC_HAS_CMDL_MODE
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switch (sequence->resolution) {
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case 12:
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case 13:
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data->resolution = kLPADC_ConversionResolutionStandard;
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break;
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case 16:
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data->resolution = kLPADC_ConversionResolutionHigh;
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break;
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default:
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LOG_ERR("Unsupported resolution %d", sequence->resolution);
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return -ENOTSUP;
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}
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#else
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/* If FSL_FEATURE_LPADC_HAS_CMDL_MODE is not defined
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only 12/13 bit resolution is supported. */
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if (sequence->resolution != 12 || sequence->resolution != 13) {
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LOG_ERR("Unsupported resolution %d", sequence->resolution);
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return -ENOTSUP;
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}
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#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
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switch (sequence->oversampling) {
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case 0:
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data->average = kLPADC_HardwareAverageCount1;
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break;
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case 1:
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data->average = kLPADC_HardwareAverageCount2;
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break;
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case 2:
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data->average = kLPADC_HardwareAverageCount4;
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break;
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case 3:
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data->average = kLPADC_HardwareAverageCount8;
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break;
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case 4:
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data->average = kLPADC_HardwareAverageCount16;
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break;
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case 5:
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data->average = kLPADC_HardwareAverageCount32;
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break;
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case 6:
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data->average = kLPADC_HardwareAverageCount64;
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break;
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case 7:
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data->average = kLPADC_HardwareAverageCount128;
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break;
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default:
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LOG_ERR("Unsupported oversampling value %d",
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sequence->oversampling);
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return -ENOTSUP;
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}
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data->buffer = sequence->buffer;
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adc_context_start_read(&data->ctx, sequence);
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int error = adc_context_wait_for_completion(&data->ctx);
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return error;
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}
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static int mcux_lpadc_read_async(const struct device *dev,
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const struct adc_sequence *sequence,
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struct k_poll_signal *async)
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{
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struct mcux_lpadc_data *data = dev->data;
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int error;
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adc_context_lock(&data->ctx, async ? true : false, async);
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error = mcux_lpadc_start_read(dev, sequence);
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adc_context_release(&data->ctx, error);
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return error;
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}
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static int mcux_lpadc_read(const struct device *dev,
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const struct adc_sequence *sequence)
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{
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return mcux_lpadc_read_async(dev, sequence, NULL);
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}
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static void mcux_lpadc_start_channel(const struct device *dev)
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{
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const struct mcux_lpadc_config *config = dev->config;
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struct mcux_lpadc_data *data = dev->data;
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data->channel_id = find_lsb_set(data->channels) - 1;
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LOG_DBG("Starting channel %d", data->channel_id);
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lpadc_conv_command_config_t cmd_config;
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LPADC_GetDefaultConvCommandConfig(&cmd_config);
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cmd_config.channelNumber = data->channel_id;
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#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) \
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&& FSL_FEATURE_LPADC_HAS_CMDL_MODE
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cmd_config.conversionResolutionMode = data->resolution;
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#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
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cmd_config.hardwareAverageMode = data->average;
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LPADC_SetConvCommandConfig(config->base, 1, &cmd_config);
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lpadc_conv_trigger_config_t trigger_config;
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LPADC_GetDefaultConvTriggerConfig(&trigger_config);
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trigger_config.targetCommandId = 1;
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/* configures trigger0. */
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LPADC_SetConvTriggerConfig(config->base, 0, &trigger_config);
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/* 1 is trigger0 mask. */
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LPADC_DoSoftwareTrigger(config->base, 1);
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct mcux_lpadc_data *data =
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CONTAINER_OF(ctx, struct mcux_lpadc_data, ctx);
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data->channels = ctx->sequence.channels;
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data->repeat_buffer = data->buffer;
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mcux_lpadc_start_channel(data->dev);
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx,
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bool repeat_sampling)
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{
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struct mcux_lpadc_data *data =
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CONTAINER_OF(ctx, struct mcux_lpadc_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->repeat_buffer;
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}
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}
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static void mcux_lpadc_isr(const struct device *dev)
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{
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const struct mcux_lpadc_config *config = dev->config;
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struct mcux_lpadc_data *data = dev->data;
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ADC_Type *base = config->base;
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lpadc_conv_result_t conv_result;
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#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) \
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&& (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
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LPADC_GetConvResult(base, &conv_result, 0U);
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#else
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LPADC_GetConvResult(base, &conv_result);
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#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
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/* For 12-bit resolution the MSB will be 0.
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So a 3 bit shift is also needed. */
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uint16_t result = data->ctx.sequence.resolution < 16 ?
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conv_result.convValue >> 3 : conv_result.convValue;
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LOG_DBG("Finished channel %d. Result is 0x%04x",
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data->channel_id, result);
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*data->buffer++ = result;
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data->channels &= ~BIT(data->channel_id);
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if (data->channels) {
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mcux_lpadc_start_channel(dev);
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} else {
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adc_context_on_sampling_done(&data->ctx, dev);
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}
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}
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static int mcux_lpadc_init(const struct device *dev)
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{
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const struct mcux_lpadc_config *config = dev->config;
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struct mcux_lpadc_data *data = dev->data;
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ADC_Type *base = config->base;
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lpadc_config_t adc_config;
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CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, config->clock_div, true);
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CLOCK_AttachClk(config->clock_source);
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/* Power up the ADC */
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POWER_DisablePD(kPDRUNCFG_PD_LDOGPADC);
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LPADC_GetDefaultConfig(&adc_config);
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adc_config.enableAnalogPreliminary = true;
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adc_config.referenceVoltageSource = config->voltage_ref;
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#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) \
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&& FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
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adc_config.conversionAverageMode = config->calibration_average;
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#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
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adc_config.powerLevelMode = config->power_level;
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LPADC_Init(base, &adc_config);
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/* Do ADC calibration. */
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#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) \
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&& FSL_FEATURE_LPADC_HAS_CTRL_CALOFS
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#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) \
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&& FSL_FEATURE_LPADC_HAS_OFSTRIM
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/* Request offset calibration. */
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#if defined(CONFIG_LPADC_DO_OFFSET_CALIBRATION) \
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&& CONFIG_LPADC_DO_OFFSET_CALIBRATION
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LPADC_DoOffsetCalibration(base);
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#else
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LPADC_SetOffsetValue(base,
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config->offset_a,
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config->offset_b);
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#endif /* DEMO_LPADC_DO_OFFSET_CALIBRATION */
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#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */
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/* Request gain calibration. */
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LPADC_DoAutoCalibration(base);
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#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */
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#if (defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) \
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&& FSL_FEATURE_LPADC_HAS_CFG_CALOFS)
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/* Do auto calibration. */
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LPADC_DoAutoCalibration(base);
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#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */
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/* Enable the watermark interrupt. */
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#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) \
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&& (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
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LPADC_EnableInterrupts(base, kLPADC_FIFO0WatermarkInterruptEnable);
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#else
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LPADC_EnableInterrupts(base, kLPADC_FIFOWatermarkInterruptEnable);
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#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
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config->irq_config_func(dev);
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data->dev = dev;
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static const struct adc_driver_api mcux_lpadc_driver_api = {
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.channel_setup = mcux_lpadc_channel_setup,
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.read = mcux_lpadc_read,
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#ifdef CONFIG_ADC_ASYNC
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.read_async = mcux_lpadc_read_async,
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#endif
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};
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#define ASSERT_LPADC_CLK_SOURCE_VALID(val, str) \
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BUILD_ASSERT(val == 0 || val == 1 || val == 2 || val == 7, str)
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#define ASSERT_LPADC_CLK_DIV_VALID(val, str) \
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BUILD_ASSERT(val == 1 || val == 2 || val == 4 || val == 8, str)
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#define ASSERT_LPADC_CALIBRATION_AVERAGE_VALID(val, str) \
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BUILD_ASSERT(val == 1 || val == 2 || val == 4 || val == 8 \
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|| val == 16 || val == 32 || val == 64 || val == 128, str) \
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#define ASSERT_WITHIN_RANGE(val, min, max, str) \
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BUILD_ASSERT(val >= min && val <= max, str)
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#define TO_LPADC_CLOCK_SOURCE(val) \
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MUX_A(CM_ADCASYNCCLKSEL, val)
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#define TO_LPADC_REFERENCE_VOLTAGE(val) \
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_DO_CONCAT(kLPADC_ReferenceVoltageAlt, val)
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#define TO_LPADC_CALIBRATION_AVERAGE(val) \
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_DO_CONCAT(kLPADC_ConversionAverage, val)
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#define TO_LPADC_POWER_LEVEL(val) \
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_DO_CONCAT(kLPADC_PowerLevelAlt, val)
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#define LPADC_MCUX_INIT(n) \
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static void mcux_lpadc_config_func_##n(const struct device *dev); \
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\
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ASSERT_LPADC_CLK_SOURCE_VALID(DT_INST_PROP(n, clk_source), \
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"Invalid clock source"); \
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ASSERT_LPADC_CLK_DIV_VALID(DT_INST_PROP(n, clk_divider), \
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"Invalid clock divider"); \
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ASSERT_WITHIN_RANGE(DT_INST_PROP(n, voltage_ref), 2, 3, \
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"Invalid voltage reference source"); \
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ASSERT_LPADC_CALIBRATION_AVERAGE_VALID( \
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DT_INST_PROP(n, calibration_average), \
|
||||
"Invalid converion average number for auto-calibration time"); \
|
||||
ASSERT_WITHIN_RANGE(DT_INST_PROP(n, power_level), 1, 4, \
|
||||
"Invalid power level"); \
|
||||
static const struct mcux_lpadc_config mcux_lpadc_config_##n = { \
|
||||
.base = (ADC_Type *)DT_INST_REG_ADDR(n), \
|
||||
.clock_source = TO_LPADC_CLOCK_SOURCE(DT_INST_PROP(n, clk_source)), \
|
||||
.clock_div = DT_INST_PROP(n, clk_divider), \
|
||||
.voltage_ref = \
|
||||
TO_LPADC_REFERENCE_VOLTAGE(DT_INST_PROP(n, voltage_ref)), \
|
||||
.calibration_average = \
|
||||
TO_LPADC_CALIBRATION_AVERAGE(DT_INST_PROP(n, calibration_average)), \
|
||||
.power_level = TO_LPADC_POWER_LEVEL(DT_INST_PROP(n, power_level)), \
|
||||
.offset_a = DT_INST_PROP(n, offset_value_a), \
|
||||
.offset_a = DT_INST_PROP(n, offset_value_b), \
|
||||
.irq_config_func = mcux_lpadc_config_func_##n, \
|
||||
}; \
|
||||
\
|
||||
static struct mcux_lpadc_data mcux_lpadc_data_##n = { \
|
||||
ADC_CONTEXT_INIT_TIMER(mcux_lpadc_data_##n, ctx), \
|
||||
ADC_CONTEXT_INIT_LOCK(mcux_lpadc_data_##n, ctx), \
|
||||
ADC_CONTEXT_INIT_SYNC(mcux_lpadc_data_##n, ctx), \
|
||||
}; \
|
||||
\
|
||||
DEVICE_AND_API_INIT(mcux_lpadc_##n, DT_INST_LABEL(n), \
|
||||
&mcux_lpadc_init, &mcux_lpadc_data_##n, \
|
||||
&mcux_lpadc_config_##n, POST_KERNEL, \
|
||||
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
|
||||
&mcux_lpadc_driver_api); \
|
||||
\
|
||||
static void mcux_lpadc_config_func_##n(const struct device *dev) \
|
||||
{ \
|
||||
IRQ_CONNECT(DT_INST_IRQN(n), \
|
||||
DT_INST_IRQ(n, priority), mcux_lpadc_isr, \
|
||||
DEVICE_GET(mcux_lpadc_##n), 0); \
|
||||
\
|
||||
irq_enable(DT_INST_IRQN(n)); \
|
||||
}
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(LPADC_MCUX_INIT)
|
|
@ -222,6 +222,22 @@
|
|||
clk-divider = <1>;
|
||||
label = "WWDT_0";
|
||||
};
|
||||
|
||||
adc0: adc@A0000 {
|
||||
compatible = "nxp,lpc-lpadc";
|
||||
reg = <0xA0000 0x580>;
|
||||
interrupts = <22 0>;
|
||||
status = "disabled";
|
||||
clk-divider = <8>;
|
||||
clk-source = <0>;
|
||||
voltage-ref= <2>;
|
||||
calibration-average = <128>;
|
||||
power-level = <1>;
|
||||
label = "ADC_0";
|
||||
offset-value-a = <10>;
|
||||
offset-value-b = <10>;
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
|
|
56
dts/bindings/iio/adc/nxp,lpc-lpadc.yaml
Normal file
56
dts/bindings/iio/adc/nxp,lpc-lpadc.yaml
Normal file
|
@ -0,0 +1,56 @@
|
|||
# Copyright (c) 2020, Toby Firth
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: LPC LPADC
|
||||
|
||||
compatible: "nxp,lpc-lpadc"
|
||||
|
||||
include: adc-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
clk-divider:
|
||||
type: int
|
||||
required: true
|
||||
description: clock divider for the converter
|
||||
|
||||
clk-source:
|
||||
type: int
|
||||
required: true
|
||||
description: source to attach the ADC clock to
|
||||
|
||||
voltage-ref:
|
||||
type: int
|
||||
required: true
|
||||
description: reference voltage source
|
||||
|
||||
calibration-average:
|
||||
type: int
|
||||
required: true
|
||||
description: conversion average number for auto-calibration
|
||||
|
||||
power-level:
|
||||
type: int
|
||||
required: true
|
||||
description: power level for the ADC
|
||||
|
||||
offset-value-a:
|
||||
type: int
|
||||
required: true
|
||||
description: Offset value A to use if CONFIG_LPADC_DO_OFFSET_CALIBRATION is false
|
||||
|
||||
offset-value-b:
|
||||
type: int
|
||||
required: true
|
||||
description: Offset value B to use if CONFIG_LPADC_DO_OFFSET_CALIBRATION is false
|
||||
|
||||
"#io-channel-cells":
|
||||
const: 1
|
||||
|
||||
io-channel-cells:
|
||||
- input
|
|
@ -20,6 +20,11 @@ config HAS_MCUX_ADC16
|
|||
help
|
||||
Set if the 16-bit ADC (ADC16) module is present in the SoC.
|
||||
|
||||
config HAS_MCUX_LPADC
|
||||
bool
|
||||
help
|
||||
Set if the LPADC module is present in the SoC.
|
||||
|
||||
config HAS_MCUX_CACHE
|
||||
bool
|
||||
help
|
||||
|
|
|
@ -28,4 +28,8 @@ config WDT_MCUX_WWDT
|
|||
default y
|
||||
depends on WATCHDOG
|
||||
|
||||
config ADC_MCUX_LPADC
|
||||
default y
|
||||
depends on ADC
|
||||
|
||||
endif # SOC_LPC55S69_CPU0
|
||||
|
|
|
@ -26,6 +26,7 @@ config SOC_LPC55S69_CPU0
|
|||
select ARMV8_M_DSP
|
||||
select ARM_TRUSTZONE_M
|
||||
select HAS_MCUX_IAP
|
||||
select HAS_MCUX_LPADC
|
||||
|
||||
config SOC_LPC55S69_CPU1
|
||||
bool "SOC_LPC55S69 M33 [CPU 1]"
|
||||
|
|
|
@ -219,6 +219,15 @@
|
|||
#define ADC_1ST_CHANNEL_ID 4
|
||||
#define ADC_2ND_CHANNEL_ID 5
|
||||
|
||||
#elif defined(CONFIG_BOARD_LPCXPRESSO55S69_CPU0)
|
||||
#define ADC_DEVICE_NAME DT_LABEL(DT_INST(0, nxp_lpc_lpadc))
|
||||
#define ADC_RESOLUTION 12
|
||||
#define ADC_GAIN ADC_GAIN_1
|
||||
#define ADC_REFERENCE ADC_REF_EXTERNAL0
|
||||
#define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT
|
||||
#define ADC_1ST_CHANNEL_ID 0
|
||||
#define ADC_2ND_CHANNEL_ID 1
|
||||
|
||||
#else
|
||||
#error "Unsupported board."
|
||||
#endif
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue