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drivers: adc: added support adc driver for lpcexpresso55s69

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Added shim driver for the LPADC for lpcexpresso55s69 board.

Fixes #22703.

Signed-off-by: Toby Firth <tobyjfirth@gmail.com>
This commit is contained in:
Toby Firth 2020-08-12 11:12:19 +01:00 • committed by Maureen Helm
commit dc37f988e0
14 changed files with 531 additions and 0 deletions
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2
boards/arm/lpcxpresso55s69/doc/index.rst
View file

@ -72,6 +72,8 @@ features:
+-----------+------------+-------------------------------------+
| TrustZone | on-chip | Trusted Firmware-M |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
The default configuration file
``boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0_defconfig``

4
boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.dts
View file

@ -80,3 +80,7 @@
&wwdt0 {
status = "okay";
};
&adc0 {
status = "okay";
};

1
boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.yaml
View file

@ -15,6 +15,7 @@ toolchain:
- gnuarmemb
- xtools
supported:
- adc
- arduino_i2c
- arduino_spi
- gpio

4
boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.dts
View file

@ -84,3 +84,7 @@
&wwdt0 {
status = "okay";
};
&adc0 {
status = "okay";
};

1
boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.yaml
View file

@ -15,6 +15,7 @@ toolchain:
- gnuarmemb
- xtools
supported:
- adc
- arduino_spi
- gpio
- spi

1
drivers/adc/CMakeLists.txt
View file

@ -6,6 +6,7 @@ zephyr_library_sources_ifdef(CONFIG_ADC adc_common.c)
zephyr_library_sources_ifdef(CONFIG_ADC_SHELL adc_shell.c)
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC12 adc_mcux_adc12.c)
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC16 adc_mcux_adc16.c)
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_LPADC adc_mcux_lpadc.c)
zephyr_library_sources_ifdef(CONFIG_ADC_SAM_AFEC adc_sam_afec.c)
zephyr_library_sources_ifdef(CONFIG_ADC_NRFX_ADC adc_nrfx_adc.c)
zephyr_library_sources_ifdef(CONFIG_ADC_NRFX_SAADC adc_nrfx_saadc.c)

16
drivers/adc/Kconfig.mcux
View file

@ -15,6 +15,12 @@ config ADC_MCUX_ADC16
help
Enable the MCUX ADC16 driver.
config ADC_MCUX_LPADC
bool "MCUX LPADC driver"
depends on HAS_MCUX_LPADC
help
Enable the MCUX LPADC driver.
if ADC_MCUX_ADC16
choice
@ -48,3 +54,13 @@ config ADC_MCUX_ADC16_VREF_ALTERNATE
endchoice
endif # ADC_MCUX_ADC16
if ADC_MCUX_LPADC
config LPADC_DO_OFFSET_CALIBRATION
bool "Do offset calibration"
help
Do offset calibration
endif # ADC_MCUX_LPADC

411
drivers/adc/adc_mcux_lpadc.c Normal file
View file

@ -0,0 +1,411 @@
/*
* Copyright (c) 2020 Toby Firth
*
* Based on adc_mcux_adc16.c and adc_mcux_adc12.c, which are:
* Copyright (c) 2017-2018, NXP
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_lpc_lpadc
#include <errno.h>
#include <drivers/adc.h>
#include <fsl_lpadc.h>
#include <fsl_power.h>
#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
#include <logging/log.h>
LOG_MODULE_REGISTER(nxp_mcux_lpadc);
#define ADC_CONTEXT_USES_KERNEL_TIMER
#include "adc_context.h"
struct mcux_lpadc_config {
ADC_Type *base;
uint32_t clock_div;
uint32_t clock_source;
lpadc_reference_voltage_source_t voltage_ref;
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS)\
&& FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
lpadc_conversion_average_mode_t calibration_average;
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
lpadc_power_level_mode_t power_level;
uint32_t offset_a;
uint32_t offset_b;
void (*irq_config_func)(const struct device *dev);
};
struct mcux_lpadc_data {
const struct device *dev;
struct adc_context ctx;
uint16_t *buffer;
uint16_t *repeat_buffer;
uint32_t channels;
uint8_t channel_id;
lpadc_hardware_average_mode_t average;
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) \
&& FSL_FEATURE_LPADC_HAS_CMDL_MODE
lpadc_conversion_resolution_mode_t resolution;
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
};
static int mcux_lpadc_channel_setup(const struct device *dev,
const struct adc_channel_cfg *channel_cfg)
{
uint8_t channel_id = channel_cfg->channel_id;
if (channel_id > 31) {
LOG_ERR("Channel %d is not valid", channel_id);
return -EINVAL;
}
if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
LOG_ERR("Invalid channel acquisition time");
return -EINVAL;
}
if (channel_cfg->differential) {
LOG_ERR("Differential channels are not supported");
return -EINVAL;
}
if (channel_cfg->gain != ADC_GAIN_1) {
LOG_ERR("Invalid channel gain");
return -EINVAL;
}
if (channel_cfg->reference != ADC_REF_EXTERNAL0) {
LOG_ERR("Invalid channel reference");
return -EINVAL;
}
return 0;
}
static int mcux_lpadc_start_read(const struct device *dev,
const struct adc_sequence *sequence)
{
struct mcux_lpadc_data *data = dev->data;
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) \
&& FSL_FEATURE_LPADC_HAS_CMDL_MODE
switch (sequence->resolution) {
case 12:
case 13:
data->resolution = kLPADC_ConversionResolutionStandard;
break;
case 16:
data->resolution = kLPADC_ConversionResolutionHigh;
break;
default:
LOG_ERR("Unsupported resolution %d", sequence->resolution);
return -ENOTSUP;
}
#else
/* If FSL_FEATURE_LPADC_HAS_CMDL_MODE is not defined
only 12/13 bit resolution is supported. */
if (sequence->resolution != 12 || sequence->resolution != 13) {
LOG_ERR("Unsupported resolution %d", sequence->resolution);
return -ENOTSUP;
}
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
switch (sequence->oversampling) {
case 0:
data->average = kLPADC_HardwareAverageCount1;
break;
case 1:
data->average = kLPADC_HardwareAverageCount2;
break;
case 2:
data->average = kLPADC_HardwareAverageCount4;
break;
case 3:
data->average = kLPADC_HardwareAverageCount8;
break;
case 4:
data->average = kLPADC_HardwareAverageCount16;
break;
case 5:
data->average = kLPADC_HardwareAverageCount32;
break;
case 6:
data->average = kLPADC_HardwareAverageCount64;
break;
case 7:
data->average = kLPADC_HardwareAverageCount128;
break;
default:
LOG_ERR("Unsupported oversampling value %d",
sequence->oversampling);
return -ENOTSUP;
}
data->buffer = sequence->buffer;
adc_context_start_read(&data->ctx, sequence);
int error = adc_context_wait_for_completion(&data->ctx);
return error;
}
static int mcux_lpadc_read_async(const struct device *dev,
const struct adc_sequence *sequence,
struct k_poll_signal *async)
{
struct mcux_lpadc_data *data = dev->data;
int error;
adc_context_lock(&data->ctx, async ? true : false, async);
error = mcux_lpadc_start_read(dev, sequence);
adc_context_release(&data->ctx, error);
return error;
}
static int mcux_lpadc_read(const struct device *dev,
const struct adc_sequence *sequence)
{
return mcux_lpadc_read_async(dev, sequence, NULL);
}
static void mcux_lpadc_start_channel(const struct device *dev)
{
const struct mcux_lpadc_config *config = dev->config;
struct mcux_lpadc_data *data = dev->data;
data->channel_id = find_lsb_set(data->channels) - 1;
LOG_DBG("Starting channel %d", data->channel_id);
lpadc_conv_command_config_t cmd_config;
LPADC_GetDefaultConvCommandConfig(&cmd_config);
cmd_config.channelNumber = data->channel_id;
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) \
&& FSL_FEATURE_LPADC_HAS_CMDL_MODE
cmd_config.conversionResolutionMode = data->resolution;
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
cmd_config.hardwareAverageMode = data->average;
LPADC_SetConvCommandConfig(config->base, 1, &cmd_config);
lpadc_conv_trigger_config_t trigger_config;
LPADC_GetDefaultConvTriggerConfig(&trigger_config);
trigger_config.targetCommandId = 1;
/* configures trigger0. */
LPADC_SetConvTriggerConfig(config->base, 0, &trigger_config);
/* 1 is trigger0 mask. */
LPADC_DoSoftwareTrigger(config->base, 1);
}
static void adc_context_start_sampling(struct adc_context *ctx)
{
struct mcux_lpadc_data *data =
CONTAINER_OF(ctx, struct mcux_lpadc_data, ctx);
data->channels = ctx->sequence.channels;
data->repeat_buffer = data->buffer;
mcux_lpadc_start_channel(data->dev);
}
static void adc_context_update_buffer_pointer(struct adc_context *ctx,
bool repeat_sampling)
{
struct mcux_lpadc_data *data =
CONTAINER_OF(ctx, struct mcux_lpadc_data, ctx);
if (repeat_sampling) {
data->buffer = data->repeat_buffer;
}
}
static void mcux_lpadc_isr(const struct device *dev)
{
const struct mcux_lpadc_config *config = dev->config;
struct mcux_lpadc_data *data = dev->data;
ADC_Type *base = config->base;
lpadc_conv_result_t conv_result;
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) \
&& (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
LPADC_GetConvResult(base, &conv_result, 0U);
#else
LPADC_GetConvResult(base, &conv_result);
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
/* For 12-bit resolution the MSB will be 0.
So a 3 bit shift is also needed. */
uint16_t result = data->ctx.sequence.resolution < 16 ?
conv_result.convValue >> 3 : conv_result.convValue;
LOG_DBG("Finished channel %d. Result is 0x%04x",
data->channel_id, result);
*data->buffer++ = result;
data->channels &= ~BIT(data->channel_id);
if (data->channels) {
mcux_lpadc_start_channel(dev);
} else {
adc_context_on_sampling_done(&data->ctx, dev);
}
}
static int mcux_lpadc_init(const struct device *dev)
{
const struct mcux_lpadc_config *config = dev->config;
struct mcux_lpadc_data *data = dev->data;
ADC_Type *base = config->base;
lpadc_config_t adc_config;
CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, config->clock_div, true);
CLOCK_AttachClk(config->clock_source);
/* Power up the ADC */
POWER_DisablePD(kPDRUNCFG_PD_LDOGPADC);
LPADC_GetDefaultConfig(&adc_config);
adc_config.enableAnalogPreliminary = true;
adc_config.referenceVoltageSource = config->voltage_ref;
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) \
&& FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
adc_config.conversionAverageMode = config->calibration_average;
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
adc_config.powerLevelMode = config->power_level;
LPADC_Init(base, &adc_config);
/* Do ADC calibration. */
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) \
&& FSL_FEATURE_LPADC_HAS_CTRL_CALOFS
#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) \
&& FSL_FEATURE_LPADC_HAS_OFSTRIM
/* Request offset calibration. */
#if defined(CONFIG_LPADC_DO_OFFSET_CALIBRATION) \
&& CONFIG_LPADC_DO_OFFSET_CALIBRATION
LPADC_DoOffsetCalibration(base);
#else
LPADC_SetOffsetValue(base,
config->offset_a,
config->offset_b);
#endif /* DEMO_LPADC_DO_OFFSET_CALIBRATION */
#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */
/* Request gain calibration. */
LPADC_DoAutoCalibration(base);
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */
#if (defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) \
&& FSL_FEATURE_LPADC_HAS_CFG_CALOFS)
/* Do auto calibration. */
LPADC_DoAutoCalibration(base);
#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */
/* Enable the watermark interrupt. */
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) \
&& (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
LPADC_EnableInterrupts(base, kLPADC_FIFO0WatermarkInterruptEnable);
#else
LPADC_EnableInterrupts(base, kLPADC_FIFOWatermarkInterruptEnable);
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
config->irq_config_func(dev);
data->dev = dev;
adc_context_unlock_unconditionally(&data->ctx);
return 0;
}
static const struct adc_driver_api mcux_lpadc_driver_api = {
.channel_setup = mcux_lpadc_channel_setup,
.read = mcux_lpadc_read,
#ifdef CONFIG_ADC_ASYNC
.read_async = mcux_lpadc_read_async,
#endif
};
#define ASSERT_LPADC_CLK_SOURCE_VALID(val, str) \
BUILD_ASSERT(val == 0 || val == 1 || val == 2 || val == 7, str)
#define ASSERT_LPADC_CLK_DIV_VALID(val, str) \
BUILD_ASSERT(val == 1 || val == 2 || val == 4 || val == 8, str)
#define ASSERT_LPADC_CALIBRATION_AVERAGE_VALID(val, str) \
BUILD_ASSERT(val == 1 || val == 2 || val == 4 || val == 8 \
|| val == 16 || val == 32 || val == 64 || val == 128, str) \
#define ASSERT_WITHIN_RANGE(val, min, max, str) \
BUILD_ASSERT(val >= min && val <= max, str)
#define TO_LPADC_CLOCK_SOURCE(val) \
MUX_A(CM_ADCASYNCCLKSEL, val)
#define TO_LPADC_REFERENCE_VOLTAGE(val) \
_DO_CONCAT(kLPADC_ReferenceVoltageAlt, val)
#define TO_LPADC_CALIBRATION_AVERAGE(val) \
_DO_CONCAT(kLPADC_ConversionAverage, val)
#define TO_LPADC_POWER_LEVEL(val) \
_DO_CONCAT(kLPADC_PowerLevelAlt, val)
#define LPADC_MCUX_INIT(n) \
static void mcux_lpadc_config_func_##n(const struct device *dev); \
\
ASSERT_LPADC_CLK_SOURCE_VALID(DT_INST_PROP(n, clk_source), \
"Invalid clock source"); \
ASSERT_LPADC_CLK_DIV_VALID(DT_INST_PROP(n, clk_divider), \
"Invalid clock divider"); \
ASSERT_WITHIN_RANGE(DT_INST_PROP(n, voltage_ref), 2, 3, \
"Invalid voltage reference source"); \
ASSERT_LPADC_CALIBRATION_AVERAGE_VALID( \
DT_INST_PROP(n, calibration_average), \
"Invalid converion average number for auto-calibration time"); \
ASSERT_WITHIN_RANGE(DT_INST_PROP(n, power_level), 1, 4, \
"Invalid power level"); \
static const struct mcux_lpadc_config mcux_lpadc_config_##n = { \
.base = (ADC_Type *)DT_INST_REG_ADDR(n), \
.clock_source = TO_LPADC_CLOCK_SOURCE(DT_INST_PROP(n, clk_source)), \
.clock_div = DT_INST_PROP(n, clk_divider), \
.voltage_ref = \
TO_LPADC_REFERENCE_VOLTAGE(DT_INST_PROP(n, voltage_ref)), \
.calibration_average = \
TO_LPADC_CALIBRATION_AVERAGE(DT_INST_PROP(n, calibration_average)), \
.power_level = TO_LPADC_POWER_LEVEL(DT_INST_PROP(n, power_level)), \
.offset_a = DT_INST_PROP(n, offset_value_a), \
.offset_a = DT_INST_PROP(n, offset_value_b), \
.irq_config_func = mcux_lpadc_config_func_##n, \
}; \
\
static struct mcux_lpadc_data mcux_lpadc_data_##n = { \
ADC_CONTEXT_INIT_TIMER(mcux_lpadc_data_##n, ctx), \
ADC_CONTEXT_INIT_LOCK(mcux_lpadc_data_##n, ctx), \
ADC_CONTEXT_INIT_SYNC(mcux_lpadc_data_##n, ctx), \
}; \
\
DEVICE_AND_API_INIT(mcux_lpadc_##n, DT_INST_LABEL(n), \
&mcux_lpadc_init, &mcux_lpadc_data_##n, \
&mcux_lpadc_config_##n, POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&mcux_lpadc_driver_api); \
\
static void mcux_lpadc_config_func_##n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), mcux_lpadc_isr, \
DEVICE_GET(mcux_lpadc_##n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
}
DT_INST_FOREACH_STATUS_OKAY(LPADC_MCUX_INIT)

16
dts/arm/nxp/nxp_lpc55S6x_common.dtsi
View file

@ -222,6 +222,22 @@
clk-divider = <1>;
label = "WWDT_0";
};
adc0: adc@A0000 {
compatible = "nxp,lpc-lpadc";
reg = <0xA0000 0x580>;
interrupts = <22 0>;
status = "disabled";
clk-divider = <8>;
clk-source = <0>;
voltage-ref= <2>;
calibration-average = <128>;
power-level = <1>;
label = "ADC_0";
offset-value-a = <10>;
offset-value-b = <10>;
#io-channel-cells = <1>;
};
};
&nvic {

56
dts/bindings/iio/adc/nxp,lpc-lpadc.yaml Normal file
View file

@ -0,0 +1,56 @@
# Copyright (c) 2020, Toby Firth
# SPDX-License-Identifier: Apache-2.0
description: LPC LPADC
compatible: "nxp,lpc-lpadc"
include: adc-controller.yaml
properties:
reg:
required: true
interrupts:
required: true
clk-divider:
type: int
required: true
description: clock divider for the converter
clk-source:
type: int
required: true
description: source to attach the ADC clock to
voltage-ref:
type: int
required: true
description: reference voltage source
calibration-average:
type: int
required: true
description: conversion average number for auto-calibration
power-level:
type: int
required: true
description: power level for the ADC
offset-value-a:
type: int
required: true
description: Offset value A to use if CONFIG_LPADC_DO_OFFSET_CALIBRATION is false
offset-value-b:
type: int
required: true
description: Offset value B to use if CONFIG_LPADC_DO_OFFSET_CALIBRATION is false
"#io-channel-cells":
const: 1
io-channel-cells:
- input

5
modules/Kconfig.mcux
View file

@ -20,6 +20,11 @@ config HAS_MCUX_ADC16
help
Set if the 16-bit ADC (ADC16) module is present in the SoC.
config HAS_MCUX_LPADC
bool
help
Set if the LPADC module is present in the SoC.
config HAS_MCUX_CACHE
bool
help

4
soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu0
View file

@ -28,4 +28,8 @@ config WDT_MCUX_WWDT
default y
depends on WATCHDOG
config ADC_MCUX_LPADC
default y
depends on ADC
endif # SOC_LPC55S69_CPU0

1
soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc
View file

@ -26,6 +26,7 @@ config SOC_LPC55S69_CPU0
select ARMV8_M_DSP
select ARM_TRUSTZONE_M
select HAS_MCUX_IAP
select HAS_MCUX_LPADC
config SOC_LPC55S69_CPU1
bool "SOC_LPC55S69 M33 [CPU 1]"

9
tests/drivers/adc/adc_api/src/test_adc.c
View file

@ -219,6 +219,15 @@
#define ADC_1ST_CHANNEL_ID 4
#define ADC_2ND_CHANNEL_ID 5
#elif defined(CONFIG_BOARD_LPCXPRESSO55S69_CPU0)
#define ADC_DEVICE_NAME DT_LABEL(DT_INST(0, nxp_lpc_lpadc))
#define ADC_RESOLUTION 12
#define ADC_GAIN ADC_GAIN_1
#define ADC_REFERENCE ADC_REF_EXTERNAL0
#define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT
#define ADC_1ST_CHANNEL_ID 0
#define ADC_2ND_CHANNEL_ID 1
#else
#error "Unsupported board."
#endif