soc: riscv: andes_v5: add custom CSR context switch support

Support custom RISC-V CSR context switch for Andes V5 CPUs.
Both AndeStar V5 DSP and PowerBrake features have it's own CSR to be
saved for thread and ISR context, so adding these CSRs into the RISC-V
SOC context management framework (CONFIG_RISCV_SOC_CONTEXT_SAVE).

Signed-off-by: Jim Shu <cwshu@andestech.com>
This commit is contained in:
Jim Shu 2021-07-29 12:16:10 +08:00 committed by Anas Nashif
commit 7db0fedcfe
6 changed files with 156 additions and 0 deletions

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@ -4,4 +4,10 @@ zephyr_include_directories(${CONFIG_SOC})
zephyr_sources(
start.S
soc_irq.S
)
# Note: AndeStar V5 DSP needs custom Andes V5 toolchain
if(CONFIG_SOC_ANDES_V5_HWDSP)
zephyr_cc_option(-mext-dsp)
endif()

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@ -17,6 +17,10 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config KERNEL_ENTRY
default "entry"
config RISCV_GENERIC_TOOLCHAIN
default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr"
default n
config RISCV_SOC_INTERRUPT_INIT
default y

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@ -47,4 +47,20 @@ config CACHE_ENABLE
bool "Enable cache"
default n
config SOC_ANDES_V5_HWDSP
bool "Enable AndeStar V5 DSP ISA"
select RISCV_SOC_CONTEXT_SAVE
depends on !RISCV_GENERIC_TOOLCHAIN
help
This option enables the AndeStar v5 hardware DSP, in order to
support using the DSP instructions.
config SOC_ANDES_V5_PFT
bool "Enable Andes V5 PowerBrake extension"
default y
select RISCV_SOC_CONTEXT_SAVE
help
The PowerBrake extension throttles performance by reducing instruction
executing rate.
endif # SOC_SERIES_RISCV_ANDES_V5

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@ -0,0 +1,44 @@
/*
* Copyright (c) 2021 Andes Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Extra definitions required for CONFIG_RISCV_SOC_CONTEXT_SAVE.
*/
#ifndef SOC_RISCV_ANDES_V5_SOC_CONTEXT_H_
#define SOC_RISCV_ANDES_V5_SOC_CONTEXT_H_
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/* Andes V5 specific registers. */
#if defined(CONFIG_SOC_ANDES_V5_PFT) && defined(CONFIG_SOC_ANDES_V5_HWDSP)
#define SOC_ESF_MEMBERS \
uint32_t mxstatus; \
uint32_t ucode \
#define SOC_ESF_INIT \
0, \
0
#elif defined(CONFIG_SOC_ANDES_V5_PFT)
#define SOC_ESF_MEMBERS \
uint32_t mxstatus
#define SOC_ESF_INIT \
0
#elif defined(CONFIG_SOC_ANDES_V5_HWDSP)
#define SOC_ESF_MEMBERS \
uint32_t ucode
#define SOC_ESF_INIT \
0
#endif
#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
#endif /* SOC_RISCV_ANDES_V5_SOC_CONTEXT_H_ */

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@ -0,0 +1,52 @@
/*
* Copyright (c) 2021 Andes Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <offsets.h>
#include <toolchain.h>
#include <soc.h>
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/* Exports */
GTEXT(__soc_save_context)
GTEXT(__soc_restore_context)
SECTION_FUNC(exception.other, __soc_save_context)
#ifdef CONFIG_SOC_ANDES_V5_PFT
csrr t0, NDS_MXSTATUS
#endif
#ifdef CONFIG_SOC_ANDES_V5_HWDSP
csrr t1, NDS_UCODE
#endif
#ifdef CONFIG_SOC_ANDES_V5_PFT
sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
#endif
#ifdef CONFIG_SOC_ANDES_V5_HWDSP
sw t1, __soc_esf_t_ucode_OFFSET(a0)
#endif
ret
SECTION_FUNC(exception.other, __soc_restore_context)
#ifdef CONFIG_SOC_ANDES_V5_PFT
lw t0, __soc_esf_t_mxstatus_OFFSET(a0)
#endif
#ifdef CONFIG_SOC_ANDES_V5_HWDSP
lw t1, __soc_esf_t_ucode_OFFSET(a0)
#endif
#ifdef CONFIG_SOC_ANDES_V5_PFT
csrw NDS_MXSTATUS, t0
#endif
#ifdef CONFIG_SOC_ANDES_V5_HWDSP
csrw NDS_UCODE, t1
#endif
ret
#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */

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@ -0,0 +1,34 @@
/*
* Copyright (c) 2021 Andes Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Extra definitions required for CONFIG_RISCV_SOC_OFFSETS.
*/
#ifndef SOC_RISCV_ANDES_V5_SOC_OFFSETS_H_
#define SOC_RISCV_ANDES_V5_SOC_OFFSETS_H_
#ifdef CONFIG_RISCV_SOC_OFFSETS
/* Andes V5 specific registers. */
#if defined(CONFIG_SOC_ANDES_V5_PFT) && defined(CONFIG_SOC_ANDES_V5_HWDSP)
#define GEN_SOC_OFFSET_SYMS() \
GEN_OFFSET_SYM(soc_esf_t, mxstatus); \
GEN_OFFSET_SYM(soc_esf_t, ucode)
#elif defined(CONFIG_SOC_ANDES_V5_PFT)
#define GEN_SOC_OFFSET_SYMS() \
GEN_OFFSET_SYM(soc_esf_t, mxstatus)
#elif defined(CONFIG_SOC_ANDES_V5_HWDSP)
#define GEN_SOC_OFFSET_SYMS() \
GEN_OFFSET_SYM(soc_esf_t, ucode)
#endif
#endif /* CONFIG_RISCV_SOC_OFFSETS */
#endif /* SOC_RISCV_ANDES_V5_SOC_OFFSETS_H_*/