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soc: arm: dts: arm: xilinx: Zynq-7000 SoC init code, device tree data

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Add SoC-specific code, the basic device tree and Kconfig data as well
as the corresponding linker command file for the Xilinx Zynq-7000
family of SoCs. This SoC - either as a QEMU simulation or on actual
hardware such as the Avnet/Digilent ZedBoard - is suitable as an ini-
tial target for the ARMv7 Cortex-A support.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
This commit is contained in:
Immo Birnbaum 2021-07-15 13:05:54 +02:00 • committed by Carles Cufí
commit f668474e4d
9 changed files with 327 additions and 0 deletions
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1
CODEOWNERS
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@ -433,6 +433,7 @@
/dts/riscv/starfive/ @rajnesh-kanwal
/dts/riscv/andes_v5* @cwshu @Teng-Shih-Wei
/dts/arm/armv*m.dtsi @galak @ioannisg
/dts/arm/armv7-a.dtsi @ibirnbaum
/dts/arm/armv7-r.dtsi @bbolen @stephanosio
/dts/arm/xilinx/ @bbolen @stephanosio
/dts/arm/renesas/ @julien-massot

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dts/arm/armv7-a.dtsi Normal file
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/*
* Copyright (c) 2018 Lexmark International, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "skeleton.dtsi"
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
};
};

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dts/arm/xilinx/zynq7000.dtsi Normal file
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/*
* Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <arm/armv7-a.dtsi>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/ethernet/xlnx_gem.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
};
soc {
interrupt-parent = <&gic>;
ocm_low: memory@1000 {
compatible = "xlnx,zynq-ocm";
reg = <0x00001000 DT_SIZE_K(188)>;
};
ocm_high: memory@fffc0000 {
compatible = "xlnx,zynq-ocm";
reg = <0xFFFC0000 DT_SIZE_K(256)>;
};
arch_timer: timer@f8f00200 {
compatible = "arm,armv8-timer";
status = "okay";
interrupt-names = "irq_0", "irq_1", "irq_2", "irq_3";
interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE
IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 14 IRQ_TYPE_EDGE
IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 11 IRQ_TYPE_EDGE
IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 10 IRQ_TYPE_EDGE
IRQ_DEFAULT_PRIORITY>;
reg = <0xf8f00200 0x1C>;
label = "arch_timer";
};
gic: interrupt-controller@f8f01000 {
compatible = "arm,gic";
status = "okay";
reg = <0xf8f01000 0x1000>,
<0xf8f00100 0x100>;
interrupt-controller;
#interrupt-cells = <4>;
label = "gic";
};
gem0: ethernet@e000b000 {
compatible = "xlnx,gem";
status = "disabled";
reg = <0xe000b000 0x1000>,
<0xf8000140 0x4>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 23 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>;
interrupt-names = "irq_0", "irq_1";
label = "gem0";
mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>;
phy-poll-interval = <1000>;
link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>;
amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>;
amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>;
hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>;
hw-rx-buffer-offset = <0>;
hw-tx-buffer-size-full;
rx-buffer-descriptors = <32>;
tx-buffer-descriptors = <32>;
rx-buffer-size = <512>;
tx-buffer-size = <512>;
discard-rx-fcs;
unicast-hash;
full-duplex;
};
gem1: ethernet@e000c000 {
compatible = "xlnx,gem";
status = "disabled";
reg = <0xe000c000 0x1000>,
<0xf8000144 0x4>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 46 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>;
interrupt-names = "irq_0", "irq_1";
label = "gem1";
mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>;
phy-poll-interval = <1000>;
link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>;
amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>;
amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>;
hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>;
hw-rx-buffer-offset = <0>;
hw-tx-buffer-size-full;
rx-buffer-descriptors = <32>;
tx-buffer-descriptors = <32>;
rx-buffer-size = <512>;
tx-buffer-size = <512>;
discard-rx-fcs;
unicast-hash;
full-duplex;
};
uart0: uart@e0000000 {
compatible = "xlnx,xuartps";
status = "disabled";
reg = <0xe0000000 0x4c>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>;
interrupt-names = "irq_0";
label = "uart0";
};
uart1: uart@e0001000 {
compatible = "xlnx,xuartps";
status = "disabled";
reg = <0xe0001000 0x4c>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>;
interrupt-names = "irq_0";
label = "uart1";
};
};
};

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soc/arm/xilinx_zynq7000/CMakeLists.txt Normal file
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#
# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
#
# SPDX-License-Identifier: Apache-2.0
#
zephyr_sources(
soc.c
)

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soc/arm/xilinx_zynq7000/Kconfig.defconfig Normal file
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#
# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
# SPDX-License-Identifier: Apache-2.0
#
if SOC_XILINX_ZYNQ7000 || SOC_XILINX_ZYNQ7000S
config SOC
default "xilinx_zynq7000"
config NUM_IRQS
int
# must be >= the highest interrupt number used
default 96
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_FLASH := zephyr,flash
config FLASH_SIZE
default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
config FLASH_BASE_ADDRESS
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
endif

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soc/arm/xilinx_zynq7000/Kconfig.soc Normal file
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#
# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
# SPDX-License-Identifier: Apache-2.0
#
config SOC_SERIES_XILINX_ZYNQ7000
bool "Xilinx Zynq-7000 Core Series"
select ARM
select CPU_CORTEX_A9
select GIC_V1
select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER
help
Enable support for the Xilinx Zynq-7000 SoC series.
choice
prompt "Xilinx Zynq-7000 Selection"
depends on SOC_SERIES_XILINX_ZYNQ7000
config SOC_XILINX_ZYNQ7000
bool "Xilinx Zynq-7000 dual-core (XC7Zxxx)"
config SOC_XILINX_ZYNQ7000S
bool "Xilinx Zynq-7000 single-core (XC7ZxxxS)"
endchoice

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soc/arm/xilinx_zynq7000/linker.ld Normal file
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/*
* Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arch/arm/aarch32/cortex_a_r/scripts/linker.ld>

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soc/arm/xilinx_zynq7000/soc.c Normal file
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/*
* Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
* SPDX-License-Identifier: Apache-2.0
*/
#include <device.h>
#include <devicetree.h>
#include <init.h>
#include <sys/util.h>
#include <arch/arm/aarch32/mmu/arm_mmu.h>
#include "soc.h"
static const struct arm_mmu_region mmu_regions[] = {
MMU_REGION_FLAT_ENTRY("vectors",
0x00000000,
0x1000,
MT_STRONGLY_ORDERED | MPERM_R | MPERM_X),
MMU_REGION_FLAT_ENTRY("slcr",
0xF8000000,
0x1000,
MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
MMU_REGION_FLAT_ENTRY("mpcore",
0xF8F00000,
0x2000,
MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
MMU_REGION_FLAT_ENTRY("ocm",
DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)),
DT_REG_SIZE(DT_CHOSEN(zephyr_ocm)),
MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
/* ARM Arch timer, GIC are covered by the MPCore mapping */
/* UARTs */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart0), okay)
MMU_REGION_FLAT_ENTRY("uart0",
DT_REG_ADDR(DT_NODELABEL(uart0)),
DT_REG_SIZE(DT_NODELABEL(uart0)),
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
MMU_REGION_FLAT_ENTRY("uart1",
DT_REG_ADDR(DT_NODELABEL(uart1)),
DT_REG_SIZE(DT_NODELABEL(uart1)),
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
#endif
/* GEMs */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gem0), okay)
MMU_REGION_FLAT_ENTRY("gem0",
DT_REG_ADDR(DT_NODELABEL(gem0)),
DT_REG_SIZE(DT_NODELABEL(gem0)),
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gem1), okay)
MMU_REGION_FLAT_ENTRY("gem1",
DT_REG_ADDR(DT_NODELABEL(gem1)),
DT_REG_SIZE(DT_NODELABEL(gem1)),
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
#endif
};
const struct arm_mmu_config mmu_config = {
.num_regions = ARRAY_SIZE(mmu_regions),
.mmu_regions = mmu_regions,
};
/**
* @brief Basic hardware initialization of the Zynq-7000 SoC
*
* Performs the basic initialization of the Zynq-7000 SoC.
*
* @return 0
*/
static int soc_xlnx_zynq7000_init(const struct device *arg)
{
ARG_UNUSED(arg);
NMI_INIT();
return 0;
}
SYS_INIT(soc_xlnx_zynq7000_init, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
/* EOF */

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soc/arm/xilinx_zynq7000/soc.h Normal file
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/*
* Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC__H_
#define _SOC__H_
#ifndef _ASMLANGUAGE
/*
* The following definitions are required for the inclusion of the CMSIS
* Common Peripheral Access Layer for aarch32 Cortex-A CPUs:
*/
#define __CORTEX_A 9U
#endif /* !_ASMLANGUAGE */
#endif /* _SOC__H_ */