ITE drivers/pwm: add PWM for it8xxx2
Add pulse width modulator (PWM) for it8xxx2. Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
This commit is contained in:
parent
ee3ccc9696
commit
d0ce9bb877
13 changed files with 601 additions and 45 deletions
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@ -275,6 +275,7 @@
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/drivers/pwm/pwm_capture.c @henrikbrixandersen
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/drivers/pwm/pwm_shell.c @henrikbrixandersen
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/drivers/pwm/*gecko* @sun681
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/drivers/pwm/*it8xxx2* @RuibinChang
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/drivers/sensor/ @MaureenHelm
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/drivers/sensor/ams_iAQcore/ @alexanderwachter
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/drivers/sensor/ens210/ @alexanderwachter
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@ -471,6 +472,7 @@
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/include/dt-bindings/dma/stm32_dma.h @cybertale
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/include/dt-bindings/ethernet/xlnx_gem.h @ibirnbaum
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/include/dt-bindings/pcie/ @dcpleung
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/include/dt-bindings/pwm/*it8xxx2* @RuibinChang
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/include/dt-bindings/usb/usb.h @galak
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/include/drivers/emul.h @sjg20
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/include/fs/ @nashif @nvlsianpu @de-nordic
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@ -11,6 +11,12 @@
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/ {
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model = "IT8XXX2 EV-Board";
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compatible = "riscv,it8xxx2-evb";
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aliases {
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pwm-led0 = &led0;
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pwm-led1 = &led1;
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};
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chosen {
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zephyr,console = &uart1;
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zephyr,shell-uart = &uart1;
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@ -20,6 +26,19 @@
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zephyr,flash-controller = &flashctrl;
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zephyr,code-partition = &slot0_partition;
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};
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pwmleds {
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compatible = "pwm-leds";
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/* NOTE: &pwm number needs same with channel number */
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led0: led_0 {
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pwms = <&pwm7 PWM_CHANNEL_7 PWM_POLARITY_INVERTED>;
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label = "LED0_GREEN";
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};
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led1: led_1 {
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pwms = <&pwm0 PWM_CHANNEL_0 PWM_POLARITY_NORMAL>;
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label = "LED1_BLUE";
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};
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};
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};
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&adc0 {
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status = "okay";
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@ -58,6 +77,20 @@
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current-speed = <460800>;
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clock-frequency = <1804800>;
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};
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&pwm0 {
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status = "okay";
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prescaler-cx = <PWM_PRESCALER_C6>;
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/*
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* If we need pwm output in ITE chip power saving mode,
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* then we should set frequency <=324Hz.
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*/
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pwm-output-frequency = <324>;
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};
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&pwm7 {
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status = "okay";
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prescaler-cx = <PWM_PRESCALER_C4>;
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pwm-output-frequency = <30000>;
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};
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&flash0 {
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partitions {
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compatible = "fixed-partitions";
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@ -32,3 +32,5 @@ CONFIG_I2C=y
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CONFIG_I2C_ITE_IT8XXX2=y
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CONFIG_ADC_ITE_IT8XXX2=y
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CONFIG_SOC_FLASH_ITE_IT8XXX2=y
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CONFIG_PWM=y
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CONFIG_PWM_ITE_IT8XXX2=y
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@ -8,6 +8,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_NRF5_SW pwm_nrf5_sw.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_NRFX pwm_nrfx.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MCUX_FTM pwm_mcux_ftm.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_IMX pwm_imx.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_ITE_IT8XXX2 pwm_ite_it8xxx2.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_LED_ESP32 pwm_led_esp32.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SAM pwm_sam.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MCUX pwm_mcux.c)
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@ -39,6 +39,8 @@ source "drivers/pwm/Kconfig.mcux_ftm"
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source "drivers/pwm/Kconfig.imx"
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source "drivers/pwm/Kconfig.it8xxx2"
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source "drivers/pwm/Kconfig.esp32"
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source "drivers/pwm/Kconfig.sam"
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12
drivers/pwm/Kconfig.it8xxx2
Normal file
12
drivers/pwm/Kconfig.it8xxx2
Normal file
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@ -0,0 +1,12 @@
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# IT8XXX2 PWM configuration options
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# Copyright (c) 2021 ITE Corporation. All Rights Reserved.
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# SPDX-License-Identifier: Apache-2.0
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config PWM_ITE_IT8XXX2
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bool "ITE IT8XXX2 embedded controller (EC) PWM driver"
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depends on SOC_IT8XXX2
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help
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Enable PWM driver for it8xxx2_evb.
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Supports three 16-bit prescalers each with 8-bit cycle timer, and
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eight PWM channels each with 8-bit duty cycle.
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265
drivers/pwm/pwm_ite_it8xxx2.c
Normal file
265
drivers/pwm/pwm_ite_it8xxx2.c
Normal file
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@ -0,0 +1,265 @@
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/*
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* Copyright (c) 2021 ITE Corporation. All Rights Reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ite_it8xxx2_pwm
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#include <device.h>
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#include <drivers/pwm.h>
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#include <drivers/pinmux.h>
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#include <dt-bindings/pwm/it8xxx2_pwm.h>
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#include <errno.h>
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#include <kernel.h>
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#include <soc.h>
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#include <stdlib.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pwm_ite_it8xxx2, CONFIG_PWM_LOG_LEVEL);
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#define PWM_CTRX_MIN 100
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#define PWM_EC_FREQ MHZ(8)
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#define PCSSG_MASK 0x3
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/* Device config */
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struct pwm_it8xxx2_cfg {
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/* PWM channel duty cycle register */
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uintptr_t reg_dcr;
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/* PWM channel clock source selection register */
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uintptr_t reg_pcssg;
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/* PWM channel clock source gating register */
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uintptr_t reg_pcsgr;
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/* PWM channel output polarity register */
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uintptr_t reg_pwmpol;
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/* PWM channel */
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int channel;
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/* PWM prescaler control register base */
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uintptr_t base;
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/* Select PWM prescaler that output to PWM channel */
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int prs_sel;
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/* Pinmux control device structure */
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const struct device *pinctrls;
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/* GPIO pin */
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uint8_t pin;
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/* Alternate function */
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uint8_t alt_fun;
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};
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/* Driver convenience defines */
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#define DRV_CONFIG(dev) ((const struct pwm_it8xxx2_cfg * const)(dev)->config)
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#define DRV_REG(dev) (struct pwm_it8xxx2_regs *)(DRV_CONFIG(dev)->base)
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#define DEV_PINMUX(inst) \
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DEVICE_DT_GET(DT_PHANDLE_BY_IDX(DT_NODELABEL(pinctrl_pwm##inst), pinctrls, 0))
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#define DEV_PIN(inst) \
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DT_PHA(DT_PHANDLE_BY_IDX(DT_DRV_INST(inst), pinctrl_0, 0), pinctrls, pin)
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#define DEV_ALT_FUN(inst) \
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DT_PHA(DT_PHANDLE_BY_IDX(DT_DRV_INST(inst), pinctrl_0, 0), pinctrls, alt_func)
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static void pwm_enable(const struct device *dev, int enabled)
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{
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const struct pwm_it8xxx2_cfg *config = DRV_CONFIG(dev);
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volatile uint8_t *reg_pcsgr = (uint8_t *)config->reg_pcsgr;
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int ch = config->channel;
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if (enabled)
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/* PWM channel clock source not gating */
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*reg_pcsgr &= ~BIT(ch);
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else
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/* PWM channel clock source gating */
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*reg_pcsgr |= BIT(ch);
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}
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static int pwm_it8xxx2_get_cycles_per_sec(const struct device *dev,
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uint32_t pwm, uint64_t *cycles)
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{
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const struct pwm_it8xxx2_cfg *config = DRV_CONFIG(dev);
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struct pwm_it8xxx2_regs *const inst = DRV_REG(dev);
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int prs_sel = config->prs_sel;
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ARG_UNUSED(pwm);
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/* Get clock source cycles per second that output to prescaler */
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if ((inst->PCFSR) & BIT(prs_sel))
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*cycles = (uint64_t) PWM_EC_FREQ;
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else
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*cycles = (uint64_t) 32768;
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return 0;
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}
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static int pwm_it8xxx2_pin_set(const struct device *dev,
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uint32_t pwm, uint32_t period_cycles,
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uint32_t pulse_cycles, pwm_flags_t flags)
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{
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const struct pwm_it8xxx2_cfg *config = DRV_CONFIG(dev);
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struct pwm_it8xxx2_regs *const inst = DRV_REG(dev);
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volatile uint8_t *reg_dcr = (uint8_t *)config->reg_dcr;
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volatile uint8_t *reg_pwmpol = (uint8_t *)config->reg_pwmpol;
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int ch = config->channel;
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int prs_sel = config->prs_sel;
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uint32_t actual_freq = 0xffffffff, target_freq, deviation, cxcprs, ctr;
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uint64_t pwm_clk_src;
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ARG_UNUSED(pwm);
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if (pulse_cycles > period_cycles)
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return -EINVAL;
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/* PWM channel clock source gating before configuring */
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pwm_enable(dev, 0);
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/* Select PWM inverted polarity (ex. active-low pulse) */
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if (flags & PWM_POLARITY_INVERTED)
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*reg_pwmpol |= BIT(ch);
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else
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*reg_pwmpol &= ~BIT(ch);
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/* If pulse cycles is 0, set duty cycle 0 and enable pwm channel */
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if (pulse_cycles == 0) {
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*reg_dcr = 0;
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pwm_enable(dev, 1);
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return 0;
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}
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pwm_it8xxx2_get_cycles_per_sec(dev, pwm, &pwm_clk_src);
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target_freq = ((uint32_t) pwm_clk_src) / period_cycles;
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deviation = (target_freq / 100) + 1;
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/*
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* Default clock source setting is 8MHz, when ITE chip is in power
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* saving mode, clock source 8MHz will be gated (32.768KHz won't).
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* So if we still need pwm output in mode, then we should set frequency
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* <=324Hz in board dts. Now change prescaler clock source from 8MHz to
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* 32.768KHz to support pwm output in mode.
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* NOTE: PWM output signal maximum supported frequency 324Hz comes from
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* 32768 / (PWM_CTRX_MIN + 1).
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*/
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if ((target_freq <= 324) && (inst->PCFSR & BIT(prs_sel))) {
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inst->PCFSR &= ~BIT(prs_sel);
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pwm_clk_src = (uint64_t) 32768;
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}
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/*
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* PWM output signal frequency is
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* pwm_clk_src / ((CxCPRS[15:0] + 1) * (CTRx[7:0] + 1))
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* NOTE: 1) define CTR minimum is 100 for more precisely when
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* calculate DCR
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* 2) CxCPRS[15:0] value 0001h results in a divisor 2
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* CxCPRS[15:0] value FFFFh results in a divisor 65536
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* CTRx[7:0] value 00h results in a divisor 1
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* CTRx[7:0] value FFh results in a divisor 256
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*/
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for (ctr = 0xFF; ctr >= PWM_CTRX_MIN; ctr--) {
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cxcprs = (((uint32_t) pwm_clk_src) / (ctr + 1) / target_freq) - 1;
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if (cxcprs >= 0) {
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actual_freq = ((uint32_t) pwm_clk_src) / (ctr + 1) / (cxcprs + 1);
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if (abs(actual_freq - target_freq) < deviation)
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break;
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}
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}
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if (cxcprs > UINT16_MAX) {
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LOG_ERR("PWM prescaler CxCPRS only support 2 bytes !");
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return -EINVAL;
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}
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/* Set PWM prescaler clock divide and cycle time register */
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if (prs_sel == PWM_PRESCALER_C4) {
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inst->C4CPRS = cxcprs & 0xFF;
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inst->C4MCPRS = (cxcprs >> 8) & 0xFF;
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inst->CTR1 = ctr;
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} else if (prs_sel == PWM_PRESCALER_C6) {
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inst->C6CPRS = cxcprs & 0xFF;
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inst->C6MCPRS = (cxcprs >> 8) & 0xFF;
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inst->CTR2 = ctr;
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} else if (prs_sel == PWM_PRESCALER_C7) {
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inst->C7CPRS = cxcprs & 0xFF;
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inst->C7MCPRS = (cxcprs >> 8) & 0xFF;
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inst->CTR3 = ctr;
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}
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/* Set PWM channel duty cycle register */
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*reg_dcr = (ctr * pulse_cycles) / period_cycles;
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/* PWM channel clock source not gating */
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pwm_enable(dev, 1);
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LOG_DBG("clock source freq %d, target freq %d",
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(uint32_t) pwm_clk_src, target_freq);
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return 0;
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}
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static int pwm_it8xxx2_init(const struct device *dev)
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{
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const struct pwm_it8xxx2_cfg *config = DRV_CONFIG(dev);
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struct pwm_it8xxx2_regs *const inst = DRV_REG(dev);
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volatile uint8_t *reg_pcssg = (uint8_t *)config->reg_pcssg;
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int ch = config->channel;
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int prs_sel = config->prs_sel;
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int pcssg_shift;
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int pcssg_mask;
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/* PWM channel clock source gating before configuring */
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pwm_enable(dev, 0);
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/* Select clock source 8MHz for prescaler */
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inst->PCFSR |= BIT(prs_sel);
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/* Bit shift and mask of prescaler clock source select group register */
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pcssg_shift = (ch % 4) * 2;
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pcssg_mask = (prs_sel & PCSSG_MASK) << pcssg_shift;
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/* Select which prescaler output to PWM channel */
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*reg_pcssg &= ~(PCSSG_MASK << pcssg_shift);
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*reg_pcssg |= pcssg_mask;
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/*
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* The cycle timer1 of it8320 later series was enhanced from
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* 8bits to 10bits resolution, and others are still 8bit resolution.
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* Because the cycle timer1 high byte default value is not zero,
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* we clear cycle timer1 high byte at init and use it as 8-bit
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* resolution like others.
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*/
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inst->CTR1M = 0;
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/* Enable PWMs clock counter */
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inst->ZTIER |= IT8XXX2_PWM_PCCE;
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/* Set alternate mode of PWM pin */
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pinmux_pin_set(config->pinctrls, config->pin, config->alt_fun);
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return 0;
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}
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static const struct pwm_driver_api pwm_it8xxx2_api = {
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.pin_set = pwm_it8xxx2_pin_set,
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.get_cycles_per_sec = pwm_it8xxx2_get_cycles_per_sec,
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};
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/* Device Instance */
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#define PWM_IT8XXX2_INIT(inst) \
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static const struct pwm_it8xxx2_cfg pwm_it8xxx2_cfg_##inst = { \
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.reg_dcr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
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.reg_pcssg = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
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.reg_pcsgr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
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.reg_pwmpol = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
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.channel = DT_PROP(DT_INST(inst, ite_it8xxx2_pwm), channel), \
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.base = DT_REG_ADDR(DT_NODELABEL(prs)), \
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.prs_sel = DT_PROP(DT_INST(inst, ite_it8xxx2_pwm), prescaler_cx), \
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.pinctrls = DEV_PINMUX(inst), \
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.pin = DEV_PIN(inst), \
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.alt_fun = DEV_ALT_FUN(inst), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, \
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&pwm_it8xxx2_init, \
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NULL, \
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NULL, \
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&pwm_it8xxx2_cfg_##inst, \
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PRE_KERNEL_1, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&pwm_it8xxx2_api);
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DT_INST_FOREACH_STATUS_OKAY(PWM_IT8XXX2_INIT)
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58
dts/bindings/pwm/ite,it8xxx2-pwm.yaml
Normal file
58
dts/bindings/pwm/ite,it8xxx2-pwm.yaml
Normal file
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# Copyright (c) 2021 ITE Corporation. All Rights Reserved.
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# SPDX-License-Identifier: Apache-2.0
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description: ITE, it8xxx2 Pulse Width Modulator (PWM) node
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compatible: "ite,it8xxx2-pwm"
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include: [pwm-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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label:
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required: true
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interrupts:
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required: false
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channel:
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type: int
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required: true
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enum:
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- 0 #PWM_CHANNEL_0
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- 1 #PWM_CHANNEL_1
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- 2 #PWM_CHANNEL_2
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- 3 #PWM_CHANNEL_3
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- 4 #PWM_CHANNEL_4
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- 5 #PWM_CHANNEL_5
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- 6 #PWM_CHANNEL_6
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- 7 #PWM_CHANNEL_7
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pwmctrl:
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type: phandle
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required: true
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description: PWM prescaler controller
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pinctrl-0:
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type: phandle
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required: true
|
||||
description: configuration of PWM pinmux controller
|
||||
|
||||
prescaler-cx:
|
||||
type: int
|
||||
required: true
|
||||
enum:
|
||||
- 1 #PWM_PRESCALER_C4
|
||||
- 2 #PWM_PRESCALER_C6
|
||||
- 3 #PWM_PRESCALER_C7
|
||||
|
||||
pwm-output-frequency:
|
||||
type: int
|
||||
required: false
|
||||
description: PWM output frequency for operation
|
||||
|
||||
pwm-cells:
|
||||
- channel
|
||||
- flags
|
18
dts/bindings/pwm/ite,it8xxx2-pwmprs.yaml
Normal file
18
dts/bindings/pwm/ite,it8xxx2-pwmprs.yaml
Normal file
|
@ -0,0 +1,18 @@
|
|||
# Copyright (c) 2021 ITE Corporation. All Rights Reserved.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: ITE, it8xxx2 PWM prescaler node
|
||||
|
||||
compatible: "ite,it8xxx2-pwmprs"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: false
|
|
@ -36,5 +36,30 @@
|
|||
pinctrls = <&pinmuxi 7 IT8XXX2_PINMUX_FUNC_1>;
|
||||
};
|
||||
|
||||
/* PWM alternate function */
|
||||
pinctrl_pwm0: pwm0 {
|
||||
pinctrls = <&pinmuxa 0 IT8XXX2_PINMUX_FUNC_1>;
|
||||
};
|
||||
pinctrl_pwm1: pwm1 {
|
||||
pinctrls = <&pinmuxa 1 IT8XXX2_PINMUX_FUNC_1>;
|
||||
};
|
||||
pinctrl_pwm2: pwm2 {
|
||||
pinctrls = <&pinmuxa 2 IT8XXX2_PINMUX_FUNC_1>;
|
||||
};
|
||||
pinctrl_pwm3: pwm3 {
|
||||
pinctrls = <&pinmuxa 3 IT8XXX2_PINMUX_FUNC_1>;
|
||||
};
|
||||
pinctrl_pwm4: pwm4 {
|
||||
pinctrls = <&pinmuxa 4 IT8XXX2_PINMUX_FUNC_1>;
|
||||
};
|
||||
pinctrl_pwm5: pwm5 {
|
||||
pinctrls = <&pinmuxa 5 IT8XXX2_PINMUX_FUNC_1>;
|
||||
};
|
||||
pinctrl_pwm6: pwm6 {
|
||||
pinctrls = <&pinmuxa 6 IT8XXX2_PINMUX_FUNC_1>;
|
||||
};
|
||||
pinctrl_pwm7: pwm7 {
|
||||
pinctrls = <&pinmuxa 7 IT8XXX2_PINMUX_FUNC_1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -9,6 +9,8 @@
|
|||
#include <dt-bindings/interrupt-controller/ite-intc.h>
|
||||
#include <dt-bindings/i2c/i2c.h>
|
||||
#include <dt-bindings/pinctrl/it8xxx2-pinctrl.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <dt-bindings/pwm/it8xxx2_pwm.h>
|
||||
#include "it8xxx2-alts-map.dtsi"
|
||||
|
||||
/ {
|
||||
|
@ -664,5 +666,114 @@
|
|||
reg-names = "ecpm";
|
||||
label = "EC_PM";
|
||||
};
|
||||
prs: pwmprs@f01800 {
|
||||
compatible = "ite,it8xxx2-pwmprs";
|
||||
reg = <0x00f01800 1>;
|
||||
label = "prescaler";
|
||||
};
|
||||
pwm0: pwm@f01802 {
|
||||
compatible = "ite,it8xxx2-pwm";
|
||||
reg = <0x00f01802 1 /* DCR */
|
||||
0x00f0180c 1 /* PCSSG */
|
||||
0x00f0180f 1 /* PCSG */
|
||||
0x00f0180a 1>; /* PWMPOL */
|
||||
channel = <PWM_CHANNEL_0>;
|
||||
label = "pwm_0";
|
||||
status = "disabled";
|
||||
pwmctrl = <&prs>;
|
||||
pinctrl-0 = <&pinctrl_pwm0>; /* GPA0 */
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
pwm1: pwm@f01803 {
|
||||
compatible = "ite,it8xxx2-pwm";
|
||||
reg = <0x00f01803 1 /* DCR */
|
||||
0x00f0180c 1 /* PCSSG */
|
||||
0x00f0180f 1 /* PCSG */
|
||||
0x00f0180a 1>; /* PWMPOL */
|
||||
channel = <PWM_CHANNEL_1>;
|
||||
label = "pwm_1";
|
||||
status = "disabled";
|
||||
pwmctrl = <&prs>;
|
||||
pinctrl-0 = <&pinctrl_pwm1>; /* GPA1 */
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
pwm2: pwm@f01804 {
|
||||
compatible = "ite,it8xxx2-pwm";
|
||||
reg = <0x00f01804 1 /* DCR */
|
||||
0x00f0180c 1 /* PCSSG */
|
||||
0x00f0180f 1 /* PCSG */
|
||||
0x00f0180a 1>; /* PWMPOL */
|
||||
channel = <PWM_CHANNEL_2>;
|
||||
label = "pwm_2";
|
||||
status = "disabled";
|
||||
pwmctrl = <&prs>;
|
||||
pinctrl-0 = <&pinctrl_pwm2>; /* GPA2 */
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
pwm3: pwm@f01805 {
|
||||
compatible = "ite,it8xxx2-pwm";
|
||||
reg = <0x00f01805 1 /* DCR */
|
||||
0x00f0180c 1 /* PCSSG */
|
||||
0x00f0180f 1 /* PCSG */
|
||||
0x00f0180a 1>; /* PWMPOL */
|
||||
channel = <PWM_CHANNEL_3>;
|
||||
label = "pwm_3";
|
||||
status = "disabled";
|
||||
pwmctrl = <&prs>;
|
||||
pinctrl-0 = <&pinctrl_pwm3>; /* GPA3 */
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
pwm4: pwm@f01806 {
|
||||
compatible = "ite,it8xxx2-pwm";
|
||||
reg = <0x00f01806 1 /* DCR */
|
||||
0x00f0180d 1 /* PCSSG */
|
||||
0x00f0180f 1 /* PCSG */
|
||||
0x00f0180a 1>; /* PWMPOL */
|
||||
channel = <PWM_CHANNEL_4>;
|
||||
label = "pwm_4";
|
||||
status = "disabled";
|
||||
pwmctrl = <&prs>;
|
||||
pinctrl-0 = <&pinctrl_pwm4>; /* GPA4 */
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
pwm5: pwm@f01807 {
|
||||
compatible = "ite,it8xxx2-pwm";
|
||||
reg = <0x00f01807 1 /* DCR */
|
||||
0x00f0180d 1 /* PCSSG */
|
||||
0x00f0180f 1 /* PCSG */
|
||||
0x00f0180a 1>; /* PWMPOL */
|
||||
channel = <PWM_CHANNEL_5>;
|
||||
label = "pwm_5";
|
||||
status = "disabled";
|
||||
pwmctrl = <&prs>;
|
||||
pinctrl-0 = <&pinctrl_pwm5>; /* GPA5 */
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
pwm6: pwm@f01808 {
|
||||
compatible = "ite,it8xxx2-pwm";
|
||||
reg = <0x00f01808 1 /* DCR */
|
||||
0x00f0180d 1 /* PCSSG */
|
||||
0x00f0180f 1 /* PCSG */
|
||||
0x00f0180a 1>; /* PWMPOL */
|
||||
channel = <PWM_CHANNEL_6>;
|
||||
label = "pwm_6";
|
||||
status = "disabled";
|
||||
pwmctrl = <&prs>;
|
||||
pinctrl-0 = <&pinctrl_pwm6>; /* GPA6 */
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
pwm7: pwm@f01809 {
|
||||
compatible = "ite,it8xxx2-pwm";
|
||||
reg = <0x00f01809 1 /* DCR */
|
||||
0x00f0180d 1 /* PCSSG */
|
||||
0x00f0180f 1 /* PCSG */
|
||||
0x00f0180a 1>; /* PWMPOL */
|
||||
channel = <PWM_CHANNEL_7>;
|
||||
label = "pwm_7";
|
||||
status = "disabled";
|
||||
pwmctrl = <&prs>;
|
||||
pinctrl-0 = <&pinctrl_pwm7>; /* GPA7 */
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
24
include/dt-bindings/pwm/it8xxx2_pwm.h
Normal file
24
include/dt-bindings/pwm/it8xxx2_pwm.h
Normal file
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Copyright (c) 2021 ITE Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_H_
|
||||
|
||||
/* PWM prescaler references */
|
||||
#define PWM_PRESCALER_C4 1
|
||||
#define PWM_PRESCALER_C6 2
|
||||
#define PWM_PRESCALER_C7 3
|
||||
|
||||
/* PWM channel references */
|
||||
#define PWM_CHANNEL_0 0
|
||||
#define PWM_CHANNEL_1 1
|
||||
#define PWM_CHANNEL_2 2
|
||||
#define PWM_CHANNEL_3 3
|
||||
#define PWM_CHANNEL_4 4
|
||||
#define PWM_CHANNEL_5 5
|
||||
#define PWM_CHANNEL_6 6
|
||||
#define PWM_CHANNEL_7 7
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_H_ */
|
|
@ -739,51 +739,54 @@
|
|||
* (18xxh) PWM & SmartAuto Fan Control (PWM)
|
||||
*
|
||||
*/
|
||||
#define C0CPRS ECREG(EC_REG_BASE_ADDR + 0x1800)
|
||||
#define CTR ECREG(EC_REG_BASE_ADDR + 0x1801)
|
||||
#define DCR0 ECREG(EC_REG_BASE_ADDR + 0x1802)
|
||||
#define DCR1 ECREG(EC_REG_BASE_ADDR + 0x1803)
|
||||
#define DCR2 ECREG(EC_REG_BASE_ADDR + 0x1804)
|
||||
#define DCR3 ECREG(EC_REG_BASE_ADDR + 0x1805)
|
||||
#define DCR4 ECREG(EC_REG_BASE_ADDR + 0x1806)
|
||||
#define DCR5 ECREG(EC_REG_BASE_ADDR + 0x1807)
|
||||
#define DCR6 ECREG(EC_REG_BASE_ADDR + 0x1808)
|
||||
#define DCR7 ECREG(EC_REG_BASE_ADDR + 0x1809)
|
||||
#define PWMPOL ECREG(EC_REG_BASE_ADDR + 0x180A)
|
||||
#define PCFSR ECREG(EC_REG_BASE_ADDR + 0x180B)
|
||||
#define PCSSGL ECREG(EC_REG_BASE_ADDR + 0x180C)
|
||||
#define PCSSGH ECREG(EC_REG_BASE_ADDR + 0x180D)
|
||||
#define CR256PCSSG ECREG(EC_REG_BASE_ADDR + 0x180E)
|
||||
#define PCSGR ECREG(EC_REG_BASE_ADDR + 0x180F)
|
||||
#define F1TLRR ECREG(EC_REG_BASE_ADDR + 0x181E)
|
||||
#define F1TMRR ECREG(EC_REG_BASE_ADDR + 0x181F)
|
||||
#define F2TLRR ECREG(EC_REG_BASE_ADDR + 0x1820)
|
||||
#define F2TMRR ECREG(EC_REG_BASE_ADDR + 0x1821)
|
||||
#define ZINTSCR ECREG(EC_REG_BASE_ADDR + 0x1822)
|
||||
#define ZTIER ECREG(EC_REG_BASE_ADDR + 0x1823)
|
||||
#define TSWCTLR ECREG(EC_REG_BASE_ADDR + 0x1824)
|
||||
#define C4CPRS ECREG(EC_REG_BASE_ADDR + 0x1827)
|
||||
#define C4MCPRS ECREG(EC_REG_BASE_ADDR + 0x1828)
|
||||
#define C6CPRS ECREG(EC_REG_BASE_ADDR + 0x182B)
|
||||
#define C6MCPRS ECREG(EC_REG_BASE_ADDR + 0x182C)
|
||||
#define C7CPRS ECREG(EC_REG_BASE_ADDR + 0x182D)
|
||||
#define C7MCPRS ECREG(EC_REG_BASE_ADDR + 0x182E)
|
||||
#define CLK6MSEL ECREG(EC_REG_BASE_ADDR + 0x1840)
|
||||
#define CTR1 ECREG(EC_REG_BASE_ADDR + 0x1841)
|
||||
#define CTR2 ECREG(EC_REG_BASE_ADDR + 0x1842)
|
||||
#define CTR3 ECREG(EC_REG_BASE_ADDR + 0x1843)
|
||||
#define PWM5TOCTRL ECREG(EC_REG_BASE_ADDR + 0x1844)
|
||||
#define CFLRR ECREG(EC_REG_BASE_ADDR + 0x1845)
|
||||
#define CFMRR ECREG(EC_REG_BASE_ADDR + 0x1846)
|
||||
#define CFINTCTRL ECREG(EC_REG_BASE_ADDR + 0x1847)
|
||||
#define TSWCTRL ECREG(EC_REG_BASE_ADDR + 0x1848)
|
||||
#define PWMODENR ECREG(EC_REG_BASE_ADDR + 0x1849)
|
||||
#define PWM0LHE ECREG(EC_REG_BASE_ADDR + 0x1850)
|
||||
#define PWM0LCR1 ECREG(EC_REG_BASE_ADDR + 0x1851)
|
||||
#define PWM0LCR2 ECREG(EC_REG_BASE_ADDR + 0x1852)
|
||||
#define PWM1LHE ECREG(EC_REG_BASE_ADDR + 0x1853)
|
||||
#define PWM1LCR1 ECREG(EC_REG_BASE_ADDR + 0x1854)
|
||||
#define PWM1LCR2 ECREG(EC_REG_BASE_ADDR + 0x1855)
|
||||
#ifndef __ASSEMBLER__
|
||||
struct pwm_it8xxx2_regs {
|
||||
/* 0x000: Channel0 Clock Prescaler */
|
||||
volatile uint8_t C0CPRS;
|
||||
/* 0x001: Cycle Time0 */
|
||||
volatile uint8_t CTR;
|
||||
/* 0x002~0x00A: Reserved1 */
|
||||
volatile uint8_t Reserved1[9];
|
||||
/* 0x00B: Prescaler Clock Frequency Select */
|
||||
volatile uint8_t PCFSR;
|
||||
/* 0x00C~0x00F: Reserved2 */
|
||||
volatile uint8_t Reserved2[4];
|
||||
/* 0x010: Cycle Time1 MSB */
|
||||
volatile uint8_t CTR1M;
|
||||
/* 0x011~0x022: Reserved3 */
|
||||
volatile uint8_t Reserved3[18];
|
||||
/* 0x023: PWM Clock Control */
|
||||
volatile uint8_t ZTIER;
|
||||
/* 0x024~0x026: Reserved4 */
|
||||
volatile uint8_t Reserved4[3];
|
||||
/* 0x027: Channel4 Clock Prescaler */
|
||||
volatile uint8_t C4CPRS;
|
||||
/* 0x028: Channel4 Clock Prescaler MSB */
|
||||
volatile uint8_t C4MCPRS;
|
||||
/* 0x029~0x02A: Reserved5 */
|
||||
volatile uint8_t Reserved5[2];
|
||||
/* 0x02B: Channel6 Clock Prescaler */
|
||||
volatile uint8_t C6CPRS;
|
||||
/* 0x02C: Channel6 Clock Prescaler MSB */
|
||||
volatile uint8_t C6MCPRS;
|
||||
/* 0x02D: Channel7 Clock Prescaler */
|
||||
volatile uint8_t C7CPRS;
|
||||
/* 0x02E: Channel7 Clock Prescaler MSB */
|
||||
volatile uint8_t C7MCPRS;
|
||||
/* 0x02F~0x040: Reserved6 */
|
||||
volatile uint8_t reserved6[18];
|
||||
/* 0x041: Cycle Time1 */
|
||||
volatile uint8_t CTR1;
|
||||
/* 0x042: Cycle Time2 */
|
||||
volatile uint8_t CTR2;
|
||||
/* 0x043: Cycle Time3 */
|
||||
volatile uint8_t CTR3;
|
||||
};
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
|
||||
/* PWM register fields */
|
||||
/* 0x023: PWM Clock Control */
|
||||
#define IT8XXX2_PWM_PCCE BIT(1)
|
||||
|
||||
/**
|
||||
*
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue