ipm: ipm_intel_adsp: Add INTEL ADSP IPM driver
Add IPM driver for Host-DSP communication channel. Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
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58b7c875ff
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4 changed files with 236 additions and 1 deletions
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@ -7,7 +7,7 @@ zephyr_library_sources_ifdef(CONFIG_IPM_IMX ipm_imx.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_MHU ipm_mhu.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_STM32_IPCC ipm_stm32_ipcc.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_NRFX ipm_nrfx_ipc.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_CAVS_IDC ipm_cavs_idc.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_INTEL_ADSP ipm_intel_adsp.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE ipm_handlers.c)
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@ -106,6 +106,11 @@ config IPM_CAVS_IDC
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Driver for the Intra-DSP Communication (IDC) channel for
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cross SoC communications.
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config IPM_INTEL_ADSP
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bool "IPM ADSP Host-DSP Communication driver"
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help
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Driver for the Host-DSP Mailbox Communication channel.
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module = IPM
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module-str = ipm
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source "subsys/logging/Kconfig.template.log_config"
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222
drivers/ipm/ipm_intel_adsp.c
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222
drivers/ipm/ipm_intel_adsp.c
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@ -0,0 +1,222 @@
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/*
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* Copyright (c) 2020, Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT intel_adsp_mailbox
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#include <device.h>
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#include <soc.h>
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#include <drivers/ipm.h>
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#include <platform/mailbox.h>
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#include <platform/shim.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(ipm_adsp, CONFIG_IPM_LOG_LEVEL);
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/*
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* With IPM data might be transferred by using ID field for simple
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* messages or via shared memory. Following parameters specify maximum
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* values for ID and DATA.
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*/
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#define IPM_INTEL_ADSP_MAX_DATA_SIZE 256
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#define IPM_INTEL_ADSP_MAX_ID_VAL IPC_DIPCI_MSG_MASK
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/* Mailbox ADSP -> Host */
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#define IPM_INTEL_ADSP_MAILBOX_OUT MAILBOX_DSPBOX_BASE
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#define IPM_INTEL_ADSP_MAILBOX_OUT_SIZE MAILBOX_DSPBOX_SIZE
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BUILD_ASSERT(IPM_INTEL_ADSP_MAILBOX_OUT_SIZE >= IPM_INTEL_ADSP_MAX_DATA_SIZE);
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/* Mailbox Host -> ADSP */
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#define IPM_INTEL_ADSP_MAILBOX_IN MAILBOX_HOSTBOX_BASE
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#define IPM_INTEL_ADSP_MAILBOX_IN_SIZE MAILBOX_HOSTBOX_SIZE
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BUILD_ASSERT(IPM_INTEL_ADSP_MAILBOX_IN_SIZE >= IPM_INTEL_ADSP_MAX_DATA_SIZE);
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struct ipm_adsp_config {
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void (*irq_config_func)(struct device *dev);
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};
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struct ipm_adsp_data {
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ipm_callback_t callback;
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void *user_data;
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};
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static void ipm_adsp_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct ipm_adsp_data *data = dev->data;
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uint32_t dipcctl, dipcie, dipct;
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dipct = ipc_read(IPC_DIPCT);
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dipcie = ipc_read(IPC_DIPCIE);
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dipcctl = ipc_read(IPC_DIPCCTL);
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LOG_DBG("dipct 0x%x dipcie 0x%x dipcctl 0x%x", dipct, dipcie, dipcctl);
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/*
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* DSP core has received a message from IPC initiator (HOST).
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* Initiator set Doorbel mechanism (HIPCI_BUSY bit).
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*/
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if (dipct & IPC_DIPCT_BUSY && dipcctl & IPC_DIPCCTL_IPCTBIE) {
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/* Mask BUSY interrupt */
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ipc_write(IPC_DIPCCTL, dipcctl & ~IPC_DIPCCTL_IPCTBIE);
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if (data->callback) {
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SOC_DCACHE_INVALIDATE((void *)IPM_INTEL_ADSP_MAILBOX_IN,
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IPM_INTEL_ADSP_MAILBOX_IN_SIZE);
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/* Use zero copy */
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data->callback(dev, data->user_data,
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dipct & IPC_DIPCI_MSG_MASK,
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(void *)IPM_INTEL_ADSP_MAILBOX_IN);
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}
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/*
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* Clear BUSY indicating to the Host that the message is
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* received, and DSP is ready to accept another message
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*/
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ipc_write(IPC_DIPCT, ipc_read(IPC_DIPCT) | IPC_DIPCT_BUSY);
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/* Unmask BUSY interrupts */
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ipc_write(IPC_DIPCCTL,
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ipc_read(IPC_DIPCCTL) | IPC_DIPCCTL_IPCTBIE);
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}
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/*
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* DSP Initiator DONE indicates that we got reply from HOST that message
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* is received and we can send another message.
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*/
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if (dipcie & IPC_DIPCIE_DONE && dipcctl & IPC_DIPCCTL_IPCIDIE) {
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/* Mask DONE interrupt */
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ipc_write(IPC_DIPCCTL,
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ipc_read(IPC_DIPCCTL) & ~IPC_DIPCCTL_IPCIDIE);
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/* Clear DONE bit, Notify HOST that operation is completed */
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ipc_write(IPC_DIPCIE,
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ipc_read(IPC_DIPCIE) | IPC_DIPCIE_DONE);
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/* Unmask DONE interrupt */
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ipc_write(IPC_DIPCCTL,
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ipc_read(IPC_DIPCCTL) | IPC_DIPCCTL_IPCIDIE);
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LOG_DBG("Not handled: IPC_DIPCCTL_IPCIDIE");
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/* TODO: implement queued message sending if needed */
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}
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}
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static int ipm_adsp_send(struct device *dev, int wait, uint32_t id,
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const void *data, int size)
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{
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LOG_DBG("Send: id %d data %p size %d", id, data, size);
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LOG_HEXDUMP_DBG(data, size, "send");
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if (id > IPM_INTEL_ADSP_MAX_ID_VAL) {
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return -EINVAL;
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}
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if (size > IPM_INTEL_ADSP_MAX_DATA_SIZE) {
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return -EMSGSIZE;
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}
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if (wait) {
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while (ipc_read(IPC_DIPCI) & IPC_DIPCI_BUSY) {
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}
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} else {
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if (ipc_read(IPC_DIPCI) & IPC_DIPCI_BUSY) {
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LOG_DBG("Busy: previous message is not handled");
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return -EBUSY;
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}
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}
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memcpy((void *)IPM_INTEL_ADSP_MAILBOX_OUT, data, size);
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SOC_DCACHE_FLUSH((void *)IPM_INTEL_ADSP_MAILBOX_OUT, size);
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ipc_write(IPC_DIPCIE, 0);
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ipc_write(IPC_DIPCI, IPC_DIPCI_BUSY | id);
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return 0;
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}
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static void ipm_adsp_register_callback(struct device *dev,
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ipm_callback_t cb,
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void *user_data)
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{
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struct ipm_adsp_data *data = dev->data;
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data->callback = cb;
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data->user_data = user_data;
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}
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static int ipm_adsp_max_data_size_get(struct device *dev)
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{
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ARG_UNUSED(dev);
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LOG_DBG("dev %p", dev);
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return IPM_INTEL_ADSP_MAX_DATA_SIZE;
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}
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static uint32_t ipm_adsp_max_id_val_get(struct device *dev)
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{
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ARG_UNUSED(dev);
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LOG_DBG("dev %p", dev);
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return IPM_INTEL_ADSP_MAX_ID_VAL;
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}
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static int ipm_adsp_set_enabled(struct device *dev, int enable)
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{
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LOG_DBG("dev %p", dev);
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/* enable IPC interrupts from host */
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ipc_write(IPC_DIPCCTL, IPC_DIPCCTL_IPCIDIE | IPC_DIPCCTL_IPCTBIE);
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return 0;
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}
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static int ipm_adsp_init(struct device *dev)
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{
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const struct ipm_adsp_config *config = dev->config;
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LOG_DBG("dev %p", dev);
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config->irq_config_func(dev);
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return 0;
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}
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static const struct ipm_driver_api ipm_adsp_driver_api = {
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.send = ipm_adsp_send,
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.register_callback = ipm_adsp_register_callback,
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.max_data_size_get = ipm_adsp_max_data_size_get,
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.max_id_val_get = ipm_adsp_max_id_val_get,
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.set_enabled = ipm_adsp_set_enabled,
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};
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static void ipm_adsp_config_func(struct device *dev);
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static const struct ipm_adsp_config ipm_adsp_config = {
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.irq_config_func = ipm_adsp_config_func,
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};
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static struct ipm_adsp_data ipm_adsp_data;
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DEVICE_AND_API_INIT(ipm_adsp, DT_INST_LABEL(0),
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&ipm_adsp_init,
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&ipm_adsp_data, &ipm_adsp_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&ipm_adsp_driver_api);
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static void ipm_adsp_config_func(struct device *dev)
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{
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IRQ_CONNECT(DT_INST_IRQN(0),
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DT_INST_IRQ(0, priority),
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ipm_adsp_isr, DEVICE_GET(ipm_adsp), 0);
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irq_enable(DT_INST_IRQN(0));
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}
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@ -78,6 +78,14 @@ static void prepare_host_windows(void)
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SOC_DCACHE_FLUSH((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
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HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
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if (IS_ENABLED(CONFIG_IPM_INTEL_ADSP)) {
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/* window1, for inbox/downlink mbox */
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sys_write32((HP_SRAM_WIN1_SIZE | 0x7), DMWLO(1));
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sys_write32((HP_SRAM_WIN1_BASE | DMWBA_ENABLE), DMWBA(1));
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memset((void *)HP_SRAM_WIN1_BASE, 0, HP_SRAM_WIN1_SIZE);
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SOC_DCACHE_FLUSH((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE);
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}
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/* window3, for trace
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* zeroed by trace initialization
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*/
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