soc: arm: st_stm32: add support for STM32 backup SRAM

Add support for backup SRAM initialization found in multiple STM32
microcontrollers. Linker script facilities are also provided to make it
easy to define variables in the backup SRAM.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>

dts/bindings/memory-controllers/st,stm32-backup-sram.yaml

@@ -0,0 +1,22 @@
+# Copyright (c) 2021, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32 Backup SRAM.
+
+  With a battery connected to the VBAT pin, the backup SRAM can be used to
+  retain data during low-power mode (Standby and VBAT mode).
+
+compatible: "st,stm32-backup-sram"
+
+include: base.yaml
+
+properties:
+  label:
+    required: true
+
+  reg:
+    required: true
+
+  clocks:
+    required: true

include/arch/arm/aarch32/cortex_m/scripts/linker.ld

@@ -131,6 +131,9 @@ MEMORY
 #if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram2), okay)
     SDRAM2                (rw) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram2)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram2))
 #endif
+#endif
+#ifdef CONFIG_STM32_BACKUP_SRAM
+    BACKUP_SRAM           (rw) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(backup_sram)), LENGTH = DT_REG_SIZE(DT_NODELABEL(backup_sram))
 #endif
     /* Used by and documented in include/linker/intlist.ld */
     IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K

include/linker/section_tags.h

@@ -33,6 +33,7 @@
 #define __imx_boot_dcd_section Z_GENERIC_SECTION(_IMX_BOOT_DCD_SECTION_NAME)
 #define __stm32_sdram1_section Z_GENERIC_SECTION(_STM32_SDRAM1_SECTION_NAME)
 #define __stm32_sdram2_section Z_GENERIC_SECTION(_STM32_SDRAM2_SECTION_NAME)
+#define __stm32_backup_sram_section Z_GENERIC_SECTION(_STM32_BACKUP_SRAM_SECTION_NAME)
 #endif /* CONFIG_ARM */
 
 #if defined(CONFIG_NOCACHE_MEMORY)

include/linker/sections.h

@@ -61,6 +61,8 @@
 #define _STM32_SDRAM1_SECTION_NAME	.stm32_sdram1
 #define _STM32_SDRAM2_SECTION_NAME	.stm32_sdram2
 
+#define _STM32_BACKUP_SRAM_SECTION_NAME	.stm32_backup_sram
+
 #ifdef CONFIG_NOCACHE_MEMORY
 #define _NOCACHE_SECTION_NAME nocache
 #endif

soc/arm/st_stm32/common/CMakeLists.txt

@@ -5,3 +5,6 @@ zephyr_include_directories(.)
 zephyr_sources(stm32cube_hal.c)
 
 zephyr_linker_sources_ifdef(CONFIG_STM32_CCM SECTIONS ccm.ld)
+
+zephyr_sources_ifdef(CONFIG_STM32_BACKUP_SRAM stm32_backup_sram.c)
+zephyr_linker_sources_ifdef(CONFIG_STM32_BACKUP_SRAM SECTIONS stm32_backup_sram.ld)

soc/arm/st_stm32/common/Kconfig.soc

@@ -8,3 +8,10 @@ DT_CHOSEN_Z_CCM := zephyr,ccm
 
 config STM32_CCM
 	def_bool $(dt_chosen_enabled,$(DT_CHOSEN_Z_CCM))
+
+config STM32_BACKUP_SRAM
+	bool "Enable STM32 Backup SRAM"
+	depends on SOC_SERIES_STM32F2X || SOC_SERIES_STM32F4X || \
+		   SOC_SERIES_STM32F7X || SOC_SERIES_STM32H7X
+	help
+	  Enable support for STM32 backup SRAM.

soc/arm/st_stm32/common/stm32_backup_sram.c

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2021 Teslabs Engineering S.L.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT st_stm32_backup_sram
+
+#include <device.h>
+#include <drivers/clock_control/stm32_clock_control.h>
+
+#include <stm32_ll_pwr.h>
+
+#include <logging/log.h>
+LOG_MODULE_REGISTER(stm32_backup_sram, CONFIG_SOC_LOG_LEVEL);
+
+struct stm32_backup_sram_config {
+	struct stm32_pclken pclken;
+};
+
+static int stm32_backup_sram_init(const struct device *dev)
+{
+	const struct stm32_backup_sram_config *config = dev->config;
+
+	int ret;
+	const struct device *clk;
+
+	/* enable backup SRAM clock */
+	clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
+	__ASSERT_NO_MSG(clk);
+
+	ret = clock_control_on(clk, (clock_control_subsys_t *)&config->pclken);
+	if (ret < 0) {
+		LOG_ERR("Could not initialize backup SRAM clock (%d)", ret);
+		return ret;
+	}
+
+	/* enable write access to backup domain */
+	LL_PWR_EnableBkUpAccess();
+	while (!LL_PWR_IsEnabledBkUpAccess()) {
+	}
+
+	/* enable backup sram regulator (required to retain backup SRAM content
+	 * while in standby or VBAT modes).
+	 */
+	LL_PWR_EnableBkUpRegulator();
+	while (!LL_PWR_IsEnabledBkUpRegulator()) {
+	}
+
+	return 0;
+}
+
+static const struct stm32_backup_sram_config config = {
+	.pclken = { .bus = DT_INST_CLOCKS_CELL(0, bus),
+		    .enr = DT_INST_CLOCKS_CELL(0, bits) },
+};
+
+DEVICE_DT_INST_DEFINE(0, stm32_backup_sram_init, device_pm_control_nop,
+		      NULL, &config, POST_KERNEL,
+		      CONFIG_APPLICATION_INIT_PRIORITY, NULL);

soc/arm/st_stm32/common/stm32_backup_sram.ld

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021 Teslabs Engineering S.L.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+GROUP_START(BACKUP_SRAM)
+
+	SECTION_PROLOGUE(_STM32_BACKUP_SRAM_SECTION_NAME, (NOLOAD),)
+	{
+		*(.stm32_backup_sram)
+		*(".stm32_backup_sram.*")
+	} GROUP_LINK_IN(BACKUP_SRAM)
+
+GROUP_END(BACKUP_SRAM)