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clock_control: esp32c3: added clock control

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gating driver support for esp32c3 SoC family

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
This commit is contained in:
Felipe Neves 2021-10-11 16:27:36 -03:00 • committed by Anas Nashif
commit 1e328fe109
7 changed files with 195 additions and 0 deletions
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1
drivers/clock_control/CMakeLists.txt
View file

@ -5,6 +5,7 @@ zephyr_library()
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BEETLE beetle_clock_control.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32 clock_control_esp32.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32S2 clock_control_esp32s2.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32C3 clock_control_esp32c3.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LITEX clock_control_litex.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LPC11U6X clock_control_lpc11u6x.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_XEC clock_control_mchp_xec.c)

2
drivers/clock_control/Kconfig
View file

@ -56,6 +56,8 @@ source "drivers/clock_control/Kconfig.esp32"
source "drivers/clock_control/Kconfig.esp32s2"
source "drivers/clock_control/Kconfig.esp32c3"
source "drivers/clock_control/Kconfig.litex"
source "drivers/clock_control/Kconfig.rcar"

10
drivers/clock_control/Kconfig.esp32c3 Normal file
View file

@ -0,0 +1,10 @@
# ESP32C3 Clock Driver configuration options
# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
# SPDX-License-Identifier: Apache-2.0
config CLOCK_CONTROL_ESP32C3
bool "ESP32C3 Clock driver"
depends on SOC_ESP32C3
help
Enable support for ESP32C3 clock driver.

109
drivers/clock_control/clock_control_esp32c3.c Normal file
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@ -0,0 +1,109 @@
/*
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT espressif_esp32_rtc
#include <dt-bindings/clock/esp32c3_clock.h>
#include <hal/clk_gate_ll.h>
#include <soc/soc_caps.h>
#include <soc/soc.h>
#include <soc/rtc.h>
#include <rtc_clk_common.h>
#include <soc.h>
#include <drivers/clock_control.h>
#include <driver/periph_ctrl.h>
static int clock_control_esp32_on(const struct device *dev,
clock_control_subsys_t sys)
{
ARG_UNUSED(dev);
periph_module_enable((periph_module_t)sys);
return 0;
}
static int clock_control_esp32_off(const struct device *dev,
clock_control_subsys_t sys)
{
ARG_UNUSED(dev);
periph_module_disable((periph_module_t)sys);
return 0;
}
static enum clock_control_status clock_control_esp32_get_status(const struct device *dev,
clock_control_subsys_t sys)
{
ARG_UNUSED(dev);
uint32_t clk_en_reg = periph_ll_get_clk_en_reg((periph_module_t)sys);
uint32_t clk_en_mask = periph_ll_get_clk_en_mask((periph_module_t)sys);
if (DPORT_GET_PERI_REG_MASK(clk_en_reg, clk_en_mask)) {
return CLOCK_CONTROL_STATUS_ON;
}
return CLOCK_CONTROL_STATUS_OFF;
}
static int clock_control_esp32_get_rate(const struct device *dev,
clock_control_subsys_t sub_system,
uint32_t *rate)
{
ARG_UNUSED(dev);
ARG_UNUSED(sub_system);
uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL);
uint32_t cpuperiod_sel;
uint32_t source_freq_mhz;
uint32_t clk_div;
switch (soc_clk_sel) {
case DPORT_SOC_CLK_SEL_XTAL:
clk_div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1;
source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get();
*rate = MHZ(source_freq_mhz / clk_div);
return 0;
case DPORT_SOC_CLK_SEL_PLL:
cpuperiod_sel = DPORT_REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL);
if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) {
*rate = MHZ(80);
} else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) {
*rate = MHZ(160);
} else {
*rate = 0;
return -ENOTSUP;
}
return 0;
case DPORT_SOC_CLK_SEL_8M:
*rate = MHZ(8);
return 0;
default:
*rate = 0;
return -ENOTSUP;
}
}
static int clock_control_esp32_init(const struct device *dev)
{
ARG_UNUSED(dev);
return 0;
}
static const struct clock_control_driver_api clock_control_esp32_api = {
.on = clock_control_esp32_on,
.off = clock_control_esp32_off,
.async_on = NULL,
.get_rate = clock_control_esp32_get_rate,
.get_status = clock_control_esp32_get_status,
};
DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
&clock_control_esp32_init,
NULL,
NULL,
NULL,
PRE_KERNEL_1,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
&clock_control_esp32_api);

11
dts/riscv/espressif/esp32c3.dtsi
View file

@ -6,6 +6,7 @@
#include <mem.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/esp-esp32c3-intmux.h>
#include <dt-bindings/clock/esp32c3_clock.h>
/ {
#address-cells = <1>;
@ -59,6 +60,16 @@
status = "okay";
};
rtc: rtc@60008000 {
compatible = "espressif,esp32-rtc";
reg = <0x60008000 0x1000>;
label = "RTC";
xtal-freq = <ESP32_CLK_XTAL_40M>;
xtal-div = <0>;
#clock-cells = <1>;
status = "ok";
};
gpio0: gpio@60004000 {
compatible = "espressif,esp32-gpio";
gpio-controller;

60
include/dt-bindings/clock/esp32c3_clock.h Normal file
View file

@ -0,0 +1,60 @@
/*
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_
/* System Clock Source */
#define ESP32_CLK_SRC_XTAL 0U
#define ESP32_CLK_SRC_PLL 1U
#define ESP32_CLK_SRC_RTC8M 2U
#define ESP32_CLK_SRC_APLL 3U
/* Supported CPU Frequencies */
#define ESP32_CLK_CPU_80M 80U
#define ESP32_CLK_CPU_160M 160U
/* Supported XTAL Frequencies */
#define ESP32_CLK_XTAL_40M 0U
/* Modules IDs
* These IDs are actually offsets in CLK and RST Control registers.
* These IDs shouldn't be changed unless there is a Hardware change
* from Espressif.
*
* Basic Modules
* Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG
*/
#define ESP32_LEDC_MODULE 0
#define ESP32_UART0_MODULE 1
#define ESP32_UART1_MODULE 2
#define ESP32_USB_MODULE 3
#define ESP32_I2C0_MODULE 4
#define ESP32_I2S1_MODULE 5
#define ESP32_TIMG0_MODULE 6
#define ESP32_TIMG1_MODULE 7
#define ESP32_UHCI0_MODULE 8
#define ESP32_RMT_MODULE 9
#define ESP32_SPI_MODULE 10
#define ESP32_SPI2_MODULE 11
#define ESP32_TWAI_MODULE 12
#define ESP32_RNG_MODULE 13
#define ESP32_WIFI_MODULE 14
#define ESP32_BT_MODULE 15
#define ESP32_WIFI_BT_COMMON_MODULE 16
#define ESP32_BT_BASEBAND_MODULE 17
#define ESP32_BT_LC_MODULE 18
#define ESP32_RSA_MODULE 19
#define ESP32_AES_MODULE 20
#define ESP32_SHA_MODULE 21
#define ESP32_HMAC_MODULE 22
#define ESP32_DS_MODULE 23
#define ESP32_GDMA_MODULE 24
#define ESP32_SYSTIMER_MODULE 25
#define ESP32_SARADC_MODULE 26
#define ESP32_MODULE_MAX 27
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_ */

2
soc/riscv/esp32c3/Kconfig.soc
View file

@ -6,6 +6,8 @@ config SOC_ESP32C3
select RISCV
select RISCV_GP
select DYNAMIC_INTERRUPTS
select CLOCK_CONTROL
select CLOCK_CONTROL_ESP32C3
config IDF_TARGET_ESP32C3
bool "ESP32C3 as target board"