clock_control: esp32c3: added clock control
gating driver support for esp32c3 SoC family Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
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421ecb77a3
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1e328fe109
7 changed files with 195 additions and 0 deletions
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@ -5,6 +5,7 @@ zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BEETLE beetle_clock_control.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32 clock_control_esp32.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32S2 clock_control_esp32s2.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32C3 clock_control_esp32c3.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LITEX clock_control_litex.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LPC11U6X clock_control_lpc11u6x.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_XEC clock_control_mchp_xec.c)
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@ -56,6 +56,8 @@ source "drivers/clock_control/Kconfig.esp32"
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source "drivers/clock_control/Kconfig.esp32s2"
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source "drivers/clock_control/Kconfig.esp32c3"
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source "drivers/clock_control/Kconfig.litex"
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source "drivers/clock_control/Kconfig.rcar"
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10
drivers/clock_control/Kconfig.esp32c3
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10
drivers/clock_control/Kconfig.esp32c3
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@ -0,0 +1,10 @@
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# ESP32C3 Clock Driver configuration options
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# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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config CLOCK_CONTROL_ESP32C3
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bool "ESP32C3 Clock driver"
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depends on SOC_ESP32C3
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help
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Enable support for ESP32C3 clock driver.
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109
drivers/clock_control/clock_control_esp32c3.c
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109
drivers/clock_control/clock_control_esp32c3.c
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@ -0,0 +1,109 @@
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/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT espressif_esp32_rtc
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#include <dt-bindings/clock/esp32c3_clock.h>
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#include <hal/clk_gate_ll.h>
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#include <soc/soc_caps.h>
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#include <soc/soc.h>
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#include <soc/rtc.h>
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#include <rtc_clk_common.h>
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#include <soc.h>
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#include <drivers/clock_control.h>
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#include <driver/periph_ctrl.h>
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static int clock_control_esp32_on(const struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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periph_module_enable((periph_module_t)sys);
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return 0;
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}
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static int clock_control_esp32_off(const struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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periph_module_disable((periph_module_t)sys);
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return 0;
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}
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static enum clock_control_status clock_control_esp32_get_status(const struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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uint32_t clk_en_reg = periph_ll_get_clk_en_reg((periph_module_t)sys);
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uint32_t clk_en_mask = periph_ll_get_clk_en_mask((periph_module_t)sys);
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if (DPORT_GET_PERI_REG_MASK(clk_en_reg, clk_en_mask)) {
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return CLOCK_CONTROL_STATUS_ON;
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}
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return CLOCK_CONTROL_STATUS_OFF;
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}
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static int clock_control_esp32_get_rate(const struct device *dev,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(sub_system);
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uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL);
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uint32_t cpuperiod_sel;
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uint32_t source_freq_mhz;
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uint32_t clk_div;
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switch (soc_clk_sel) {
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case DPORT_SOC_CLK_SEL_XTAL:
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clk_div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1;
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source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get();
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*rate = MHZ(source_freq_mhz / clk_div);
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return 0;
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case DPORT_SOC_CLK_SEL_PLL:
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cpuperiod_sel = DPORT_REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL);
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if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) {
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*rate = MHZ(80);
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} else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) {
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*rate = MHZ(160);
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} else {
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*rate = 0;
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return -ENOTSUP;
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}
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return 0;
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case DPORT_SOC_CLK_SEL_8M:
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*rate = MHZ(8);
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return 0;
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default:
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*rate = 0;
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return -ENOTSUP;
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}
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}
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static int clock_control_esp32_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return 0;
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}
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static const struct clock_control_driver_api clock_control_esp32_api = {
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.on = clock_control_esp32_on,
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.off = clock_control_esp32_off,
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.async_on = NULL,
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.get_rate = clock_control_esp32_get_rate,
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.get_status = clock_control_esp32_get_status,
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
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&clock_control_esp32_init,
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NULL,
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NULL,
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NULL,
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PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
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&clock_control_esp32_api);
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@ -6,6 +6,7 @@
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#include <mem.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/esp-esp32c3-intmux.h>
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#include <dt-bindings/clock/esp32c3_clock.h>
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/ {
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#address-cells = <1>;
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@ -59,6 +60,16 @@
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status = "okay";
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};
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rtc: rtc@60008000 {
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compatible = "espressif,esp32-rtc";
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reg = <0x60008000 0x1000>;
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label = "RTC";
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xtal-freq = <ESP32_CLK_XTAL_40M>;
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xtal-div = <0>;
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#clock-cells = <1>;
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status = "ok";
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};
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gpio0: gpio@60004000 {
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compatible = "espressif,esp32-gpio";
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gpio-controller;
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60
include/dt-bindings/clock/esp32c3_clock.h
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60
include/dt-bindings/clock/esp32c3_clock.h
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/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_
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/* System Clock Source */
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#define ESP32_CLK_SRC_XTAL 0U
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#define ESP32_CLK_SRC_PLL 1U
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#define ESP32_CLK_SRC_RTC8M 2U
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#define ESP32_CLK_SRC_APLL 3U
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/* Supported CPU Frequencies */
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#define ESP32_CLK_CPU_80M 80U
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#define ESP32_CLK_CPU_160M 160U
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/* Supported XTAL Frequencies */
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#define ESP32_CLK_XTAL_40M 0U
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/* Modules IDs
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* These IDs are actually offsets in CLK and RST Control registers.
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* These IDs shouldn't be changed unless there is a Hardware change
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* from Espressif.
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*
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* Basic Modules
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* Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG
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*/
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#define ESP32_LEDC_MODULE 0
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#define ESP32_UART0_MODULE 1
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#define ESP32_UART1_MODULE 2
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#define ESP32_USB_MODULE 3
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#define ESP32_I2C0_MODULE 4
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#define ESP32_I2S1_MODULE 5
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#define ESP32_TIMG0_MODULE 6
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#define ESP32_TIMG1_MODULE 7
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#define ESP32_UHCI0_MODULE 8
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#define ESP32_RMT_MODULE 9
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#define ESP32_SPI_MODULE 10
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#define ESP32_SPI2_MODULE 11
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#define ESP32_TWAI_MODULE 12
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#define ESP32_RNG_MODULE 13
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#define ESP32_WIFI_MODULE 14
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#define ESP32_BT_MODULE 15
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#define ESP32_WIFI_BT_COMMON_MODULE 16
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#define ESP32_BT_BASEBAND_MODULE 17
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#define ESP32_BT_LC_MODULE 18
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#define ESP32_RSA_MODULE 19
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#define ESP32_AES_MODULE 20
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#define ESP32_SHA_MODULE 21
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#define ESP32_HMAC_MODULE 22
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#define ESP32_DS_MODULE 23
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#define ESP32_GDMA_MODULE 24
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#define ESP32_SYSTIMER_MODULE 25
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#define ESP32_SARADC_MODULE 26
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#define ESP32_MODULE_MAX 27
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_ */
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@ -6,6 +6,8 @@ config SOC_ESP32C3
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select RISCV
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select RISCV_GP
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select DYNAMIC_INTERRUPTS
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select CLOCK_CONTROL
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select CLOCK_CONTROL_ESP32C3
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config IDF_TARGET_ESP32C3
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bool "ESP32C3 as target board"
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