drivers: ethernet: stm32: SRAM3 / MPU configuration
Fixes #29915. Implements the memory layout and MPU configuration for Ethernet buffers for STM32H7 controllers as recommended by ST. 16 KB of SRAM3 are are reserved for this. The first 256 B are for the RX/TX descriptors and configured as strongly ordered, shareable memory. The rest is for RX/TX buffers and configured as non cacheable memory. This configuration is automatically applied for H7 chips if the SRAM3 memory is enabled in the device tree. Signed-off-by: Mario Jaun <mario.jaun@gmail.com>
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c276088567
5 changed files with 67 additions and 13 deletions
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@ -67,24 +67,27 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
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#if defined(CONFIG_ETH_STM32_HAL_USE_DTCM_FOR_DMA_BUFFER) && \
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DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
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#define ETH_DMA_MEM __dtcm_noinit_section
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#define __eth_stm32_desc __dtcm_noinit_section
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#define __eth_stm32_buf __dtcm_noinit_section
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#elif defined(CONFIG_SOC_SERIES_STM32H7X) && \
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DT_NODE_HAS_STATUS(DT_NODELABEL(sram3), okay)
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#define __eth_stm32_desc __attribute__((section(".eth_stm32_desc")))
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#define __eth_stm32_buf __attribute__((section(".eth_stm32_buf")))
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#elif defined(CONFIG_NOCACHE_MEMORY)
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#define __eth_stm32_desc __nocache __aligned(4)
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#define __eth_stm32_buf __nocache __aligned(4)
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#else
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#define ETH_DMA_MEM __aligned(4)
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#endif /* CONFIG_ETH_STM32_HAL_USE_DTCM_FOR_DMA_BUFFER */
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#if defined(CONFIG_NOCACHE_MEMORY)
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#define CACHE __nocache
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#else
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#define CACHE
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#define __eth_stm32_desc __aligned(4)
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#define __eth_stm32_buf __aligned(4)
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#endif
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static ETH_DMADescTypeDef dma_rx_desc_tab[ETH_RXBUFNB] CACHE ETH_DMA_MEM;
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static ETH_DMADescTypeDef dma_tx_desc_tab[ETH_TXBUFNB] CACHE ETH_DMA_MEM;
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static uint8_t dma_rx_buffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE] CACHE ETH_DMA_MEM;
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static uint8_t dma_tx_buffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE] CACHE ETH_DMA_MEM;
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static ETH_DMADescTypeDef dma_rx_desc_tab[ETH_RXBUFNB] __eth_stm32_desc;
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static ETH_DMADescTypeDef dma_tx_desc_tab[ETH_TXBUFNB] __eth_stm32_desc;
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static uint8_t dma_rx_buffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __eth_stm32_buf;
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static uint8_t dma_tx_buffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __eth_stm32_buf;
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#if defined(CONFIG_SOC_SERIES_STM32H7X)
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static ETH_TxPacketConfig tx_config CACHE;
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static ETH_TxPacketConfig tx_config;
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#endif
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#if defined(CONFIG_NET_L2_CANBUS_ETH_TRANSLATOR)
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@ -4,3 +4,6 @@ zephyr_include_directories(${ZEPHYR_BASE}/drivers)
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zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M7 soc_m7.c)
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zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M4 soc_m4.c)
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zephyr_sources(mpu_regions.c)
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zephyr_linker_sources(SECTIONS sections.ld)
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@ -13,6 +13,7 @@ config SOC_SERIES_STM32H7X
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select CPU_HAS_ARM_MPU
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select HAS_SWO
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select USE_STM32_HAL_CORTEX
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select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
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help
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Enable support for STM32H7 MCU series
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29
soc/arm/st_stm32/stm32h7/mpu_regions.c
Normal file
29
soc/arm/st_stm32/stm32h7/mpu_regions.c
Normal file
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@ -0,0 +1,29 @@
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/*
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* Copyright (c) 2020 Mario Jaun
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <devicetree.h>
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#include "../../common/cortex_m/arm_mpu_mem_cfg.h"
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static const struct arm_mpu_region mpu_regions[] = {
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MPU_REGION_ENTRY("FLASH", CONFIG_FLASH_BASE_ADDRESS,
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REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
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MPU_REGION_ENTRY("SRAM", CONFIG_SRAM_BASE_ADDRESS,
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REGION_RAM_ATTR(REGION_SRAM_SIZE)),
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(sram3), okay) && \
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DT_NODE_HAS_STATUS(DT_NODELABEL(mac), okay)
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MPU_REGION_ENTRY("SRAM3_ETH_BUF",
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DT_REG_ADDR(DT_NODELABEL(sram3)),
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REGION_RAM_NOCACHE_ATTR(REGION_16K)),
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MPU_REGION_ENTRY("SRAM3_ETH_DESC",
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DT_REG_ADDR(DT_NODELABEL(sram3)),
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REGION_PPB_ATTR(REGION_256B)),
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#endif
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};
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const struct arm_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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};
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18
soc/arm/st_stm32/stm32h7/sections.ld
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18
soc/arm/st_stm32/stm32h7/sections.ld
Normal file
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@ -0,0 +1,18 @@
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/*
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* Copyright (c) 2020 Mario Jaun
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(sram3), okay) && DT_NODE_HAS_STATUS(DT_NODELABEL(mac), okay)
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SECTION_DATA_PROLOGUE(eth_stm32,(NOLOAD),)
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{
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. = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3)));
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*(.eth_stm32_desc)
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. = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3))) + 256;
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*(.eth_stm32_buf)
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. = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3))) + 16K;
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} GROUP_DATA_LINK_IN(SRAM3, SRAM3)
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#endif
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