boards: arm: Enable flash for storage on mimxrt595_evk
- The MX25UM51345G flash is connected to FLEXSPI PortA for mimxrt595_evk. - Updated flexspi_mx25um51345g driver to support DTR OPI mode. - Tested with tests/drivers/flash. Signed-off-by: Chay Guo <changyi.guo@nxp.com>
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c846537820
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a4c9e13ea8
12 changed files with 134 additions and 20 deletions
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@ -8,8 +8,18 @@ if BOARD_MIMXRT595_EVK
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config BOARD
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default "mimxrt595_evk_cm33"
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config FLASH_MCUX_FLEXSPI_MX25UM51345G
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default y if FLASH
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config FLASH_SIZE
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default $(dt_node_int_prop_int,/soc/spi@134000/mx25um51345g@2,size,K)
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default $(dt_node_int_prop_int,/soc/spi@134000/mx25um51345g@0,size,K)
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config FLASH_MCUX_FLEXSPI_XIP
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default y if FLASH
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depends on MEMC_MCUX_FLEXSPI
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choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
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default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM
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endchoice
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config FXOS8700_DRDY_INT1
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default y
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@ -85,6 +85,8 @@ features:
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+-----------+------------+-------------------------------------+
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| WDT | on-chip | watchdog |
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+-----------+------------+-------------------------------------+
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| FLASH | on-chip | OctalSPI Flash |
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+-----------+------------+-------------------------------------+
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The default configuration can be found in the defconfig file:
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@ -25,6 +25,9 @@
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};
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chosen {
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zephyr,flash-controller = &flexspi;
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zephyr,flash = &mx25um51345g;
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zephyr,code-partition = &slot0_partition;
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zephyr,sram = &sram0;
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zephyr,console = &flexcomm0;
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zephyr,shell-uart = &flexcomm0;
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@ -226,11 +229,11 @@ arduino_serial: &flexcomm12 {
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};
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&flexspi {
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mx25um51345g: mx25um51345g@2 {
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mx25um51345g: mx25um51345g@0 {
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compatible = "nxp,imx-flexspi-mx25um51345g";
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size = <DT_SIZE_M(64)>;
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label = "MX25UM51345G";
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reg = <2>;
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reg = <0>;
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spi-max-frequency = <200000000>;
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status = "okay";
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jedec-id = [c2 81 3a];
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@ -17,6 +17,10 @@ config SYSOSC_SETTLING_US
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config FLASH_MCUX_FLEXSPI_MX25UM51345G
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default y if FLASH
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choice FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_MODE
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default FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_STR
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endchoice
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config FLASH_SIZE
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default $(dt_node_int_prop_int,/soc/spi@134000/mx25um51345g@2,size,K)
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@ -52,6 +52,25 @@ config FLASH_MCUX_FLEXSPI_HYPERFLASH
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endmenu
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if FLASH_MCUX_FLEXSPI_MX25UM51345G
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choice FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_MODE
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prompt "FlexSPI MX25UM51345G OPI mode"
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default FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_DTR
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help
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Select the MX25UM51345G octal flash operation mode(Octal I/O STR
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or Octal I/O DTR).
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config FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_STR
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bool "STR"
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config FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_DTR
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bool "DTR"
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endchoice
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endif # FLASH_MCUX_FLEXSPI_MX25UM51345G
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config FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
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bool "MCUX FlexSPI NOR write RAM buffer"
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default y
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@ -36,6 +36,13 @@ static uint8_t nor_write_buf[SPI_NOR_PAGE_SIZE];
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read-while-write hazards. This configuration is not recommended."
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#endif
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/* FLASH_ENABLE_OCTAL_CMD: (01 = STR OPI Enable) , (02 = DTR OPI Enable) */
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#if CONFIG_FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_DTR
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#define NOR_FLASH_ENABLE_OCTAL_CMD 0x2
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#else
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#define NOR_FLASH_ENABLE_OCTAL_CMD 0x1
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#endif
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LOG_MODULE_REGISTER(flash_flexspi_nor, CONFIG_FLASH_LOG_LEVEL);
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enum {
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@ -71,6 +78,19 @@ static const uint32_t flash_flexspi_nor_lut[][4] = {
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
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},
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[WRITE_ENABLE] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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},
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[ENTER_OPI] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x72,
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kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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},
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#if (NOR_FLASH_ENABLE_OCTAL_CMD == 0x1)
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[READ_STATUS_REG] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x05,
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kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xFA),
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@ -79,12 +99,6 @@ static const uint32_t flash_flexspi_nor_lut[][4] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_8PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
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},
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[WRITE_ENABLE] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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},
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[WRITE_ENABLE_OPI] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x06,
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kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xF9),
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@ -117,14 +131,48 @@ static const uint32_t flash_flexspi_nor_lut[][4] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_8PAD, 0x04),
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},
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[ENTER_OPI] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x72,
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kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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#else
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[READ_STATUS_REG] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xFA),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x4),
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},
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[WRITE_ENABLE_OPI] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x06,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xF9),
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},
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[ERASE_SECTOR] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x21,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xDE),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0),
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},
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[ERASE_CHIP] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60,
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kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x9F),
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},
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[READ] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xEE,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x11),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x08),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
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},
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[PAGE_PROGRAM] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x12,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xED),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04),
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},
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#endif
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};
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static int flash_flexspi_nor_get_vendor_id(const struct device *dev,
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@ -294,8 +342,8 @@ static int flash_flexspi_nor_wait_bus_busy(const struct device *dev)
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static int flash_flexspi_enable_octal_mode(const struct device *dev)
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{
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struct flash_flexspi_nor_data *data = dev->data;
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/* FLASH_ENABLE_OCTAL_CMD: (01 = STR OPI Enable) */
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uint32_t status = 0x01;
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/* FLASH_ENABLE_OCTAL_CMD: (01 = STR OPI Enable, 02 = DTR OPI Enable) */
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uint32_t status = NOR_FLASH_ENABLE_OCTAL_CMD;
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flash_flexspi_nor_write_enable(dev, false);
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flash_flexspi_nor_write_status(dev, &status);
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@ -178,7 +178,7 @@ static int memc_flexspi_init(const struct device *dev)
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#define MEMC_FLEXSPI_CFG_XIP(node_id) DT_SAME_NODE(node_id, DT_NODELABEL(flexspi))
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#elif defined(CONFIG_XIP) && defined(CONFIG_CODE_FLEXSPI2)
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#define MEMC_FLEXSPI_CFG_XIP(node_id) DT_SAME_NODE(node_id, DT_NODELABEL(flexspi2))
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#elif defined(CONFIG_SOC_SERIES_IMX_RT6XX)
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#elif defined(CONFIG_SOC_SERIES_IMX_RT6XX) || defined(CONFIG_SOC_SERIES_IMX_RT5XX)
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#define MEMC_FLEXSPI_CFG_XIP(node_id) IS_ENABLED(CONFIG_XIP)
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#else
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#define MEMC_FLEXSPI_CFG_XIP(node_id) false
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@ -17,7 +17,7 @@
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};
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flexspi: spi@134000 {
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reg = <0x5134000 0x1000>, <0x18000000 DT_SIZE_M(64)>;
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reg = <0x50134000 0x1000>, <0x18000000 DT_SIZE_M(64)>;
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};
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};
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};
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@ -25,6 +25,19 @@ config ZTEST_NO_YIELD
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config FLASH_BASE_ADDRESS
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default $(dt_node_reg_addr_hex,/soc/spi@134000,1)
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if FLASH_MCUX_FLEXSPI_XIP
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# Avoid RWW hazards by defaulting logging to disabled
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choice FLASH_LOG_LEVEL_CHOICE
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default FLASH_LOG_LEVEL_OFF
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endchoice
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choice MEMC_LOG_LEVEL_CHOICE
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default MEMC_LOG_LEVEL_OFF
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endchoice
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endif
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#
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# MBEDTLS is larger but much faster than TinyCrypt so choose wisely
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#
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@ -77,6 +77,15 @@ menuconfig NXP_IMX_RT5XX_BOOT_HEADER
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if NXP_IMX_RT5XX_BOOT_HEADER
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choice BOOT_DEVICE
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prompt "Boot device selection"
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default BOOT_FLEXSPI_NOR
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config BOOT_FLEXSPI_NOR
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bool "FlexSPI serial NOR"
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endchoice
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config FLASH_CONFIG_OFFSET
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hex "Flash config data offset"
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default 0x400
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6
tests/drivers/flash/boards/mimxrt595_evk_cm33.conf
Normal file
6
tests/drivers/flash/boards/mimxrt595_evk_cm33.conf
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#
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# Copyright (c) 2022 NXP.
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# SPDX-License-Identifier: Apache-2.0
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#
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CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER=y
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@ -27,7 +27,7 @@ tests:
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integration_platforms:
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- nrf52840dk_nrf52840
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drivers.flash.default:
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platform_allow: mimxrt1060_evk it8xxx2_evb mimxrt685_evk_cm33
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platform_allow: mimxrt1060_evk it8xxx2_evb mimxrt685_evk_cm33 mimxrt595_evk_cm33
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tags: mcux
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integration_platforms:
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- mimxrt1060_evk
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