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soc: rt11xx: Enable ethernet clocks

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Enable clocks for ethernet module.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-01-10 15:29:01 -06:00 • committed by Anas Nashif
commit b3a148b22f
2 changed files with 22 additions and 1 deletions
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4
soc/arm/nxp_imx/rt/Kconfig.soc
View file

@ -294,6 +294,7 @@ config SOC_MIMXRT1176_CM7
select HAS_MCUX_PWM
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_ENET
config SOC_MIMXRT1176_CM4
bool "SOC_MIMXRT1176_CM4"
@ -317,6 +318,7 @@ config SOC_MIMXRT1176_CM4
select HAS_MCUX_PWM
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_ENET
config SOC_MIMXRT1166_CM7
bool "SOC_MIMXRT1166_CM7"
@ -347,6 +349,7 @@ config SOC_MIMXRT1166_CM7
select HAS_MCUX_PWM
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_ENET
config SOC_MIMXRT1166_CM4
@ -371,6 +374,7 @@ config SOC_MIMXRT1166_CM4
select HAS_MCUX_PWM
select HAS_MCUX_USDHC1
select HAS_MCUX_USDHC2
select HAS_MCUX_ENET
endchoice

19
soc/arm/nxp_imx/rt/soc_rt11xx.c
View file

@ -247,7 +247,11 @@ static ALWAYS_INLINE void clock_init(void)
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
/* Init System Pll2 pfd3. */
#ifdef CONFIG_ETH_MCUX
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 24);
#else
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
#endif
/* Init Sys Pll3. */
CLOCK_InitSysPll3();
@ -290,7 +294,13 @@ static ALWAYS_INLINE void clock_init(void)
#endif
/* Configure BUS using SYS_PLL3_CLK */
#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7)
#ifdef CONFIG_ETH_MCUX
/* Configure root bus clock at 198M */
rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3;
rootCfg.div = 2;
CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
#elif defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7)
/* Keep root bus clock at default 240M */
rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out;
rootCfg.div = 2;
CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
@ -355,6 +365,13 @@ static ALWAYS_INLINE void clock_init(void)
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
#endif
#ifdef CONFIG_ETH_MCUX
rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2;
rootCfg.div = 10;
CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
#endif
#ifdef CONFIG_SPI_MCUX_LPSPI
/* Configure lpspi using Osc48MDiv2 */
rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;