soc: rt11xx: Enable ethernet clocks
Enable clocks for ethernet module. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
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2 changed files with 22 additions and 1 deletions
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@ -294,6 +294,7 @@ config SOC_MIMXRT1176_CM7
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select HAS_MCUX_PWM
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select HAS_MCUX_USDHC1
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select HAS_MCUX_USDHC2
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select HAS_MCUX_ENET
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config SOC_MIMXRT1176_CM4
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bool "SOC_MIMXRT1176_CM4"
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@ -317,6 +318,7 @@ config SOC_MIMXRT1176_CM4
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select HAS_MCUX_PWM
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select HAS_MCUX_USDHC1
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select HAS_MCUX_USDHC2
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select HAS_MCUX_ENET
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config SOC_MIMXRT1166_CM7
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bool "SOC_MIMXRT1166_CM7"
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@ -347,6 +349,7 @@ config SOC_MIMXRT1166_CM7
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select HAS_MCUX_PWM
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select HAS_MCUX_USDHC1
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select HAS_MCUX_USDHC2
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select HAS_MCUX_ENET
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config SOC_MIMXRT1166_CM4
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@ -371,6 +374,7 @@ config SOC_MIMXRT1166_CM4
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select HAS_MCUX_PWM
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select HAS_MCUX_USDHC1
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select HAS_MCUX_USDHC2
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select HAS_MCUX_ENET
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endchoice
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@ -247,7 +247,11 @@ static ALWAYS_INLINE void clock_init(void)
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CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
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/* Init System Pll2 pfd3. */
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#ifdef CONFIG_ETH_MCUX
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CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 24);
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#else
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CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
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#endif
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/* Init Sys Pll3. */
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CLOCK_InitSysPll3();
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@ -290,7 +294,13 @@ static ALWAYS_INLINE void clock_init(void)
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#endif
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/* Configure BUS using SYS_PLL3_CLK */
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#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7)
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#ifdef CONFIG_ETH_MCUX
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/* Configure root bus clock at 198M */
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rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3;
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rootCfg.div = 2;
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CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
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#elif defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7)
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/* Keep root bus clock at default 240M */
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rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out;
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rootCfg.div = 2;
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CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
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@ -355,6 +365,13 @@ static ALWAYS_INLINE void clock_init(void)
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CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
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#endif
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#ifdef CONFIG_ETH_MCUX
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rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2;
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rootCfg.div = 10;
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CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
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#endif
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#ifdef CONFIG_SPI_MCUX_LPSPI
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/* Configure lpspi using Osc48MDiv2 */
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rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
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