soc: npcx: Move ecst to npcx common folder

NPCX series ROM code changes the chip basic setting by firmware binary
header for loading the firmware from flash to RAM. Add the following to
improve the ec firmware header setting:

- Move the ECST which generates the firmware binary header to NPCX
common folder. All the following NPCX series chips can use this.
- Add ecst setting option in Kconfig.

Signed-off-by: Yuval Peress <peress@chromium.org>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>

boards/arm/npcx7m6fb_evb/CMakeLists.txt

@@ -1,14 +0,0 @@
-#
-# Copyright (c) 2020 Nuvoton Technology Corporation.
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-
-# find ECST tool for generating npcx header used by ROM code
-
-set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-  COMMAND ${PYTHON_EXECUTABLE} ${BOARD_DIR}/support/ecst.py
-  -i ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin
-  -o ${TARGET_IMAGE_FILE} -nohcrc -nofcrc
-  -chip npcx7m6 -flashsize 8 -spimaxclk 50 -spireadmode dual
-)

boards/arm/npcx7m6fb_evb/board.cmake

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-set(TARGET_IMAGE_FILE  ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}_${BOARD}.bin)
+set(NPCX_IMAGE_FILE  ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}_${BOARD}.bin)
 
 set(TARGET_IMAGE_ADDR  ${CONFIG_FLASH_BASE_ADDRESS})
 set(TARGET_IMAGE_SIZE  ${CONFIG_FLASH_SIZE})
@@ -9,6 +9,6 @@ board_set_flasher_ifnset(openocd)
 board_set_debugger_ifnset(openocd)
 
 board_finalize_runner_args(openocd
-  --cmd-load "flash_npcx ${MONITOR_IMAGE_FILE} ${TARGET_IMAGE_FILE} ${TARGET_IMAGE_ADDR} ${TARGET_IMAGE_SIZE}"
+  --cmd-load "flash_npcx ${MONITOR_IMAGE_FILE} ${NPCX_IMAGE_FILE} ${TARGET_IMAGE_ADDR} ${TARGET_IMAGE_SIZE}"
   --cmd-verify "verify_npcx"
   )

boards/arm/npcx7m6fb_evb/npcx7m6fb_evb_defconfig

@@ -8,6 +8,11 @@ CONFIG_SOC_NPCX7M6FB=y
 CONFIG_SOC_SERIES_NPCX7=y
 CONFIG_BOARD_NPCX7M6FB_EVB=y
 
+# Enable NPCX firmware header
+CONFIG_NPCX_HEADER=y
+CONFIG_NPCX_HEADER_SPI_MAX_CLOCK_50=y
+CONFIG_NPCX_HEADER_SPI_READ_MODE_DUAL=y
+
 # Enable MPU
 CONFIG_ARM_MPU=y
 

soc/arm/nuvoton_npcx/Kconfig

@@ -11,6 +11,155 @@ config SOC_FAMILY
 	string
 	default "nuvoton_npcx"
 
+menuconfig NPCX_HEADER
+	bool "Enable the output binary with NPCX binary header"
+	help
+	  On NPCX series chip, the NPCX ROM code loads firmware image from flash
+	  to RAM by the firmware binary header setting. Enable this to invoke
+	  the 'ecst' which generates the NPCX firmware header.
+
+if NPCX_HEADER
+
+config NPCX_HEADER_CHIP
+	string
+	default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC
+	default "npcx7m7" if SOC_NPCX7M7FC
+
+choice
+	prompt "Clock rate to use for SPI flash"
+	default NPCX_HEADER_SPI_MAX_CLOCK_20
+	help
+	  This selects the max clock rate that will be used for loading firmware
+	  binary from flash to RAM.
+
+config NPCX_HEADER_SPI_MAX_CLOCK_20
+	bool "SPI flash max clock rate of 20 MHz"
+
+config NPCX_HEADER_SPI_MAX_CLOCK_25
+	bool "SPI flash max clock rate of 25 MHz"
+
+config NPCX_HEADER_SPI_MAX_CLOCK_33
+	bool "SPI flash max clock rate of 33 MHz"
+
+config NPCX_HEADER_SPI_MAX_CLOCK_40
+	bool "SPI flash max clock rate of 40 MHz"
+
+config NPCX_HEADER_SPI_MAX_CLOCK_50
+	bool "SPI flash max clock rate of 50 MHz"
+endchoice
+
+config NPCX_HEADER_SPI_MAX_CLOCK
+	int
+	default 20 if NPCX_HEADER_SPI_MAX_CLOCK_20
+	default 25 if NPCX_HEADER_SPI_MAX_CLOCK_25
+	default 33 if NPCX_HEADER_SPI_MAX_CLOCK_33
+	default 40 if NPCX_HEADER_SPI_MAX_CLOCK_40
+	default 50 if NPCX_HEADER_SPI_MAX_CLOCK_50
+
+choice
+	prompt "Reading mode used by the SPI flash"
+	default NPCX_HEADER_SPI_READ_MODE_NORMAL
+	help
+	  This sets the reading mode that can be used by the SPI flash.
+	  Reading modes supported are normal, fast, dual, and quad.
+
+config NPCX_HEADER_SPI_READ_MODE_NORMAL
+	bool "SPI flash operates with normal reading mode"
+
+config NPCX_HEADER_SPI_READ_MODE_FAST
+	bool "SPI flash operates with fast reading mode"
+
+config NPCX_HEADER_SPI_READ_MODE_DUAL
+	bool "SPI flash operates with dual reading mode"
+
+config NPCX_HEADER_SPI_READ_MODE_QUAD
+	bool "SPI flash operates with quad reading mode"
+endchoice
+
+config NPCX_HEADER_SPI_READ_MODE
+	string
+	default "normal" if NPCX_HEADER_SPI_READ_MODE_NORMAL
+	default "fast" if NPCX_HEADER_SPI_READ_MODE_FAST
+	default "dual" if NPCX_HEADER_SPI_READ_MODE_DUAL
+	default "quad" if NPCX_HEADER_SPI_READ_MODE_QUAD
+
+choice
+	prompt "Core clock to SPI flash clock ratio"
+	default NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
+	help
+	  This sets the clock ratio (core clock / SPI clock)
+
+config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
+	bool "NPCX SPI clock ratio 1"
+	help
+	  The SPI flash clock has the same frequency as the core clock.
+
+config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
+	bool "NPCX SPI clock ratio 2"
+	help
+	  The core clock frequency is twice the flash clock frequency.
+endchoice
+
+config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO
+	int
+	default 1 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
+	default 2 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
+
+config NPCX_HEADER_ENABLE_HEADER_CRC
+	bool "Enable header crc check"
+	help
+	  When enabled, the header will be verified at boot using a crc
+	  checksum.
+
+config NPCX_HEADER_ENABLE_FIRMWARE_CRC
+	bool "Enable firmware image crc check"
+	help
+	  When enabled, the firmware image will be verified at boot using a
+	  crc checksum.
+
+choice
+	prompt "Flash size"
+	default NPCX_HEADER_FLASH_SIZE_0P5M_1M if SOC_SERIES_NPCX7
+	default NPCX_HEADER_FLASH_SIZE_16M
+	help
+	  This sets the SPI flash size.
+
+config NPCX_HEADER_FLASH_SIZE_0P5M_1M
+	bool "SPI flash size 0.5M or 1M Bytes"
+	help
+	  The SPI flash size is 0.5M or 1M Bytes.
+
+config NPCX_HEADER_FLASH_SIZE_2M
+	bool "SPI flash size 2M Bytes"
+	help
+	  The SPI flash size is 2M Bytes.
+
+config NPCX_HEADER_FLASH_SIZE_4M
+	bool "SPI flash size 4M Bytes"
+	help
+	  The SPI flash size is 4M Bytes.
+
+config NPCX_HEADER_FLASH_SIZE_8M
+	bool "SPI flash size 8M Bytes"
+	help
+	  The SPI flash size is 8M Bytes.
+
+config NPCX_HEADER_FLASH_SIZE_16M
+	bool "SPI flash size 16M Bytes"
+	help
+	  The SPI flash size is 16M Bytes.
+endchoice
+
+config NPCX_HEADER_FLASH_SIZE
+	int
+	default 1 if NPCX_HEADER_FLASH_SIZE_0P5M_1M
+	default 2 if NPCX_HEADER_FLASH_SIZE_2M
+	default 4 if NPCX_HEADER_FLASH_SIZE_4M
+	default 8 if NPCX_HEADER_FLASH_SIZE_8M
+	default 16 if NPCX_HEADER_FLASH_SIZE_16M
+
+endif # NPCX_HEADER
+
 # Select SoC Part No. and configuration options
 source "soc/arm/nuvoton_npcx/*/Kconfig.soc"
 

soc/arm/nuvoton_npcx/common/CMakeLists.txt

@@ -5,3 +5,27 @@ zephyr_include_directories(.)
 zephyr_sources(
   scfg.c
 )
+
+# Check for disabling header CRC.
+if (NOT DEFINED CONFIG_NPCX_HEADER_ENABLE_HEADER_CRC)
+    set(NPCX_HEADER_HCRC "-nohcrc")
+endif()
+
+# Check for disabling firmware CRC.
+if (NOT DEFINED CONFIG_NPCX_HEADER_ENABLE_FIRMWARE_CRC)
+    set(NPCX_HEADER_FCRC "-nofcrc")
+endif()
+
+if (DEFINED CONFIG_NPCX_HEADER)
+  set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+    COMMAND ${PYTHON_EXECUTABLE} ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/ecst/ecst.py
+    -i ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin
+    -o ${NPCX_IMAGE_FILE}
+    ${NPCX_HEADER_HCRC} ${NPCX_HEADER_FCRC}
+    -chip ${CONFIG_NPCX_HEADER_CHIP}
+    -flashsize ${CONFIG_NPCX_HEADER_FLASH_SIZE}
+    -spiclkratio ${CONFIG_NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO}
+    -spimaxclk ${CONFIG_NPCX_HEADER_SPI_MAX_CLOCK}
+    -spireadmode ${CONFIG_NPCX_HEADER_SPI_READ_MODE}
+  )
+endif()