soc/riscv/sifive-freedom/fe310: use correct SYS_CLOCK_HW_CYCLES_PER_SEC

This commit introduces changes in three places in order to fix the
problem with timer-related tests on FE310-based boards:
* tests/kernel/sleep/kernel.common.timing
* tests/kernel/tickless/tickless_concept/kernel.tickless.concept
* tests/kernel/workq/work_queue/kernel.workqueue

The first change is the modification of the SYS_CLOCK_HW_CYCLES_PER_SEC
value back to 32768 Hz to match FE310's datasheet description.

The second change is CLINT frequency reduction in Renode simulation
model to 16 MHz to correspond with the oscillator frequency given by the
FE310's datasheet and the HiFive1 board schematic. This fixes the first
two tests.

The last change is reducing the MIN_DELAY define to 100. This causes the
RISC-V machine timer driver to update the mtimecmp register more often,
which in turn addresses the `work_queue/kernel.workqueue` problem with
work items finishing prematurely, causing the above-mentioned test to
fail.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>

boards/riscv/hifive1/support/hifive1.resc

@@ -3,9 +3,17 @@
 
 $name?="SiFive-FE310"
 
+set platform
+"""
+using "platforms/cpus/sifive-fe310.repl"
+
+clint:
+    frequency: 16000000
+"""
+
 using sysbus
 mach create $name
-machine LoadPlatformDescription @platforms/cpus/sifive-fe310.repl
+machine LoadPlatformDescriptionFromString $platform
 
 sysbus Tag <0x10008000 4> "PRCI_HFROSCCFG" 0xFFFFFFFF
 sysbus Tag <0x10008008 4> "PRCI_PLLCFG" 0xFFFFFFFF

drivers/timer/Kconfig.riscv_machine

@@ -28,3 +28,11 @@ config RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER
 	  The division ratio should define in devicetree,
 	  and it is desirable usage that references it with using a function such as
 	  dt_node_int_prop_int from Kconfig. (Tune in the conf file is not preferable.)
+
+config RISCV_MACHINE_TIMER_MIN_DELAY
+	int
+	default 100
+	help
+	  Specifies the minimum number of machine cycles before the RISC-V machine
+	  time compare register is allowed to be updated by the RISC-V machine timer
+	  driver.

drivers/timer/riscv_machine_timer.c

@@ -14,7 +14,7 @@
 				 / (uint64_t)CONFIG_SYS_CLOCK_TICKS_PER_SEC))
 #define MAX_CYC INT_MAX
 #define MAX_TICKS ((MAX_CYC - CYC_PER_TICK) / CYC_PER_TICK)
-#define MIN_DELAY 1000
+#define MIN_DELAY CONFIG_RISCV_MACHINE_TIMER_MIN_DELAY
 
 #define TICKLESS IS_ENABLED(CONFIG_TICKLESS_KERNEL)
 

soc/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series

@@ -6,7 +6,7 @@ config SOC_SERIES
 	default "sifive-freedom"
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 320000
+	default 32768
 
 config RISCV_SOC_INTERRUPT_INIT
 	default y