drivers: pinctrl: stm32: initial version
Add initial version for STM32 pinctrl driver. Driver has been written re-using many of the already existing parts in drivers/pinmux/pinmux_stm32.c. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
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5 changed files with 356 additions and 0 deletions
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@ -5,3 +5,4 @@ zephyr_library()
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zephyr_library_sources(common.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AF pinctrl_gd32_af.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AFIO pinctrl_gd32_afio.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_STM32 pinctrl_stm32.c)
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@ -30,5 +30,6 @@ config PINCTRL_DYNAMIC
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peripheral at early boot stages depending on a certain input.
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source "drivers/pinctrl/Kconfig.gd32"
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source "drivers/pinctrl/Kconfig.stm32"
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endif # PINCTRL
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16
drivers/pinctrl/Kconfig.stm32
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16
drivers/pinctrl/Kconfig.stm32
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@ -0,0 +1,16 @@
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# Copyright (c) 2021 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_STM32
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bool "Pin controller driver for STM32 MCUs"
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depends on SOC_FAMILY_STM32
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default y
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help
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Enable pin controller driver for STM32 MCUs
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config PINCTRL_STM32_REMAP_INIT_PRIORITY
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int "Remap initialization priority"
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default 2
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help
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Initialization priority for the routine in charge of configuring the
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remap for pins PA11/12.
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236
drivers/pinctrl/pinctrl_stm32.c
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236
drivers/pinctrl/pinctrl_stm32.c
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@ -0,0 +1,236 @@
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/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2021 Linaro Limited
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* Copyright (c) 2021 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/clock_control/stm32_clock_control.h>
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#include <drivers/pinctrl.h>
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#include <gpio/gpio_stm32.h>
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#include <pm/device_runtime.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_gpio.h>
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#include <stm32_ll_system.h>
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/**
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* @brief Array containing pointers to each GPIO port.
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*
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* Entries will be NULL if the GPIO port is not enabled.
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*/
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static const struct device * const gpio_ports[] = {
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioa)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiob)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioc)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiod)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioe)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiof)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiog)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioh)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioi)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioj)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiok)),
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};
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/** Number of GPIO ports. */
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static const size_t gpio_ports_cnt = ARRAY_SIZE(gpio_ports);
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#if DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), remap_pa11)
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#define REMAP_PA11 DT_PROP(DT_NODELABEL(pinctrl), remap_pa11)
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#endif
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#if DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), remap_pa12)
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#define REMAP_PA12 DT_PROP(DT_NODELABEL(pinctrl), remap_pa12)
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#endif
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#if DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), remap_pa11_pa12)
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#define REMAP_PA11_PA12 DT_PROP(DT_NODELABEL(pinctrl), remap_pa11_pa12)
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#endif
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#if REMAP_PA11 || REMAP_PA12 || REMAP_PA11_PA12
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int stm32_pinmux_init_remap(const struct device *dev)
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{
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ARG_UNUSED(dev);
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#if REMAP_PA11 || REMAP_PA12
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#if !defined(CONFIG_SOC_SERIES_STM32G0X)
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#error "Pin remap property available only on STM32G0 SoC series"
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#endif
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
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#if REMAP_PA11
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LL_SYSCFG_EnablePinRemap(LL_SYSCFG_PIN_RMP_PA11);
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#endif
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#if REMAP_PA12
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LL_SYSCFG_EnablePinRemap(LL_SYSCFG_PIN_RMP_PA12);
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#endif
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#elif REMAP_PA11_PA12
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#if !defined(SYSCFG_CFGR1_PA11_PA12_RMP)
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#error "Pin remap property available only on STM32F070x SoC series"
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#endif
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
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LL_SYSCFG_EnablePinRemap();
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#endif /* (REMAP_PA11 || REMAP_PA12) || REMAP_PA11_PA12 */
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return 0;
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}
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SYS_INIT(stm32_pinmux_init_remap, PRE_KERNEL_1,
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CONFIG_PINCTRL_STM32_REMAP_INIT_PRIORITY);
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#endif /* REMAP_PA11 || REMAP_PA12 || REMAP_PA11_PA12 */
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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/**
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* @brief Helper function to check and apply provided pinctrl remap
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* configuration.
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*
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* Check operation verifies that pin remapping configuration is the same on all
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* pins. If configuration is valid AFIO clock is enabled and remap is applied
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*
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* @param pins List of pins to be configured.
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* @param pin_cnt Number of pins.
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*
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* @retval 0 If successful
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* @retval -EINVAL If pins have an incompatible set of remaps.
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*/
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static int stm32_pins_remap(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt)
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{
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uint8_t pos;
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uint32_t reg_val;
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volatile uint32_t *reg;
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uint16_t remap;
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remap = (uint8_t)STM32_DT_PINMUX_REMAP(pins[0].pinmux);
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/* not remappable */
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if (remap == NO_REMAP) {
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return 0;
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}
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for (size_t i = 1U; i < pin_cnt; i++) {
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if (STM32_DT_PINMUX_REMAP(pins[i].pinmux) != remap) {
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return -EINVAL;
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}
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}
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/* A valid remapping configuration is available */
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/* Apply remapping before proceeding with pin configuration */
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
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if (STM32_REMAP_REG_GET(remap) == 0U) {
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reg = &AFIO->MAPR;
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} else {
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reg = &AFIO->MAPR2;
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}
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pos = STM32_REMAP_SHIFT_GET(remap);
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reg_val = *reg;
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reg_val &= ~(STM32_REMAP_MASK_GET(remap) << pos);
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reg_val |= STM32_REMAP_VAL_GET(remap) << pos;
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*reg = reg_val;
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return 0;
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}
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
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static int stm32_pin_configure(uint32_t pin, uint32_t func, uint32_t altf)
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{
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const struct device *port_device;
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int ret = 0;
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if (STM32_PORT(pin) >= gpio_ports_cnt) {
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return -EINVAL;
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}
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port_device = gpio_ports[STM32_PORT(pin)];
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if ((port_device == NULL) || (!device_is_ready(port_device))) {
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return -ENODEV;
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}
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#ifdef CONFIG_PM_DEVICE_RUNTIME
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ret = pm_device_runtime_get(port_device);
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if (ret < 0) {
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return ret;
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}
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#endif
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gpio_stm32_configure(port_device, STM32_PIN(pin), func, altf);
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#ifdef CONFIG_PM_DEVICE_RUNTIME
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ret = pm_device_runtime_put(port_device);
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#endif
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return ret;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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uint32_t pin, mux;
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uint32_t func = 0;
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int ret = 0;
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ARG_UNUSED(reg);
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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ret = stm32_pins_remap(pins, pin_cnt);
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if (ret < 0) {
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return ret;
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}
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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mux = pins[i].pinmux;
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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uint32_t pupd;
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if (STM32_DT_PINMUX_FUNC(mux) == ALTERNATE) {
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func = pins[i].pincfg | STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC;
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} else if (STM32_DT_PINMUX_FUNC(mux) == ANALOG) {
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func = pins[i].pincfg | STM32_MODE_INPUT | STM32_CNF_IN_ANALOG;
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} else if (STM32_DT_PINMUX_FUNC(mux) == GPIO_IN) {
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func = pins[i].pincfg | STM32_MODE_INPUT;
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pupd = func & (STM32_PUPD_MASK << STM32_PUPD_SHIFT);
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if (pupd == STM32_PUPD_NO_PULL) {
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func = func | STM32_CNF_IN_FLOAT;
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} else {
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func = func | STM32_CNF_IN_PUPD;
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}
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} else {
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/* Not supported */
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__ASSERT_NO_MSG(STM32_DT_PINMUX_FUNC(mux));
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}
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#else
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if (STM32_DT_PINMUX_FUNC(mux) < STM32_ANALOG) {
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func = pins[i].pincfg | STM32_MODER_ALT_MODE;
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} else if (STM32_DT_PINMUX_FUNC(mux) == STM32_ANALOG) {
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func = STM32_MODER_ANALOG_MODE;
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} else {
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/* Not supported */
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__ASSERT_NO_MSG(STM32_DT_PINMUX_FUNC(mux));
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}
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
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pin = STM32PIN(STM32_DT_PINMUX_PORT(mux),
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STM32_DT_PINMUX_LINE(mux));
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ret = stm32_pin_configure(pin, func, STM32_DT_PINMUX_FUNC(mux));
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if (ret < 0) {
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return ret;
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}
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}
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return 0;
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}
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102
soc/arm/st_stm32/common/pinctrl_soc.h
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102
soc/arm/st_stm32/common/pinctrl_soc.h
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/*
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* Copyright (c) 2020 Linaro Ltd.
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* Copyright (c) 2021 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* STM32 SoC specific helpers for pinctrl driver
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*/
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#ifndef ZEPHYR_SOC_ARM_ST_STM32_COMMON_PINCTRL_SOC_H_
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#define ZEPHYR_SOC_ARM_ST_STM32_COMMON_PINCTRL_SOC_H_
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#include <devicetree.h>
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#include <zephyr/types.h>
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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#include <dt-bindings/pinctrl/stm32f1-pinctrl.h>
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#else
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#include <dt-bindings/pinctrl/stm32-pinctrl.h>
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @cond INTERNAL_HIDDEN */
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/** Type for STM32 pin. */
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typedef struct pinctrl_soc_pin {
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/** Pinmux settings (port, pin and function). */
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uint32_t pinmux;
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/** Pin configuration (bias, drive and slew rate). */
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uint32_t pincfg;
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} pinctrl_soc_pin_t;
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/**
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* @brief Utility macro to initialize pinmux field in #pinctrl_pin_t.
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*
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* @param node_id Node identifier.
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*/
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#define Z_PINCTRL_STM32_PINMUX_INIT(node_id) DT_PROP(node_id, pinmux)
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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/**
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* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t (F1).
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*
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* @param node_id Node identifier.
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*/
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#define Z_PINCTRL_STM32_PINCFG_INIT(node_id) \
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(((STM32_NO_PULL * DT_PROP(node_id, bias_disable)) << STM32_PUPD_SHIFT) | \
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((STM32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << STM32_PUPD_SHIFT) | \
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((STM32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << STM32_PUPD_SHIFT) | \
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((STM32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << STM32_CNF_OUT_0_SHIFT) | \
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((STM32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << STM32_CNF_OUT_0_SHIFT) | \
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(DT_ENUM_IDX(node_id, slew_rate) << STM32_MODE_OSPEED_SHIFT))
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#else
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/**
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* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t (non-F1).
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*
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* @param node_id Node identifier.
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*/
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#define Z_PINCTRL_STM32_PINCFG_INIT(node_id) \
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(((STM32_NO_PULL * DT_PROP(node_id, bias_disable)) << STM32_PUPDR_SHIFT) | \
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((STM32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << STM32_PUPDR_SHIFT) | \
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((STM32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << STM32_PUPDR_SHIFT) | \
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((STM32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << STM32_OTYPER_SHIFT) | \
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((STM32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << STM32_OTYPER_SHIFT) | \
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(DT_ENUM_IDX(node_id, slew_rate) << STM32_OSPEEDR_SHIFT))
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#endif /* CONFIG_SOC_SERIES_STM32F1X */
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/**
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* @brief Utility macro to initialize each pin.
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*
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* @param node_id Node identifier.
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* @param state_prop State property name.
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* @param idx State property entry index.
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*/
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#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \
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{ .pinmux = Z_PINCTRL_STM32_PINMUX_INIT( \
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DT_PROP_BY_IDX(node_id, state_prop, idx)), \
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.pincfg = Z_PINCTRL_STM32_PINCFG_INIT( \
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DT_PROP_BY_IDX(node_id, state_prop, idx)) },
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/**
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* @brief Utility macro to initialize state pins contained in a given property.
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*
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* @param node_id Node identifier.
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* @param prop Property name describing state pins.
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*/
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)}
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/** @endcond */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_SOC_ARM_ST_STM32_COMMON_PINCTRL_SOC_H_ */
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