soc: xtensa: rework DT_L2_SRAM and DT_L2_SRAM
Rename DT_L2_SRAM_* to just L2_SRAM_* and set it using new DT macros. Do something similar for DT_LP_SRAM_* renamed to LP_SRAM_* Updated the intel_gna driver as it used the DT_L2_SRAM_* defines. This change also lets us remove dts_fixup.h on intel_s1000 and intel_apl_adsp SoCs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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aa63b07019
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8aeb8a3814
8 changed files with 26 additions and 46 deletions
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@ -130,8 +130,8 @@ static int intel_gna_setup_page_table(void *physical, size_t size,
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LOG_DBG("physical %p size %u virtual %p", physical, size, virtual);
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if (((phys_addr + size - DT_L2_SRAM_BASE) > DT_L2_SRAM_SIZE) ||
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(phys_addr < DT_L2_SRAM_BASE)) {
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if (((phys_addr + size - L2_SRAM_BASE) > L2_SRAM_SIZE) ||
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(phys_addr < L2_SRAM_BASE)) {
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LOG_ERR("model at %p of size %u exceeds L2 SRAM space",
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physical, size);
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return -EINVAL;
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@ -63,7 +63,7 @@ extern "C" {
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#define GNA_LAYER_DESC_ALIGN (128)
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#define GNA_ADDRESSABLE_MEM_SIZE DT_L2_SRAM_SIZE
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#define GNA_ADDRESSABLE_MEM_SIZE L2_SRAM_SIZE
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#define GNA_NUM_PG_TABLE_INDEX_BITS 10
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#define GNA_NUM_PG_TABLE_ENTRIES BIT(GNA_NUM_PG_TABLE_INDEX_BITS)
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#define GNA_PG_SIZE_IN_BITSHIFT 12
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@ -1,15 +0,0 @@
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/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define DT_L2_SRAM_SIZE (CONFIG_SRAM_SIZE * 1024)
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#define DT_LP_SRAM_BASE DT_REG_ADDR(DT_INST(1, mmio_sram))
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#define DT_LP_SRAM_SIZE DT_REG_SIZE(DT_INST(1, mmio_sram))
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/* End of SoC Level DTS fixup file */
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@ -439,7 +439,7 @@ SECTIONS
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/* stack */
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_end = ALIGN(8);
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PROVIDE(end = ALIGN(8));
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__stack = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE;
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__stack = L2_SRAM_BASE + L2_SRAM_SIZE;
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/* dma buffers */
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.lpbuf (NOLOAD): ALIGN(4)
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{
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@ -447,7 +447,7 @@ SECTIONS
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*(.dma_buffers)
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_dma_buf_end = ABSOLUTE(.);
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} >LPRAM_REGION
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_heap_sentry = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE;
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_heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;
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.comment 0 : { *(.comment) }
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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@ -9,12 +9,15 @@
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/* L2 HP SRAM */
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#define HP_RAM_RESERVE_HEADER_SPACE 0x00010000
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#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
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#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
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#ifdef CONFIG_BOOTLOADER_MCUBOOT
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#define SRAM_BASE (DT_L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
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#define SRAM_SIZE (DT_L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
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#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
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#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
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#else
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#define SRAM_BASE (DT_L2_SRAM_BASE)
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#define SRAM_SIZE (DT_L2_SRAM_SIZE)
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#define SRAM_BASE (L2_SRAM_BASE)
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#define SRAM_SIZE (L2_SRAM_SIZE)
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#endif
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/* The reset vector address in SRAM and its size */
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@ -91,8 +94,8 @@
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#define IDT_SIZE 0x2000
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/* low power ram where DMA buffers are typically placed */
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#define LPRAM_BASE (DT_LP_SRAM_BASE)
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#define LPRAM_SIZE (DT_LP_SRAM_SIZE)
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#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
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#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
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#include <platform/memory.h>
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@ -1,11 +0,0 @@
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/* SPDX-License-Identifier: Apache-2.0 */
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/* SoC level DTS fixup file */
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#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define DT_L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024
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#define DT_LP_SRAM_BASE DT_REG_ADDR(DT_INST(1, mmio_sram))
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#define DT_LP_SRAM_SIZE DT_REG_SIZE(DT_INST(1, mmio_sram))
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/* End of SoC Level DTS fixup file */
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@ -449,7 +449,7 @@ SECTIONS
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/* stack */
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_end = ALIGN(8);
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PROVIDE(end = ALIGN(8));
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__stack = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE;
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__stack = L2_SRAM_BASE + L2_SRAM_SIZE;
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/* dma buffers */
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.lpbuf (NOLOAD): ALIGN(4)
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{
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@ -457,7 +457,7 @@ SECTIONS
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*(.dma_buffers)
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_dma_buf_end = ABSOLUTE(.);
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} >LPRAM_REGION
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_heap_sentry = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE;
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_heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;
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.comment 0 : { *(.comment) }
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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@ -11,12 +11,15 @@
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/* L2 HP SRAM */
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#define L2_VECTOR_SIZE 0x1000
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#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
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#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
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#ifdef CONFIG_BOOTLOADER_MCUBOOT
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#define SRAM_BASE (DT_L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
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#define SRAM_SIZE (DT_L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
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#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
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#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
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#else
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#define SRAM_BASE (DT_L2_SRAM_BASE)
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#define SRAM_SIZE (DT_L2_SRAM_SIZE)
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#define SRAM_BASE (L2_SRAM_BASE)
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#define SRAM_SIZE (L2_SRAM_SIZE)
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#endif
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/* The reset vector address in SRAM and its size */
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@ -66,10 +69,10 @@
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#define IDT_SIZE 0x2000
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/* low power ram where DMA buffers are typically placed */
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#define LPRAM_BASE (DT_LP_SRAM_BASE)
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#define LPRAM_SIZE (DT_LP_SRAM_SIZE)
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#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
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#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
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/* Boot vector resideing in LP-SRAM for core #1 */
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#define LPSRAM_BOOT_VECTOR_ADDR (DT_LP_SRAM_BASE + 0x08)
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#define LPSRAM_BOOT_VECTOR_ADDR (LP_SRAM_BASE + 0x08)
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#endif /* __INC_MEMORY_H */
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