Fix the RTC device tree node for the NXP K6x SoC series. This device
is compatible with nxp,kinetis-rtc.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
STM32L073 soc variant is a STM32L072 with LCD peripheral.
Reflect this in dts definition by including stm32l072.dtsi
in stm32l073.dtsi.
This also allows to fix an issue on stm32l073 gpioe which
declared wrong reg definition.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The I2C controllers on the MEC1501 SoC can be attached to
different I2C output line. For example, the I2C #0 controller
can be used with I2C7 physical lines out of SoC. The output
selection is done by the attribute "port_sel". This renames
the parent I2C nodes on the SoC side to refer to
the controller themselves instead of the output lines to
avoid confusion. The labels of these nodes are also renamed
to reflect the controllers.
On the board level, the DTS labels are overwritten to indicate
the actual output lines.
Aliases are also provided in both SoC and board levels to
provide shortcuts to the DTS nodes.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SoC, driver, and board support for the CC2650 and CC2650 Sensortag
aren't currently supported and we are removing them as such. If anyone
is interesting in supporting this platform we can easily recovery it
from git.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add device tree nodes for the internal temperature sensor in the NXP
Kinetis K6x SoC series.
A temperature sensor node is added for each ADC in the SoC to allow
the user to choose which ADC instance to use for the sensor readings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add device tree nodes for the internal temperature sensor in the NXP
Kinetis KE1xF SoC series.
A temperature sensor node is added for each ADC in the SoC to allow
the user to choose which ADC instance to use for the sensor readings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Added dts additions for stm32 nucleo f767zi board, also added
and modified soc addtions for thet board.
Updated dts reference file name.
Updated yaml to take out adc for now.
Signed-off-by: Roland Ma <rolandma@yahoo.com>
The amount of lock regions differs between different sam0 MCUs.
saml10: 2
saml11: 4
samd2x: 16
saml2x: 16
samd5x: 32
ASF does not provide a definition for this, so create a new one
in dts.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Refactors the mcux gpt driver to use generated device tree macros
directly. Removes now unused dts fixup macros from i.mx rt socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Defines device tree aliases for on-chip peripherals at the soc level
instead of the board level for all lpc socs. The eliminates some
duplicate code in the board level device trees, and will allow drivers
to use device-tree generated macros directly instead of through dts
fixups.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Defines device tree aliases for on-chip peripherals at the soc level
instead of the board level for all i.mx 6/7 socs. The eliminates some
duplicate code in the board level device trees, and will allow drivers
to use device-tree generated macros directly instead of through dts
fixups.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Defines device tree aliases for on-chip peripherals at the soc level
instead of the board level for all i.mx rt socs. The eliminates some
duplicate code in the board level device trees, and will allow drivers
to use device-tree generated macros directly instead of through dts
fixups.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Defines device tree aliases for on-chip peripherals at the soc level
instead of the board level for all kinetis socs. The eliminates some
duplicate code in the board level device trees, and will allow drivers
to use device-tree generated macros directly instead of through dts
fixups.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add device_type DTS property in sram0 and sram1 nodes,
for nRF5340 Application and Network CPU, respectively.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add support for specifying PWM flags for the NXP Kinetis FlexTimer
(FTM) PWM driver through the device tree.
All in-tree clients of this PWM controller are active-low LEDs.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit fixes the following problems with the RPU device tree:
1. The core type of the RPU of ZynqMP SoC is Cortex-R5F, not
Cortex-R4.
2. RPU and APU use different interrupt controllers (PL390 GICv1 and
GIC-400 GICv2, respectively) mapped to the same CPU local bus address
region but with different offsets for the distributor and CPU
interrupt control register sets. The GIC address mapping specified by
the current dts is that of an APU and does not apply to the PL390
GICv1 of an RPU (refer to the "Zynq UltraScale+ Devices Register
Reference" document from Xilinx for more information).
For more details, refer to the issue #20217.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and
Cortex-A for APU.
Since the current Zephyr architecture cannot support AMP of Cortex-R
and Cortex-A within one project, the RPU and APU should be considered
separate platforms.
This commit relocates the device tree nodes that are not common between
RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi).
When Cortex-A53 APU support is added in the future, an additional dtsi
file (zynqmp_apu.dtsi) for specifying the APU device tree should be
added.
For more details, refer to the issue #20217.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Rename the NXP FTM instances in the KE1xF SoC to PWM to match the
other SoCs/boards using the FlexTimer as PWM generator.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This patchset enables USART3 on the 96Boards STM32 Mezzanine.
It is broken out to J10 Grove Connector.
Changes:
- Enabled USART3 in board dts.
- Updated board index.rst with uart pinouts.
- soc dtsi: enabled usart3.
Test: Tested USART3 as console at 115200 baud
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
This patch enables SPI4 on the 96Boards STM32 Sensors Mezzanine.
SPI4 has been broken out to a Grove Connector on the board.
Changes:
- Updated board dts to enable spi4
- Updated board Kconfig
- Updated board documentation
- Update board pinmux
- Updated stm32f4 pinmux header file
- Updated stm32f401 dtsi
- Updated stm32f4 defconfig to enable PORTE GPIO
- Added board to spi_loopback test
Test: spi_loopback test passed
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
Adds spi device tree bindings and nodes for the lpc54xxx and lpc55s6x
socs in preparation for adding a new spi driver.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The GIC-400 driver currently only supports SPIs because the (32) offset
for the INTIDs is hard-coded in the driver. At the driver level there is
no really difference between PPIs and SPIs so we can easily extend the
driver to support PPIs as well.
This is useful if we want to add support for the ARM Generic Timers that
use INTIDs in the PPI range.
SPI interrupts are in the range [0-987]. PPI interrupts are in the range
[0-15].
This commit adds interrupt 'type' cell to the GIC device tree binding
and changes the 'irq' cell to use interrupt type-specific index, rather
than a linear IRQ number.
The 'type'+'irq (index)' combo is automatically fixed up into a linear
IRQ number by the scripts/dts/gen_defines.py script.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add device tree elements for all gpio ports of the efr32mg12p including
the dts fixup entries.
Also remove gpio port e since this is not available in efr32mg12p socs.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
NXP's LPC family of MCU's GPIOs parameters is udated.
Boards LPC54xxx and LPC55xxx have updated values according
pin and interrupt layout.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
This commit adds basic support for nRF52833 SoC.
Changes affect introducing:
- architecuture files (dtsi)
- configuration of nrfx drivers
- adaptation of inclusions based on chosen SoC
- configuration of NFCT_PINS_AS_GPIOS depends on HAS_HW_NRF_NFCT.
Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
This patch introduces the support of the Low Power Timer
for the STM32WBxx from STMicroelectronics.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The SPI NOR driver requires that the size (in bits) be provided in the
devicetree node. Update the binding to make the property required,
and update all nodes based on the memory chip identified.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
This patch introduces the support of the Low Power Timer
for the STM32L4xx from STMicroelectronics.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds supoprt for the Atmel SAME54 SoC.
The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals
with the sam0 Cortex-M0+ and saml1x Cortex-M23 parts.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Introduce a standard watchdog alias 'watchdog0' that can be utilized
by sample/test code in the future. This helps remove the need for
CONFIG_WDT_0_NAME in dts_fixup.h files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
dts pinctrl definitions were pushed in tree without the code
available to deal with it. They have been kept waiting for the
code, but this is taking much more time than initially thought.
So in current zephyr tree, for all STM32 boards, we have pinmux.c
file which is used to configure pins and these files that are
basically no-op. This situation is creating a lot of confusion
especially to new comers, and create useless maintenance effort.
Remove these files for now.
When zephyr will ready to use them, this commit could be reverted.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit moves DMA parameters previously hard coded in the driver
to the dts.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
There is no APB2 bus on stm32f0 series.
What could be found as APB2 in CMSIS files is actually
second group of APB (A.K.A APB1_2).
Fix nodes that are using this wrong reference accorss the series.
Fixes#20310
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move the selection of the IP clock source for the modules in the NXP
Kinetis KE1xF SoCs from being hardcoded in soc.c to being specified in
the device tree.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
STM32L151XB-A SoC is almost similar to the STM32L151XB SoC except that
it has more RAM (32KiB). Hence add devicetree and Kconfig support.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Indtroduction of generic device tree bindings for keyboard scan devices.
In addition, device tree node entries and dt specific bindings where
also implemented for Microchip MEC1501
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
STM32L1 uses the same spi controller as STM32F1 so we can just set the
right addresses and enable them. We also need to add the fixup names and
to correctly include the header for ST LL HAL.
Signed-off-by: Karl Palsson <karlp@etactica.com>
1. Replace the non-existent CPU device binding ("Cortex-R") specified
by the CPU node with a proper one.
2. Relocate CPU node declaration to SoC dtsi:
The CPU node should be declared in the SoC dtsi because the core
type is SoC-dependent. In fact, this is exactly how it is done in
the Cortex-M port.
3. Remove core_intc (supposedly Cortex-R VIC):
Unlike the NVIC of Cortex-M, the VIC of Cortex-R is not a true
interrupt controller in the conventional sense and merely acts as
a CPU input port for aggregated interrupt request and vector index
signals. For this reason, there is no point in declaring it in the
device tree and specifying it as an interrupt parent. All SoCs
incorporating Cortex-R implement a separate true interrupt
controller (for instance, GIC for Zynq MPSoC and VIM for Hercules).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The patch adds initial support for STM32F030X4 SoC.
STM32F0 Cube package advises to use 'stm32f030x6' code
for both STM32F030x4 and STM32F030x6 SoC variants.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Add soc and dts files to support for most of the common peripherals
in the STM32G4 series. Add specific support for the STM32G431RB.
Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>
Add #pwm-cells property in bindings for Nordic PWMs and add this
property with a suitable value assigned to all PWM nodes in dts
files for Nordic SoCs.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit introduces separate "compatible" strings for DTS nodes
representing different types of Nordic SPI peripherals. Previously
"nordic,nrf-spi" was used for both SPI and SPIM. SPIS was already
handled separately.
Quite a few files need to be touched by this commit but the changes can
be divided into groups of related or very similar ones, distinguishable
by the initial part of the path to the modified file:
* dts/bindings/spi/
new binding for "nordic,nrf-spim" is added and common fields for all
3 types of Nordic SPI peripherals are extracted to a shared file
* dts/arm/nordic/
"compatible" properties in spiX nodes are updated (when there is no
choice as only one type of SPI peripheral is available) or replaced
with a comment pointing out that the proper type of peripheral needs
to be picked at some upper layer
* drivers/spi/
spi_nrfx_spim driver is updated with the new form of macros generated
from dts
* boards/
all spiX nodes in dts files for boards equipped with an nRF chip are
updated with the proper "compatible" property, according to the type
of SPI peripheral that is currently selected for the board by the
corresponding Kconfig choice option (SPI_x_NRF_SPI*)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit introduces separate "compatible" strings for dts nodes
representing different types of Nordic TWI peripherals. Previously
"nordic,nrf-i2c" was used for both TWI and TWIM, and TWIS was not
supported.
Quite a few files need to be touched by this commit but the changes can
be divided into groups of related or very similar ones, distinguishable
by the initial part of the path to the modified file:
* dts/bindings/i2c/
new bindings for "nordic,nrf-twim" and "nordic,nrf-twis" are added
and the one for "nordic,nrf-i2s" is renamed to "nordic,nrf-twi",
common fields for all these bindings are extracted to a shared file
* dts/arm/nordic/
"compatible" properties in i2cX nodes are updated (when there is no
choice as only one type of TWI peripheral is available) or replaced
with a comment pointing out that the proper type of peripheral needs
to be picked at some upper layer
* drivers/i2c/
both flavors of i2c_nrfx drivers are updated with the new names of
macros generated from dts
* boards/
all i2cX nodes in dts files for boards equipped with an nRF chip are
updated with the proper "compatible" property, according to the type
of TWI peripheral that is currently selected for the board by the
corresponding Kconfig choice option (I2C_x_NRF_TWI*)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use the device tree to assign the correct peripheral clock to each
UART/USART/LEUART. Previously, the clock identifier was determined
through the sequence number of the instantiated UART. This meant
configuring all UARTs when only one of the later UARTs was required.
Signed-off-by: Oane Kingma <o.kingma@interay.com>
This adds support for Kinestis K22
Co-authored-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Co-authored-by: Oliver Stäbler <oliver.staebler@bytesatwork.ch>
Co-authored-by: Tom Burdick <thomas.burdick@gmail.com>
Signed-off-by: Tom Burdick <thomas.burdick@gmail.com>
Add RTC timer driver for CC13X2/CC26X2, and use it instead of systick
as system clock. It is necessary to use this timer for power
management support, so that the system can exit from deep sleep upon
expiry of timeouts.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
4 are found: 2 with a counter of 16bits and 2 with a counter of 32 bits.
However, first 32bits instance will not be exposed as it will be used by
rtos timer driver directly to implement k_busy_wait()
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The driver for STM32's independent watchdog already exists and is
compatible with the stm32wb SoC. Enable the independent watchdog
for the stm32wb series for use with this driver.
Signed-off-by: Robert Weber <robertweber95@gmail.com>
The KE1xF SoC family SIM unit differs from the other Kinetis family
SoCs. Add a unique compatiable and binding for it.
Fixes#18160
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
For quite a few peripherals that are currently supported by nrfx HALs
or drivers there are no definitions of corresponding CMSIS-Core
peripheral accessing symbols that would provide their base addresses
in the proper domain (secure or non-secure), accordingly to the build
target. This commits adds devicetree nodes for these peripherals so
that their base addresses can be used in definitions of the accessing
symbols mentioned above.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Pull out the LPO fixed-clock that is part of the PMC hardware block as
its own child node of the PMC block. This is because the PMC could have
its own driver associated with it that is seperate from the LPO clk.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Update the ADC bindings to include #io-channel-cells and update the
related dts files to set #io-channel-cells.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
'interrupt-parent' should contain just the phandle of the node
interrupts are sent to.
This node (gic: interrupt-controller@f9010000) doesn't generate any
interrupts, so the 'interrupt-parent' value is never used (this is why
it wasn't caught). It'll give an error later with 'interrupt-parent'
declared as 'type: phandle' in bindings though.
Don't know what was intended. Just remove the 0.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
SPI3 clock info were missing and following macros were
not generated:
- DT_ST_STM32_SPI_FIFO_40003C00_CLOCK_BITS
- DT_ST_STM32_SPI_FIFO_40003C00_CLOCK_BUS
Signed-off-by: Armando Visconti <armando.visconti@st.com>
This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based
platform for Cortex-R based testing. This SoC only supports an
interrupt controller and serial port for limited testing.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
Remove unused "system-clock-frequency" property, we don't have this
defined in various bindings and thus aren't using it.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Use clock specified in the device tree for obtaining the source clock
frequency for the pwm_mcux_ftm driver instead of relying on having an
NXP Kinetis MCG clock available in all SoCs supporting FlexTimer (FTM)
modules.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
NRF_UICR needs to be defined for nRF9160 SoC in
nrfx_config_nrf9160.h, because it is not defined
in nrfx/hal/mdk/nrf9160.h (as it is a Secure-only
peripheral).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
With the new DT checks the dts bindings for "nxp,flexpwm" and
"nxp,imx-pwm" had old conventions that we now treat as build errors.
Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
i.MX RT10XX processors have four eFlexPWM modules, each containing
four 2-channels PWM submodules.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
The true mmio-sram nodes should not have had a 'device_type' property.
Remove it from the cases that we clearly know are SRAM.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Trying to get rid of properties that appear on device tree nodes but
aren't declared in bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Trying to get rid of properties that appear on device tree nodes but
aren't declared in bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Trying to get rid of properties that appear on device tree nodes but
aren't declared in bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
These are not declared in dts/bindings/arm/nxp,kinetis-sim.yaml and do
not generate any output.
Trying to get rid of properties that appear on device tree nodes but
aren't declared in bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
A minor spelling fix in an inline comment in
both nRF9160 Secure and Non-Secure .dtsi headers.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
These are not declared in any binding and do not generate any output.
Trying to get rid of properties that appear on device tree nodes but
aren't declared in bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Fix the following dtc warning:
mimxrt1064_evk.dts.pre.tmp:78.31-85.5: Warning (spi_bus_bridge):
/soc/flexspi1@402a4000: node name for SPI buses should be 'spi'
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Several aliases were added to nrf9160[ns].dtsi files solely for
the purpose of getting base addresses of certain hardware modules
via DT_ macros generated for these aliases.
Since for one-instance modules the same can be now achieved with
standard DT_INST_0_* macros, there is no need to keep these aliases.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
pinmux: Add the relevant definition of the spi3 pin
dts: Fix a bug, spi3 does not have a label
soc: Supplement spi3 related definition
Signed-off-by: Findlay Feng <i@fengch.me>
stm32f429.dtsi wrongly introduced i2s nodes 4, 5 and 6.
Remove them as actually only i2s nodes 2 and 3 are supported on
these socs.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a kernel timer driver for the MEC1501 32KHz RTOS timer.
This timer is a count down 32-bit counter clocked at a fixed
32768 Hz. It features one-shot, auto-reload, and halt count down
while the Cortex-M is halted by JTAG/SWD. This driver is based
on the new Intel local APIC driver. The driver was tuned for
accuracy at small sleep values. Added a work-around for RTOS
timer restart issue. RTOS timer driver requires board ticks per
second to be 32768 if tickless operation is configured.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This was always intended to be a bytestring rather than an array, but
full support was missing. Since that has been addressed switch it to
the preferred format.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The property is required on all SPI clients, but was missing from
several devicetree nodes. Set it, using the capitalized version of the
node alias when present, with "jedec,spi-nor#0" as the fallback.
Closes#17662
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Have the SoC dtsi files for microchip mark the devices (uart & i2c) as
disabled by default and let the board dts files enable which one's they
need/use (which is what's happening already).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
spi-max-frequency is marked as required in
dts/bindings/mtd/jedec,spi-nor.yaml.
I took the value from the datasheets (133 MHz for all), and guessed that
a dummy entry is fine for QEMU.
Fixes some errors in
https://github.com/zephyrproject-rtos/zephyr/issues/17532.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
There doesn't seem to be any use of the virtualcom device in the code,
so lets remove it from the dts as it describes itself as a usb device
controller which it is not.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds a fixed clock node (representing clock driving
system bus). The added node is then referenced by peripherals requiring
information about driving clock frequency.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This commit adds 'clock-frequency' property to the cpu nodes.
The clock frequency specified in the added property is used
during platform configuration. Examples:
- The SWO logger uses clock frequency to configure SWO output.
- Plenty of platforms need CPU clock specified for their HAL.
- Most of devices with USB needs information about CPU clock
in order to configure USB clock source.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This patch populates "clocks" property in stm32 usb nodes
for clock related usb configuration code of each dtsi files
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The spi-nor flash nodes require a jedec-id property as per the binding.
We add the jedec-id's as best we can determine based on the data sheets
for the various flash modules on these boards.
However these id's should be validated by actually reading the value to
ensure they are correct.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fix USB phy node for stm32l432 and stm32l452, which contain
a USB controller and not a OTG FS controller.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
1) dts/bindings/mmc/mmc.yaml: specifies common mmc.
2) dts/bindings/mmc/nxp,imx-usdhc.yaml: specifies
nxp usdhc module which inherits mmc.
3) dts/arm/nxp/nxp_rt.dtsi: usdhc support on RT chip.
4) boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts:
usdhc slot support on mimxrt1050_evk board.
Signed-off-by: Jun Yang <jun.yang@nxp.com>
A number of minor issues with the 'fixed-clock' support:
* Fix the #clock-cells to be 0
* Fix nxp_ke1xf.dtsi to set #clock-cells 0 and the clock reference to
only be a phandle.
* Fix the generation script to only generate what it should for a
'fixed-clock'
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add clock support for STM32G0X SoC series.
Signed-off-by: Philippe Retornaz <philippe@shapescale.com
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This patch adds support for the STM32G071xx
from STMicroelectronics.
Signed-off-by: Philippe Retornaz <philippe@shapescale.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Allow individual specification of the time quanta used for the CAN bus
propagation segment and phase segment 1.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Added support for the STM32L496XE series with 512KB internal flash and
256KB SRAM of contiguous addresses.
Signed-off-by: Ioannis Konstantelias <ikonstadel@gmail.com>
The DT spec. only has "okay" and not "ok". The Linux kernel has around
12k "okay"s and 300 "ok"s.
The scripts/dts scripts only check for "disabled", so should be safe re.
those at least.
The replacement was done with
git ls-files | xargs sed -i 's/status\s*=\s*"ok"/status = "okay"/'
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit adds counter driver based on RTCC module for SiLabs Gecko
SoCs.
Tested with SLWSTK6061A / BRD4250B wireless starter kit.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
stm32wb55rg is a dual core SoC (M4/M0) with a radio/protocol stack
running on M0 core. M0 FW starts at flash address 0x80CB000.
So flash size available to zephyr is 812K instead of 1M.
Configure package size to reflect this (flash size is now 812K)
and update MPU setting to exclude M0 FW. From MPU point of view,
we set flash size to 512K since we should chose a size being a power
of 2.
If we consider there will be 2 images partitions in a FOTA scheme,
512 K is beyond image-0 and hence is sufficient to cover application
image.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
sram2a and sram2b where defined in the prospect of defining
HCI shared memory sections from device tree.
Remove them, since this is not the case anymore.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This adds support for the basic timer counter (TC) found on SAM0
series parts. This driver only supports running the counter
in 32 bit wide mode. Since this mode explicitly slaves the odd
counters to the even ones, only instances of the even ones are
defined.
Tested with tests/drivers/counter/counter_basic_api on SAMD21.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Add support for the Low Power Inter-Integrated Circuit (LPI2C)
controllers found in the NXP Kinetis KE1xF SoC series.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The node name for device_id was device_id@0 it should be
device_id@80a00c to reflect the first register region
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
ARM SysTick peripheral is optional in Cortex-M0 MCUs,
so we delete the respective dts node when the peripheral
is not present.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Atmel SAM D series SoC variants (present in the tree) all have
an ARM Cortex-M0+ core, not a Cortex-M0, so we correct this in
the .dtsi header.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Unlike Cortex-M3 and Cortex-M4, in Cortex-M7 the number of
MPU regions may vary based on the implementation. This commit
adds a DTS node for the ARM MPU peripheral in the device tree
of Cortex-M7 SoCs and updates the fixup files, so we may extract
the number of MPU regions at build time. SoCs:
- nxp_rt
- same70
- stm32f7
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds a DTS node for the ARM MPU peripheral in the
device tree of ARMv8-M SoCs (for the secure and the non-secure
DTS descriptions) and updates the fixup files. SoCs:
- nrf9160
- musca_a
- musca_b1
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Adding missing erase-block-size entries for the flash-controller
nodes in the nrf52810 and nrf52811 .dtsi files.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Move flash-controller and SRAM node definitions under SoC node.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Reduced Kconfig for counter with nRF TIMER and RTC. Added overlays
for TIMER and RTC configuration in the counter test.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This commit adds basic support for nrf52811 in the arch SoC, dts
and nrfx folders.
The nRF52811 is a Bluetooth 5.1 Direction Finding SoC with comprehensive
protocol support.
The nRF52811 SoC is capable of the latest features of Bluetooth 5.1,
the most prominent being Direction Finding.
The radio in the nRF52811 SoC has comprehensive protocol capabilities,
including Bluetooth 5.1 Directing Finding, all Bluetooth 5 features,
802.15.4, Thread, Zigbee, ANT and 2.4 GHz proprietary.
It has 4 dBm TX power and has been optimized to offer the best RX
sensitivity of all SoCs in the nRF52 series.
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
add usbd1 definition to rt dts file,
set EHCI controller config default value in rt1050 default config file,
add EHCI controller driver MACROs to dts_fixup.h,
initialize EHCI clock in rt soc.c
add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
Dts Nodes for all the GPIO portswere defined. In addition,
a new binding file was created for the gpio driver.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
Expose MEC1501 5 I2C/SMB controllers
Add Microchip specific I2C device tree properties
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
All series of stm32 have at least one ADC instance and this commit adds
one ADC node to the root dts file of each soc, and also adds fixing up
mappings to them.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
This adds interrupt support to the SAM0 GPIO driver. This is heavily
inspired by @nzmichaelh work in #5715. The primary difference
from that implementation is that here the External Interrupt
Controller (EIC) is separated out into an interrupt controller driver
that is less tightly coupled to the GPIO API. Instead it implements
more of a conversion from the EIC's own odd multiplexing to a more
traditional port and pin mask IRQ-like callback. Unfortunately,
through the EIC on the SAMD2x are relatively well behaved
in terms of pin to EIC line mappings, other chips that share the
peripheral interface are not. So the EIC driver implements a
per-line lookup to the pin and port pair using definitions extracted
from the ASF headers.
The EIC driver still makes some assumptions about how it will be used:
mostly it assumes exactly one callback per port. This should be fine
as the only intended user is the GPIO driver itself.
This has been tested with some simple programs and with
tests/drivers/gpio/gpio_basic_api on a SAMD21 breakout and an
adafruit_trinket_m0 board.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
This adds a SERCOM I2C driver for SAM0 series chips.
Tested with a SAMD21 chip on a SSD1306 display and a MLX90393
sensor. Only compile tested for SAMD20 and SAMR21.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Add initial support for the TI CC13x2 / CC26x2 series with the CC2652R
and CC1352R SoCs. The UART and GPIO peripherals are supported. Drivers
use the driverlib HAL from the TI CC13x2 / CC26x2 SDK.
Signed-off-by: Brett Witherspoon <spoonb@cdspooner.com>
Implementation of pinmux for the stm32mp157c_dk2 board.
Some UART pin mux definition has been added (mainly for
UART console and UART/SPI Arduino shield support).
This can be completed with pin mux for other stm32mp157c
UART.
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add support for stm32mp1 basic UART API with Zephyr.
UART Console and UART shell are also supported.
Async UART API and USART support is to be done.
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Move SERCOM peripherals to use the raw defines generated from DTS
parsing. This adds aliases to the DTS so that the SERCOM number
can still be used for clocking and pinmux.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
This adds support for the SAM0 DMA Controller (DMAC). Chained
transfer are not currently implemented.
Tested with tests/drivers/dma/loop_transfer and custom modifications
to that test using three parallel reloading channels. Also tested
with a trivial program that did memory->serial.
Signed-off-by: Michael Hope <mlhx@google.com>
[hageman@inthat.cloud: Rebased and updated commit message]
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Initial support for Microchip MEC1501 series is added to the tree.
Additional support for UART is also included. This SoC supports
two operational modes for interrupts (Direct and Aggregated). For
this commit, the direct capable interrupts are configured in
direct mode.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Adds Atmel SAMR21 soc which is based on SAMD21, but with a AT86RF233
radio connected internally via SPI.
The AT86RF233 is not yet supprted by Zephyr at this point.
This code is very much copy & paste from atmel_sam0/samd21
Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
Add USART1 and LPUART1 nodes on stm32wb series.
Only these 2 ones are available for now on this series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add GPIO support to stm32wb series.
Only ABCDE and H ports are available for now on this series.
Accordingly, update series dtsi file.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support to stm32wb series in stm32 clock_control driver.
Ip is similar to stm32l4 one but AHB bus presacler is renamed
to "CPU1" and CPU2 and AHB4 prescalers should be defined.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add driver support for Atmel SAM0 device ID, which is 16-bytes long.
The device ID can simply be read from memory at a known location, but
the location is only described in the data sheet, not in ASF.
For SAMD2x it's 0x0080A00C, 0x0080A040, 0x0080A044 & 0x0080A048.
For SAMD5x it's 0x008061FC, 0x00806010, 0x00806014 & 0x00806018.
This adds a new property to the device tree to define the device ID
registers for this SoC family.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
This commit adds CAN support for nucleo F746zg.
Furtermore CAN was added in stm32f7.dtsi and pinmuc_stm32f7.h
CAN_RX: PD0, CAN_TX: PD1
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
2 identical packages were defined for stm32f412 SoC, invariant "g".
Merge them in new sinclge stm32f412Xg.dtsi.
Update matching boards accordinlgy.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
SAMD20 does not have the DMA or USB peripherals and as a result
the IRQs for all subsequent lines are shifted down from SAMD21.
This splits the interrupt assignment for the SERCOMs into the
SoC specific DTS file and moves the USB definition to SAMD21 only.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Ports B and C share a common interrupt vector on kw40 and kw41z socs,
but we don't currently have a way to express this in device tree. A
check was added in commit 77cb942a97 that
correctly causes build errors on kw40/41 boards when both ports are
enabled.
Disable the port b interrupt for now until we have a better way to
handle this.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
According to nrf51 and nrf52 specifaction every peripheral is
assigned a fixed block of 0x1000 bytes. Due to that dts for
nrf51 and nrf52 chips have been updated.
The only exception is gpio for nrf52840 where gpio0 and gpio1
share the same memory regions. For this reason, the definition
of gpio for nrf52840 is different from the others.
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
On various stm32 soc packages CCM is available and SRAM size
mentionned in datasheet include CCM.
Though, actual SRAM size defined in dtsi files should not
include CCM sizes.
Fix this on impacted dtsi files.
Fixes#14779
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The iMX RT1060 and RT1064 have additional dedicated 512KB on-chip ram.
This OCRAM2 is mapped at 0x20200000, formerly OCRAM1 (flexram) mapping
which is moved to 0x20280000 in order to guarentee global OCRAM memory
continuity regardless OCRAM1 size configuration (256KB by default).
In default configuration, this gives 768KB (512+256) on-chip ram:
0x20200000 to 0x202BFFFF.
OCRAM2: 0x20200000 - 0x2027FFFF
OCRAM1(FlexRam): 0x2028FFFF - 0x202BFFFF
Add this memory region as a single node in the rt1060 device tree.
Note: MPU expects power of two memory region, in case of 768KB, let
the MPU configure 1MB instead.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
uart4 is not available on whole stm32f4 series (not on stm32f401
for instance), remove from stm32f4.dtsi
It is actually correctly defined in f405, f413 but missing in f446,
so add it in there.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
1. SW PWM device node added to common nrf5_common.dtsi
2. SW PWM node set in all nRF5x DTSI files.
Different initial settings for nRF51 and nRF52 devices.
Status is ok by default for nRF51.
3. Added yaml binding for Nordic SW PWM node.
4. Set codeowner of nordic dts bindings to @anangl
Signed-off-by: Gaute Gamnes <gaute.gamnes@nordicsemi.no>
In the recent MDK brought by nrfx 1.6.2, these legacy peripherals have
been revealed as available also in nRF52810. This patch allows their
use in Zephyr drivers.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
On currently supported stm32f3 chips,
erase-block-size = 2048
write-block-size = 2
Set these property in stm32f3 series root dtsi file.
Fixes#9686
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add nvs support to nucleo_f091rc board. This requires to
add erase-block-size property to stm32f0.dtsi.
Storage partition is set to 4kb at the end of the flash.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Initial support for Microchip MEC1701 series is incorporated to the
tree. Additional support for UART is also included. This SOC supports
two operation modes for interrupts (Direct and Aggregated). For this
commit, the interrupts are configured in direct mode.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
This patch adds basic support for the PWM devices available on the Atmel
SAM family. Beside enabling the driver, everything is selected through
the device tree, including enabling the PWM0 and PWM1 devices. Thus
CONFIG_PWM_0 and CONFIG_PWM_1 are ignored.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add EPIT (Enhanced Periodic Interrupt Timer) peripheral support
for i.MX6SoloX soc.
Origin: Original
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Adds device tree bindings for the imx enhanced LCD interface (eLCDIF)
controller. The compatible is reused from linux.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Actually, add the "status" property that enables the nodes explicitly.
They were apparently enabled by default without this property.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use the new DT_<COMPAT>_<INSTANCE>_<PROP> defines to instantiate
devices. This commit adds also ability to define individual pin
locations on SoC series that support the feature. Definitions of GPIO
pins assigned to a given location have been moved from soc_pinmap.h file
to board DTS file.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Use the new DT_<COMPAT>_<INSTANCE>_<PROP> defines to instantiate
devices. This commit adds also ability to define individual pin
locations on SoC series that support the feature. Definitions of GPIO
pins assigned to a given location have been moved from soc_pinmap.h file
to board DTS file.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Use the new DT_<COMPAT>_<INSTANCE>_<PROP> defines to instantiate
devices. This commit adds also ability to define individual pin
locations on SoC series that support the feature. Definitions of GPIO
pins assigned to a given location have been moved from soc_pinmap.h file
to board DTS file.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Add sam0_rtc_driver that implements system timer API on top of the RTC
and can be used as a replacement for the default systick timer.
Signed-off-by: Martin Benda <martin.benda@omsquare.com>
This commit introduces the possibility to have multiple
device nodes attached to the same I2S controller. For this
purpose a new i2s-device.yaml description has been introduced
with the a 'reg' property to define the logic number of the
device. For example, if two microphones are attached to the
same I2S port (say 1) to achieve stereo audio, the two microphones
might be described in dts as:
&i2s1 {
status = "ok";
mic@0 {
compatible = "...";
reg = <0>;
label = "...";
};
mic@1 {
compatible = "...";
reg = <1>;
label = "...";
};
};
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Added UART4 alternate pin function for L4 µC for PC10 and PC11.
Corrected naming of previously defined UART4 TX and RX defines.
Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
The SPI1 controller that is connected to the mcr20a block utilizes the
hardware chipselect and not a GPIO CS. So remove the cs-gpios property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The SPI0 node had a property called 'cs' which wasn't used or defined as
part of the binding yaml. So let's remove it.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We get warnings from dtc when building any of the NXP i.MX-RT boards of
the form:
mimxrt1020_evk.dts_compiled: Warning (simple_bus_reg):
/soc/random@400CC000: simple-bus unit address format
error, expected "400cc000"
Simple fix to make everything lowercase to have the unit-address and reg
match.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds STM32 L452 soc with L452xC variant. L452 has 160 KB SRAM;
therefore, mpu mem config has been extended; IRQ number is based on
'stm32l452xx.h'.
Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
Use the symbol generated from DT so that it is common for nRF9160
and nRF5 family SoCs. To avoid artificial renaming of CLOCK_POWER_IRQn
to POWER_CLOCK_IRQn.
For nRF5 family SoCs clock nodes were not defined so far, thus they are
added so that the proper DT symbol is generated for them as well.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add missing node for instance 0 of the RTC peripheral and use an alias
to the flash-controller node instead of the nvmc node definition (there
is no need to have a separate node just to get the NVMC base address).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Fix the QSPI and hyperflash nodes to be proper SPI children and expose
the address range for direct access as part of the controller's reg
region.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add support for the TRNG device contained in the i.MX RT SoCs. It uses
the existing MCUX driver, and mostly consists in adding the Kconfig and
DTS entries.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
By default, after reset SWO signal is not connected to GPIO pin.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
By default, after reset SWO signal is not connected to GPIO pin. This
commit adds required initialization code to enable support for SWO
logger. Not all SoC series support the feature.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
* Add DTS support for gpio controller driver
Signed-off-by: Ashokkumar B <ashokkumar@zilogic.com>
Signed-off-by: Subash G <subash@zilogic.com>
Signed-off-by: Vishnu K <vishnu@zilogic.com>
Signed-off-by: Vaishnavi D <vaishnavi.d@zilogic.com>
By adding 'aliases' node in SoC .dtsi file it is possible to generate
DT_ defines which specify a logical name rather than relay on module
location on APB bus. E.g. DT_SILABS_GECKO_USART_40010000_LABEL becomes
DT_SILABS_GECKO_USART_USART_0_LABEL. Thus it is possible to remove
dts_fixup.h defines.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Add uart5 nodes to stm32f1 series dts.
Provide matching dts_fixup add-on.
Signed-off-by: Chen Han <qq1433255094@outlook.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit introduces the main device tree header files (.dtsi)
for Nordic nRF9160 SOC, for both Secure and Non-Secure domains.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We only need to add the reg property in flash0 and sram0,
in the different DTS headers for the nRF SOCS. We do not
seem to need to define the nodes again. This commit applies
this simplification for flash and sram sizes definition.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Fix the following warning that shows up in some NRF device tree files:
Warning (simple_bus_reg): /soc/pwm@4002D000: simple-bus unit
address format error, expected "4002d000"
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
On i.mx6/7 the TCMU and TCML regions are specific to instruction or
data. So use the nxp,imx-itcm for TCML and nxp,imx-dtcm for TCMU.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The imx-rt-{i,d}tcm bindings can actually be utilized on the i.MX6/7 as
well for the TCM{L,U} regions of memory as they are specific to
instruction or data.
So let's rename imx-rt-{i,d}tcm to imx-{i,d}tcm.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Due to a bad timing in merging PR #10744 and PR #12083, the flash0 node
in stm32f756Xg.dtsi ended-up at the root of the device tree, while the
flash0 node it is trying to override in stm32f7.dtsi is now under
/soc/flash-controller.
This patch fixes that by moving it at the right location.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Added board definitions for nucleo_f756zg. Features include gpio,
pinmux, uart (ST Zio, ST-Link and Arduino Uno v3 interfaces).
Added basic documentation and some soc definitions for the
stm32 f756XX soc.
Signed-off-by: AJ Palmer <ajpcode@hotmail.com>
Adds a second sram node to the k64 device tree to acknowledge that the
additional sram is present in hardware, but deliberately not used in
zephyr until an outstanding issue is solved. The upper and lower sram
nodes are contiguous in the memory map, however the Cortex-M4
architecture does not support misaligned accesses across the boundary
between the two nodes.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This patch adds a flash driver for the STM32F7x series, inspired from
the STM32F4x one. It has been tested on the STM32F723, but should also
work on other SoCs of the family.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
We currently get a number of warnings like:
Warning (simple_bus_reg): /soc/otgfs_phy: missing or empty
reg/ranges property
This is due to the usb phy nodes not have a reg property since they
don't have an mmio address associated with them.
Move the phy nodes out of the SoC node so their lack of a reg property
will not cause a warning. This is similar to how Linux dts files
handle the phy nodes.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fix the following warning that shows up in some NRF device tree files:
Warning (simple_bus_reg): /soc/pwm@4001C000: simple-bus unit
address format error, expected "4001c000"
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
1. PWM device node added with alias to all
nRF52x DTSI files. 1 instance for
nRF52810, 3 instances for nRF52832, and
4 instance for nRF52840.
2. Added yaml binding for Nordic PWM node.
Signed-off-by: Gaute Gamnes <gaute.gamnes@nordicsemi.no>
Add comptiable into the device tree and associated binding files for NXP
i.MX RT ITCM/DTCM memory regions.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The STM32L433 has the same layout than the STM32L432, additionally it
has GPIOD, GPIOE, I2C2, USART3 and SPI2.
Also move USART3 and SPI2 out of stm32l4.dtsi since STM32L432 does not
have it.
Fixes#10909.
Signed-off-by: Markus Roppelt <markus.roppelt@gmx.de>
The Silicon Labs EFM32 Pearl Gecko MCU includes:
* Cortex-M4F core at 40MHz
* up to 1024KB of flash and 256KB of RAM
* multiple low power peripherals
Ported from EFM32WG:
https://www.silabs.com/documents/public/application-notes/an0918.0-efm32_to_efm32jgpg_migration_guide.pdf
Signed-off-by: Gil Benkö <gil.benkoe@pm.me>
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds the virtualcom device to the nrf52840 SoC dts and adds a board
specific nrf52840_overlay.dts file, copied exactly from the
arduino101_overlay.dts file, to set the console device name
appropriately for the subsys/usb/console sample project.
There were no clear alternatives to add a usb_cdc: virtualcom device to
all known SoC devices with USB support as should probably happen.
There was also no clear alternatives to add a non-board specific overlay
to the example.
This fixes a specific problem with the nrf52840-dk board for this sample
project.
Signed-off-by: Tom Burdick <thomas.burdick@gmail.com>
This commit adds support for STM32L471xG. Since STM32L475 only adds
USB, stm32l475.dtsi now includes stm32l471.dtsi
Signed-off-by: Kiril Zyapkov <k.zyapkov@allterco.com>
This patch adds a flash driver for the Atmel SAM E70 SoC. The driver has
been kept simple by considering that the flash is only composed of 8-KiB
blocks. Indeed an area at the beginning of the flash might be erased
with a smaller granularity, and the other blocks can also be erased with
a higher granularity. It also only handles the global read/write
protection, not the 128-KiB lock regions. A write error is returned if
a region is locked.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Enables Networking hardware on i.MX-RT type drivers.
Reuses the same eth_mcux driver used by Kinetis family; initialization
sequence refactored to work with this board as well. Unlike Kinetis
family, i.MX has a single ENET interrupt and we need to discriminate
between interrupts using a status register.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Add Messaging Unit B peripheral support for i.MX6SoloX soc so it can
use IMX IPM.
Origin: Original
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
dtc was producing this warning when we build on SAMD SoCs:
Warning (simple_bus_reg): /soc/nvmctrl@41004000:
simple-bus unit address format error, expected "40022000"
The reg addr isn't used by the flash_sam0.c driver so we wouldn't notice
this issue. Looking at the atmel HAL we see:
#define NVMCTRL ((Nvmctrl *)0x41004000UL)
So that provides confirmation of what the reg addr should be.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
STM32F103 micros starting from 64-pin (xE) packages upward have
available port G. This patch defines a dts binding for them.
Signed-off-by: Pavel Kral <pavel.kral@omsquare.com>
Add #pwm-cells to the i.MX PWM binding and dts files. This is to
support have a pwms clients work properly.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add #pwm-cells to the STM32 PWM binding and dts files. This is to
support have a pwms clients work properly.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Newer DTC now warns about mismatch between the reg and unit-address.
Most of these cases are due to case not matching, so fix thoses so
everything is lowercase.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The information extracted from the device tree is now used to initialize
GPIO device instances. Up until now the GPIO device driver made no use
of this information. Actual instance creation is still controlled using
the Kconfig method. Missing GPIO device tree nodes were added in the
process for STM32L073, STM32F413 and STM32F373.
The information for gpio instance initialization has already been
present for supported STM32 SoCs but remained unused. Changes in the
device tree had no effect on GPIO functionality and was essentially
redundant. Using the device tree for hardware description seems
plausible and less painful than a myriad of defines in some SoC
description header.
The change was implemented under the assumption that current device
trees provide a correct description of the SoCs. Base register addresses
and RCC register bits were not explicitly checked for each device.
Manual tests were executed on:
- NUCLEO-F103RB
- STM32F429I-DISCO
- STM32F746G-DISCO
- NUCLEO-F767ZI
Manual tests consisted of blinky on different GPIOs and pins on each
board.
sanitycheck was executed for all STM32 based boards
Fixes: #10629
Signed-off-by: Martin Bertsche <martin72216@googlemail.com>
Update stm32f469i_disco configuration to match with
default configuration guidelines:
-Configure available connectors
-Update yaml file
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update stm32l496g_disco configuration to match with
default configuration guidelines:
-Deactivate features by default
-Configure available connectors
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update disco_l475_iot1 configuration to match with
default configuration guidelines:
-Deactivate features by default
-Configure available connectors
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The only difference between the F413xH and F413xG is flash memory size.
STMF413xH: 1536 Kbytes
STMF413xG: 1024 Kbytes
Signed-off-by: Benoit Leforestier <benoit.leforestier@gmail.com>
This patch adds a USB device driver for the USBHS device that can be
found on Atmel SAM E70 SoC family. Only the FIFO mode is supported
(as opposed to DMA). It supports LS, FS and HS modes, but defaults to
FS mode as Zephyr does not fully support HS mode yet.
Tested examples on an Atmel SMART SAM E70 Xplained Board:
* usb/cdc_acm
* usb/hid-mouse
* usb/mass
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add clocks property in stm32l4r5 devices.
Replace i2c2 node by i2c3 node in l4.dtsi as i2c3 available
in all stm32l4 SoCs while i2c2 is not available in some parts.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add dts binding and info for TRNG device and enable basic support to
get the device name from DTS. We leave for now the base addresses
coming from the MCUX HAL.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add dts binding and info for RNGA device and enable basic support to
get the device name from DTS. We leave for now the base addresses
coming from the MCUX HAL.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add #pwm-cells properties to kinetis dts files and update the yaml
binding to spec the two cells as pin and period (in nanosecond to match
Linux Kernel binding spec).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert gpio_cc32xx driver over to using device tree. Added binding
files, updates to dts for various SoCs that use cc32xx.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adding watchdog driver for sam SoC. The current implemntation just
diables the watchdog on device boot.
This PR adds the following support for SAM3X, SAM4S and SAME70
1. Activate processor reset
2. Activate all reset
3. Generate interrupt on watchdog timer expiration.
Signed-off-by: Subramanian Meenakshi Sundaram <subbu147@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Silicon Labs EFR32MG12P Mighty Gecko MCU includes:
* Cortex-M4F core at 40MHz
* up to 1024KB of flash and 256KB of RAM
* integrated Sub-GHz and/or 2.4GHz radio
* multiple low power peripherals
Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
Signed-off-by: Endre Karlson <endre.karslon@gmail.com>
Partially replaces Kinetis MCUX driver configuration from Kconfig to
Device Tree. Interrputs moved from defines configuration to DT.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Introduces the location property and adds the ability to use values
generated by the device tree configuration.
Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add I2S bus initial support to stm32f4 SOC family.
On stm32f4 the I2S shares same controller as SPI, so
the declarations have been adapted from SPI ones.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The Silicon Labs EFM32 Happy Gecko MCU includes:
* Cortex-M0+ core at 24MHz
* Up to 64KB of flash and 8KB of RAM
* Full speed (12 MHz) USB 2.0 Device
* Multiple low power peripherals
Signed-off-by: Marcio Montenegro <mtuxpe@gmail.com>
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Convert gpio_gecko driver over to using device tree. Added binding
files, updates to dts for various SoCs that use gpio_gecko.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add maximum-speed property to usb nodes and set it to
their maximum on-chip PHY capability.
SoCs with USB device controllers only support full
speed, so we don't add maximum-speed to these nodes.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
The gpio controllers on SAM4S, SAME70, and SAMD were missing properties
related to GPIO pin generation. Add the missing details into the yaml
and dts files to allow boards to specific gpio pins.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
added sam4s16b, sam4s8c, sam4s8b, sam4s4c, sam4s4b,
sam4s4a, sam4s2c, sam4s2b and sam4s2a.
Used the same order as in the data sheet and code structure
equal to same70. Updated the sam4s_xplained board to match
the altered .dtsi location of the specific SoC.
Signed-off-by: Vincent van der Locht <vincent@vlotech.nl>
This patch adds timers and PWM nodes to STM32 F7 series, as well as the
corresponding dts fixup entries.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Now that we've cleaned up all the STM32 related .dtsi files we don't
use dts/arm/st/mem.h so we can remove it.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
To move forward and remove use of Kconfig in dts files lets just create
SoC specific dtsi files that the boards can include. We also seperate
out the F7 dtsi files into their own dir.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
To move forward and remove use of Kconfig in dts files lets just create
SoC specific dtsi files that the boards can include. We also seperate
out the F4 dtsi files into their own dir.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
To move forward and remove use of Kconfig in dts files lets just create
SoC specific dtsi files that the boards can include. We also seperate
out the F3 dtsi files into their own dir.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
To move forward and remove use of Kconfig in dts files lets just create
SoC specific dtsi files that the boards can include. We also seperate
out the F2 dtsi files into their own dir.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
To move forward and remove use of Kconfig in dts files lets just create
SoC specific dtsi files that the boards can include. We also seperate
out the L4 dtsi files into their own dir.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
To move forward and remove use of Kconfig in dts files lets just create
SoC specific dtsi files that the boards can include. We also seperate
out the L0 dtsi files into their own dir.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
To move forward and remove use of Kconfig in dts files lets just create
SoC specific dtsi files that the boards can include. We also seperate
out the F1 dtsi files into their own dir.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
To move forward and remove use of Kconfig in dts files lets just create
SoC specific dtsi files that the boards can include. We also seperate
out the F0 dtsi files into their own dir.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Added initial support and created the corresponding device tree part for
building PSoC6 SoC as part of Zephyr.
Signed-off-by: Nazar Chornenkyy <nazar.chornenkyy@cypress.com>
Signed-off-by: Oleg Kapshii <oleg.kapshii@cypress.com>
Commit introduces support for ARM TrustZone CryptoCell 310
for Nordic Semiconductor nRF SoCs in device tree.
Signed-off-by: Dominik Kilian <Dominik.Kilian@nordicsemi.no>
Flash controller-node for stm32f2 based SoCs was missing basic
properties such as compatible, labeln reg and interrupts.
Fix this and add matching yaml binding file;
Fixes#10057
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
When we fixed the missing reg property in the cpu node, we forgot to
add #address-cells & #size-cells for the node.
This fix the following warnings we get:
Warning (reg_format): "reg" property in /cpus/cpu@0 has invalid
length (4 bytes) (#address-cells == 2, #size-cells == 1)
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This change aims at fixing 'unit_address_vs_reg' warning in
stm32 *-pinctrl.dtsi files.
This warning pops up when a node name is made up with an address
(node_name@xx) but does not contain a reg property.
This case was encountered for led nodes for instance,
where a reg property has no meaning.
Fix this by changing node_name@xx to node_name_xx which removes the
guilty '@xx' syntax but preserves node_name uniqueness.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
We get several warnings of the form:
Warning (unit_address_vs_reg): /flash: node has a reg or ranges
property, but no unit name
or
Warning (unit_address_vs_reg): /memory: node has a reg or ranges
property, but no unit name
Fix by adding unit address that is missing to flash & memory nodes.
Additionally the Silabs memory nodes didn't have a compatiable or
device_type, so add those properties as well.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We get several warnings of the form:
Warning (unit_address_vs_reg): /cpus/cpu@0: node has a
unit name, but no reg property
Fix by adding reg property to missing cpu nodes.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
To move forward and remove use of Kconfig in dts files lets just create
SoC specific dtsi files that the boards can include. This lets us
remove:
CONFIG_SOC_NRF51822_QFAA
CONFIG_SOC_NRF51822_QFAB
CONFIG_SOC_NRF51822_QFAC
CONFIG_SOC_NRF52810_QFAA
CONFIG_SOC_NRF52832_QFAA
CONFIG_SOC_NRF52832_CIAA
CONFIG_SOC_NRF52832_QFAB
CONFIG_SOC_NRF52840_QIAA
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
To move forward and remove use of Kconfig in dts files lets just create
SoC specific dtsi files that the boards can include. This lets us
remove:
CONFIG_SOC_PART_NUMBER_SAME70*
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we have a common DT_SIZE_K macro use it instead of defining
__SIZE_K eveywhere. We also have DT_SIZE_M, so use that in a few
places as well.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The RTC node for some reason was setting #address-cells and #size-cells.
However it has no children so there isn't really any reason to do this.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In case of out of tree SoC, mem.h will trigger and error since
it is not aware of new SoC CONFIG_SOC_<reference>.
Modify error condition in order to generate the error only if
the flash and error size are not defined at this point (even in
out of tree case).
Fixes#9978
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To move forward and remove use of Kconfig in dts files lets just create
SoC specific dtsi files that the boards can include. This lets us
remove:
CONFIG_SOC_PART_NUMBER_EFM32WG990F256
CONFIG_SOC_PART_NUMBER_EFR32FG1P133F256GM48
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
To move forward and remove use of Kconfig in dts files lets just create
SoC specific dtsi files that the boards can include. This lets us
remove:
CONFIG_SOC_CC3220SF
CONFIG_SOC_MSP432P401R
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The LEDs, buttons and necessary aliases are now configured via dts.
This commit breaks the sample under samples/boards/nrf52/power_mgr.
Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
According to Device Tree specification, previously
defined nodes may be deleted with the followin
syntax:
/delete-node/ node-name;
or
/delete-node/ &label;
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
This change adds DTS definition of SPI device for nRF chips.
It also removes SPI pin configuration from Kconfig and moves it to
chip DTS.
Signed-off-by: Filip Kubicz <filip.kubicz@nordicsemi.no>
This commit adds ADC nodes to DTS files for nRF SoCs and introduces
corresponding bindings for these nodes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The whole STM32L4 family has a flash with a constant page size of 2kB.
Specify this value in the DTS as the nvs sample application pull it
from there.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The nvs sample assumed a 1 KB flash erase block size, which caused the
sample to fail on frdm_k64f because its erase block size is 4 KB. Get
the erase block size from dts instead.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add support for usbotg_fs, by adding the DT fixup, pinmux macros,
and the DT entries in stm32f2.dtsi.
Signed-off-by: Istvan Bisz <istvan.bisz@t-online.hu>
The L433 chip is a superset of the L432, just grabbing a few additional
interfaces (LCD, I2C2, USART3, SPI2, SDMMC). All the support/HAL files
are already there, so enabling these is just a matter of build system
setup.
Tested on an application specific board (builds correctly and I2C2
works.) I unfortunately don't have a nucleo/discovery board to create a
reference board for.
Signed-off-by: David Lamparter <equinox@diac24.net>
This patch adds the RDC (Resource Domain Controller) peripheral
permissions settings for the i.MX applications cores (Cortex A9 on
i.MX6 and Cortex A7 on i.MX7).
This will enable both Linux (on application's core) and Zephyr (on M4
core) to share the peripherals and coexist.
The settings are defined at devicetree level and applied in the soc.c.
A complete solution should involve the SEMA4 to control the peripherals
access and prevent resource deadlocking and misusage.
Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
The STM32F7 uses the V2 version of the STM32 I2C controller. Add the
corresponding Kconfig, DTS, DTS fixup and pinmux entries.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit adds support for the nrf52840_pca10059 board.
The flash partitions are configured to allow migrating from
the stock bootloader to MCUBoot.
Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
The STM32F7 uses the same USB OTG FS controller than the STM32F4 series.
It is therefore trivial to add support for it, by adding the DT fixup
and pinmux macros, and the DT entries in stm32f7.dtsi. Keep it disabled,
it should be enabled at the board level.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
samd21.dtsi includes now the same content need for SAMD20,
move it to samd.dtsi and include it from samd21.dtsi.
Then later USB support can be added to the samd21.dtsi seperatly
from the samd20 etc.
Signed-off-by: Sean Nyekjaer <sean@nyekjaer.dk>
The EFR32 Flex Gecko Wireless Starter Kit contains sensors and
peripherals demonstarting the usage of the EFR32FG1P SoC
family. This patch add basic support for this board.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Since the UART0 @ 0x40002000 can either be UART or UARTE the user of the
soc.dtsi needs to select either compatible = "nordic,nrf-uarte" or
"nordic,nrf-uart"
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The STM32F769 has more interrupts and features than the STM32F746,
but the basic support is similar with STM32F746
Signed-off-by: Yong Jin <jinyong.iot@foxmail.com>
clear RXNE flag in fifo_read, remove TEACK and REACK
check when uart_stm32_init because stm32f2 doesn't
has those flags.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
The STM32F723 has more interrupts than the STM32F746 due to the
additional SDMMC controller. Besides that the changes are very
similar to the ones of the STM32F746.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This patch includes:
STM32F7 family device tree file with basic and UART definitions.
STM32F746 subfamily device tree file.
Memory definitions for STM32F746xG subfamily.
Signed-off-by: Yurii Hamann <yurii@hamann.site>
STM32F412/413/446/469 SoCs have 6 bidirectional endpoints
according to the reference manuals RM0402, RM0430,
RM0390 and RM0386.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
This commit moves the definitions for the LED and Buttons
supported in nrf52810_pca10040 DK in DTS from board.h. Aliases
are kept in board.h to make basic examples pass.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The nRF52810 is a low-cost variant of the nRF52832, with a reduced set
of peripherals and memory. This commit adds basic support for it in the
arch SoC and dts folders.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Ioannis Glaropoulos <ioannis.glaropoulos@nordicsemi.no>
The i.MX 6SoloX SoC is a hybrid multi-core processor composed by one
Cortex A9 core and one Cortex M4 core.
Zephyr was ported to run on the M4 core. In a later release, it will
also communicate with the A9 core (running Linux) via RPMsg.
The low level drivers come from NXP FreeRTOS BSP and are located at
ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README
The A9 core is responsible to load the M4 binary application into the
RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer,
and get the M4 out of reset.
The A9 can perform these steps at bootloader level after the Linux
system has booted.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
The various STM32 reference manuals sometimes define the USB endpoints
as IN or OUT only and sometimes as bidirectional, even in the same
manual. This is likely because the OTG implementation has one set of
registers for the IN endpoints and one other set for OUT endpoints.
However at the end a given endpoint address can both transmit and
receive data.
This causes some confusion how to declare the endpoints in the device
tree, and depending on the SoC, they are either the same number of IN
and OUT endpoints declared, or they are declared as bidirectional. At
the end it doesn't really matter given how the driver uses those values:
#define NUM_IN_EP (CONFIG_USB_NUM_BIDIR_ENDPOINTS + \
CONFIG_USB_NUM_IN_ENDPOINTS)
#define NUM_OUT_EP (CONFIG_USB_NUM_BIDIR_ENDPOINTS + \
CONFIG_USB_NUM_OUT_ENDPOINTS)
#define NUM_BIDIR_EP NUM_OUT_EP
This patch therefore cleanup the driver, the DTS, and the DTS fixups to
only define the number of bidirectional endpoints.
In addition to the cleanup, that fixes a regression introduced by commit
52eacf16a2 ("driver: usb: add check for endpoint capabilities"), which
introduced a wrong check for SoC only defining the number of
bidirectional endpoints.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit enables CAN on the STM32L432.
Tested on nucleo l432ck with external transceiver and loopback mode.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
This commit splits the common interrupt into rx and tx parts because
only STM32F0 series has a common interrupt.
Moved clock source definition to device-tree.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
The prepended 0x causes DTC warnings and shouldn't be there.
Tested by compiling hello_world for nrf52840_pca10056 before and after.
Fixes#8334.
Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
This adds basic support for declaring gpio nodes in dts for nrf52.
The dts.fixup provides mapping for the generated defines to the config
defines currently used by the nrf gpio driver.
Existing boards that use nrf52 are updated.
Signed-off-by: Marc Reilly <marc@cpdesign.com.au>
This commit moves the bit timing (PROP, BS1, BS2 segments and SWJ)
from Kconfig to the device-tree and fixes issue #7933
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
Enable supporting UART4 on STM32F107 and STM32F103Xe SoCs.
Modified stm32f1/dts.fixup for replacing USART with UART.
Signed-off-by: Jun Li <jun.r.li@intel.com>
LPUART (Low-power UART) peripheral is just like ordinary U(S)ART
which lives in a separate clock/power domain.
Therefore already existing code could be reused as is
almost entirely.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
The STM32L432 SoC has a standard non-OTG USB controller. Add an entry
for it in stm32l432.dtsi and add the corresponding DTS fixup entries.
The controller is kept disabled and should be enabled at the board
level.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
USB OTG is currently enable for the whole STM32L4 family, while only a
few of them actually support it:
- STM32L475, STM32L476 and STM32L496 have an OTG controller
- STM32L432, STM32L433 and STM32L452 have an USB controller
- STM32L431, STM32L451 and STM32L471 do not have any USB controller
Fix that by moving the DT entry from stm32l4.dtsi to stm32l475.dtsi
and by adding a #ifdef #endif around the corresponding DTS fixup
entries.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add driver for MCUX mailbox which can be used for lpcxpresso54114
and other lpc and kinetis socs.
Origin: Original
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Add soc configuration support and dts files for nxp_lpc54xxx_m0.
Adjusted nxp_lpc54xxx soc, configuration and dts files for the
presence of slave core.
Origin: Original
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds dts bindings for the kinetis watchdog peripheral, and updates the
watchdog nodes for the k64 and kw2xd socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This patch adds some DTS information to flesh out the NXP Kinetis
based RTC blocks. DTS fixups were added as well to match up the driver
usage to the DTS output.
Signed-off-by: Andy Gross <agross@kernel.org>
Rename various SoC related defines and files from just being LPC54114
to LPC54114_M4. This is in prep for supporting a build for the second
core on the LPC54114 (the Cortex-M0+).
* Renamed Kconfig SOC_LPC54114 to SOC_LPC54114_M4
* Renamed Kconfig.defconfig.lpc54114 to Kconfig.defconfig.lpc54114_m4
* Introduced nxp_lpc54xxx_m4.dtsi based on nxp_lpc54xxx.dtsi
* Moved some pinmux related defines into SoC code.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
- Changed define for SETTINGS_CONFIG_PAGE_SIZE from a hard coded value
to reference build system generated FLASH_ERASE_BLOCK_SIZE. This value
comes from 'erase-block-size' found in the dtsi file of devices.
- Modified nrf52840.dtsi to include definition for 'erase-block-size'
Fixes#7107
Signed-off-by: David Leach <david.leach@nxp.com>
Commit introduces support for watchdog configuration for Nordic
Semiconductor nRF SoCs in device tree.
Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
Adds dts bindings for the mcr20a wireless transceiver. The frdm_k64f
board supports the mcr20a via an Arduino shield, therefore the dts node
is added to the board dts. The kw2xd is a SiP and thus the mcr20a dts
node is added to the soc dts.
The networking samples using prj_frdm_k64f_mcr20a.conf have been broken
since the refactoring of the mcux gpio driver to dts in commit
4e8f29f319. The sample is now fixed.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds dts spi bindings for the kinetis dspi controller, and updates the
k64, kw2xd, kw40z, kw41z dts nodes accordingly.
Updates the dts interrupt priorities to match the board defconfigs
(e.g., boards/arm/frdm_k64f/Kconfig.defconfig)
For k64, fixes an error in the spi1 interrupt number and adds a third
instance (spi2).
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds flexspi and semc memory controllers to the i.MX RT SoC. Adds
hyperflash, qspi, and sdram external memories to the mimxrt1050_evk
board.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Previously, when !CONFI_XIP, BOOTLOADER_SRAM_SIZE was defaulted
to 16 (K), reducing the size of SRAM available for the program.
Also, though it has no effect, the value for SRAM start in the
dtsi file was incorrect.
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
To prepare to upcoming dtc v1.4.6, fix warnings in dts files.
This commit addresses the following warning:
Warning (unit_address_vs_reg): Node /soc/pin-controller has a reg
or ranges property, but no unit name
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To prepare to upcoming dtc v1.4.6, fix warnings in dts files.
This commit addresses the following warning:
Warning (clocks_property): Missing property '#clock-cells' in node
/soc/rcc@40021000 or bad phandle (referred from
/soc/pin-controller/gpio@40011800:clocks[0])
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Adds gpio labels to all kinetis socs in preparation for refactoring the
mcux gpio driver to dts. The kl25z was missing gpio nodes altogether, so
they are added.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Create a dt-bindings/gpio.h file.
Bindings definitions are extracted from existing gpio.h.
gpio dt-bindings file is required because existing gpio.h file could
not be parsed by dts parser.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual
Cortex A7 core and Single Cortex M4 core.
Zephyr was ported to run on the M4 core. In a later release, it will
also communicate with the A7 core (running Linux) via RPmsg.
The low level drivers come from NXP FreeRTOS BSP and are located at
ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README
The A7 core is responsible to load the M4 binary application into the
RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer,
and get the M4 out of reset.
The A7 can perform these steps at bootloader level after the Linux
system has booted.
The M4 can use up to 5 different RAMs. These are the memory mapping for
A7 and M4:
+---------------+-----------------+---------------------------+
| Memory Name | Start Address | Size |
+===============+=================+===========================+
| TCML | 0x007F8000 | 32KB |
+---------------+-----------------+---------------------------+
| TCMU | 0x20000000 | 32KB |
+---------------+-----------------+---------------------------+
| OCRAM_S | 0x20180000 | 32KB |
+---------------+-----------------+---------------------------+
| OCRAM | 0x00900000 | 128KB |
+---------------+-----------------+---------------------------+
| DDR | 0x10000000 | 256MB |
+---------------+-----------------+---------------------------+
Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
With upcoming ICs that are not in the nRF5x family, rename the flash
driver and all its dependencies from nrf5 to nrf.
Should also fix the issue introduced by f49150cab6 which broke the
assignment of the flash device due to a partial rename.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add initial support for STM32L073xZ SOC which is not very different
from already supported STM32L072xZ.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
Since not all boards enable all devices, we typically have the SoC dtsi
file have a device marked with status = "disabled" and have the
board.dts explicitly enable with status = "ok". Update it so USB on
Atmel SAMD21 work this way.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Switch the SoC device tree to define a single entry per SERCOM instead
of one per mode.
Define a Device Tree binding for the SAM0 SPI and use it instead of
Kconfig for enabling / disabaling instances
Switch the Arduino Zero, Adafruit Feather M0 Basic Proto, and
Trinket M0 to use the new defintion.
Add the APA102 LED that's on the Trinket as a test.
Signed-off-by: Michael Hope <mlhx@google.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Implements interrupt driven UART for the serial driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Justin Watson <jwatson5@gmail.com>
The spi nodes should have #address-cells and #size-cells properties much
like i2c does. Add these missing properties.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Most STM32F429 SoCs have 6 SPIs, but STM32F429Vx SoCs only have
4 SPIs. This is one of the rare conditions where device-tree
directive /delete-node/ should be used.
Add spi5 and spi6 node to stm32f429.dtsi. Create file
stm32f429vX.dtsi to delete those nodes and document usage of
/delete-node/ directive.
Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
Some stm32f4 SoCs don't support spi2, so remove spi2
device-tree node from stm32f4.dtsi file.
Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
stm32f405 is not an expansion of stm32f411, since stm32f411 has more
SPIs than stm32f405.
Fix this by including stm32f401.dtsi in stm32f405.dtsi
(instead of stm32f411.dtsi).
Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
Configure ccm size and address via dts. According to the DT
specification, the unit-address of a node must match the
first address specified in the reg property of the node.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
stm32f334 is not an expansion of stm32f303, since
stm32f303 has more I2C, SPI ports than stm32f303.
Fix this by including stm32f3.dtsi in stm32f334.dtsi.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
This PR includes the required changes in order to support
conditional compilation for Armv8-M architecture. Two
variants of the Armv8-M architecture are defined:
- the Armv8-M Baseline (backwards compatible with ARMv6-M),
- the Armv8-M Mainline (backwards compatible with ARMv7-M).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Pin multiplexing is a function of the PORT peripheral. This change
defines a separate pinmux device at the same address as the PORTs
themselves.
Signed-off-by: Michael Hope <mlhx@google.com>
Adds a new optional dts property to define the erase block size of a
flash device. This will be used by the mcux flash driver to implement
the flash page layout function.
The value is set for all kinetis devices to match
FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add device tree support for the "nxp,kinetis-ftfa" flash controller used
on the NXP KL2X and KW4xZ SoCs.
Fixes: #5788
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert NXP k6x and kw2xd flash driver to use device tree to get the
flash controller name from device tree. We introduce yaml bindings for
the "nxp,kinetis-ftfe" and "nxp,kinetis-ftfl" devices.
Fixes: #5788
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
On the various NXP Kinetis SoCs add the write-block-size property and
set it to match FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE for the
given SoC.
Fixes: #5788
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert Atmel SAM0 flash driver to use device tree to get the flash
controller name and base address.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Introduce flash controller nodes for STM32 SoCs that are supported in
the flash driver. This is a precusor to converting the flash driver on
stm32 over to using device tree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
So far, DT did not support the flash driver name.
Any flash-controller should have the appropriate
flash driver that should be identified by its name.
This path adds generic support for extract the description
from the flash-controller node,
adds implementation of this property for all nrf5x targets.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Where missing add compatible = "soc-nv-flash". Also added a label for
all the soc-nv-flash that we might use in the future.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commits adds the "least common denominator" in the
stm32fX.dtsi files and fills the additional SPI nodes
in stm32fXYZ.dtsi files, only for the SOCs where boards
use the additional SPI peripheral.
We could add the rest SPI nodes in the stm32fXYZ.dtsi
files when we add SPI support to other boards.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
The SAM0 has a 64 byte page (the programing unit) with 4 pages to a
row (the erase unit). This driver implements a read/modify/write to
emulate the byte level writes used by NFFS.
Signed-off-by: Michael Hope <mlhx@google.com>
This was validated on the cc3220sf_launchxl board
using the Zephyr thermometer sample program
adapted to call the i2c driver directly, and fetching
samples from the on-board TMP006 temperature sensor.
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Add configuration, pinmux, dts and documentation for the STM32L476G
Discovery board based on the STM32L476VG SoC.
Signed-off-by: Arthur SFEZ <arthur.sfez@gmail.com>
Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and
series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core,
512 KB TCM, and many peripherals including 2D graphics, an LCD display
controller, camera interface, SPDIF and I2S. Unlike other SoCs in
Zephyr, the mimxrt1052 has no internal flash.
This initial port to mimxrt1052 configures the system clock to operate
at 528 MHz, and enables the serial/uart and gpio interfaces to support
the hello_world and blinky samples. Support for additional Zephyr driver
interfaces will come later.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Move the dts files into the board dir so that board ports can be more
standalone. This will allow us at some point to have board ports
outside of the tree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move the dts fixup files into the board dir so that board ports can be
more standalone. This will allow us at some point to have board ports
outside of the tree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
If DTS does not depend on include paths determined in /ext then we can
move dts next to kconfig. Moving it next to kconfig means that DTS
CONFIG_ variables will be available at the same time as kconfig's
CONFIG_ variables which is the intended design and beneficial from a
usability perspective.
Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
Boot serial recovery feature consume additional
memory size so the mcuboot partition must been
expanded on cost of images partitions.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Boot serial recovery feature consume additional
memory size so the mcuboot partition must been
expanded on cost of images partitions.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Add board configuration, dts and pinmux, based on
arm/stm32f4_disco and arm/nucleo_f411re boards.
Error free tests are executed on eval board with the following
sample applications:
- hello_world
- blinky-sample
- button-sample
- console_echo_sample
- console_getchar_sample
Signed-off-by: Jose F. Fernandez <jffernandez@fenix-es.com>
Moved yaml files to be under dts/bindings and have the bindings try
and match the linux doc device tree binding dir structure as the
canonical binding reference.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Added I2C bus (TWI) driver for Atmel SAM MCU family. Only
I2C Master Mode with 7 bit addressing is currently supported.
Tested on Arduino Due board.
Origin: Original
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Adds device tree bindings for the Kinetis System Integration Module
(SIM), and defines peripheral source clocks (e.g., system clock or bus
clock) and clock gates for all Kinetis SoCs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This patch adds support for TI Simplelink MSP-EXP432P401R-LAUNCHXL
development board based on Cortex M4 family
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch adds support for on board UART_0 on MSP-EXP432P401R-LAUNCHXL.
Driver makes use of driverlib available in ROM by default, thus saving
code space.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
The EFM32 Wonder Gecko Starter Kit contains sensors and
peripherals demonstarting the usage of the EFM32WG MCU
family. This patch add basic support for this board.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Silicon Labs EFM32 Wonder Gecko MCU includes:
* Cortex-M4F core at 48MHz
* up to 256KB of flash and 32KB of RAM
* USB with host and OTG support
* multiple low power peripherals
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
stm32f407 SoC is an extension of stm32f405 SoC with additional
support of ethernet and DCMI. Hence, in dts description, this
should be represented by stm32f407.dtsi including stm32f405.dtsi.
The opposite was proposed today in stm32 .dtsi files.
This commit fixes the inclusion model and renames
stm32f407-pinctrl.dtsi into stm32f405-pinctrl.dtsi
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This makes the SoC flash compatible with the common nonvolatile flash
YAML schema, and provides a write alignment. It mirrors work done on
nRF chips for the DFU subsystem.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
This makes the SoC flash compatible with the common nonvolatile flash
YAML schema, and provides a write alignment. It mirrors work done on
nRF chips for the DFU subsystem.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
This makes the SoC flash compatible with the common nonvolatile flash
YAML schema, and provides a write alignment. It mirrors work done on
nRF chips for the DFU subsystem.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
This patch adds partition for NFFS for nRF51, nRF52 and nRF52840.
The partition is placed at the end of flash. This is only added if NFFS
is enabled (since it's required) - in other case free space can be used
for other purposes.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Similar addition was don previous for nRF52840.
Added flash-controller description and moved flash description to
it. Added property for description of
the flash alignment required by write operations.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Similar addition was don previous for nRF52840.
Added flash-controller description and moved flash description to
it. Added property for description of
the flash alignment required by write operations.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Remove usart2_pins_b as this configuration is not possible
(PA15 could not be mapped on USART2).
Besides usart2_pins_c as this configuration is not used yet,
remove to reserve "usart2_pins_c" for future use
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Default configuration for USART1 (Console output) on board
stm32f3_disco was set on PA9/PA10, which matches Rev-A/B
configuration. Though, on more recent configuration of the
board (Rev-C onward). USART1 is mapped to PC4/PC5.
This configuration has the benefit to support VCP, hence it
is chosen to be set by default.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add board configuration, dts and pinmux based on both
stm32f469i_disco board and nucleo_f412zg board
Signed-off-by: Massimiliano Cialdi <massimiliano.cialdi@powersoft.it>
Fixes uart irq info in the device tree fixup files for frdm_k64f and
hexiwear_k64. They were incorrect in uart instance 5.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This patch enables I2C_2 support for 96b_carbon. Without
this patch, trying to build I2C_2 will result in build
error.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Added flash-controller description and moved flash description to
it (for coherence). Added property for description of
the flash alignment required by write operations.
Thanks to that l-value FLASH_WRITE_BLOCK_SIZE macro
will be generated. It is useful for any component uses
the flash.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
We use UART1 for UART pipe in a number of qemu tests, so lets do the
same thing for the bluetooth test and move the bluetooth uart to UART2.
Jira: ZEP-2412.
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Stop using CONFIG_I2C_x_DEFAULT_CFG to get the initial value. Since we
only support master mode we always default to it for initial config and
we get the bitrate from the device tree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Stop using CONFIG_I2C_x_DEFAULT_CFG to get the initial value. Since we
only support master mode we always default to it for initial config and
we get the bitrate from the device tree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Per ZEP-1958, Phase 2 of adding CC3220sf LaunchXL support,
was to "deprecate the CC3200 launchxl support in Zephyr
(redundant to the CC3220)."
Effectively, the CC3220 SOC replaces the CC3200.
This patch removes the following:
* the imported CC3200 SDK
* CC3200 SOC, board, DTS files.
* adjusts other files where cc3200 was mentioned.
Also, it fixes explicit references to CC3200 in generic
CC32xx driver files.
Jira: ZEP-1958
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
pin-controller reg is already set in stm32f407.dtsi which we include in
stm32f469.dtsi so no need to set it again.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds common and Kinetis-specific pwm device tree properties, and updates
the k64 SoC and board dts files to include all four pwm nodes.
Jira: ZEP-2025
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
- board name olimex_stm32_p405
- CPU STM32F405RGT6 Cortex M4
- LED/BUTTON support
- Console on USART2 with 8n1 115200 baud
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
The API name space for Bluetooth is bt_* and BT_* so it makes sense to
align the Kconfig name space with this. The additional benefit is that
this also makes the names shorter. It is also in line with what Linux
uses for Bluetooth Kconfig entries.
Some Bluetooth-related Networking Kconfig defines are renamed as well
in order to be consistent, such as NET_L2_BLUETOOTH.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Move to using the generated IRQ defines from the DTS instead of soc.h.
This change also fixes a minor bug in that the error irq priority wasn't
getting correctly picked up from device tree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add needed uart pinctrl configuration in pinmux node.
Populate stm32 f1 based boards dts files with references
to uart pinctrl nodes
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add needed uart pinctrl configuration in pinmux node.
This is done thanks to <soc>-pinctrl.dtsi file matching
<soc>.dtsi files
Populate stm32 f3 based boards dts files with references
to uart pinctrl nodes
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add needed uart pinctrl configuration in pinmux node.
This is done thanks to <soc>-pinctrl.dtsi file matching
the <soc>.dtsi files
Populate stm32 f4 based boards dts files with references
to uart pinctrl nodes.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add pinctrl node on stm32l4 soc dts files, including uart
pinctrl configurations. This is done thanks to <soc>-pinctrl.dtsi
file matching the <soc>.dtsi file
Populate stm32 l4 based boards dts files with references
to uart pinctrl nodes
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add pinmux yaml file and bindings before introduction
of pinmux node in stm32 soc device tree files
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
When we introduced I2C DTS support on hexiwear_kw40z we got it wrong.
Its I2C1 not I2C0 that was being used on the hexiwear. Fix the dts and
fixup file to reflect that.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Update the I2C defines in fixup files after the introduction
of cell prefix to interrupts-names generated defines
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Now that we generate BLUETOOTH_UART_ON_DEV_NAME, UART_PIPE_ON_DEV_NAME,
and BLUETOOTH_MONITOR_ON_DEV_NAME Kconfig defines for dts enabled
platforms add those into the appropriate dts files and remove from the
various board/Kconfig.defconfig files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In order to simplify maintenance of dts files for
stm32f4 series, introduce a stm32l4.dtsi file which
represent the smallest common denominator of IPs in
the family.
This allows to fix usart4 availability on stm32l432
which was not correct.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to simplify maintenance of dts files for
stm32f1 series, introduce a stm32f3.dtsi file which
represent the smallest common denominator of IPs in
the family.
Besides, stm32f334 includes stm32f303, as it is a
extension of this SoC.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to simplify maintenance of dts files for
stm32f1 series, introduce a stm32f1.dtsi file which
represent the smallest common denominator of IPs in
the family.
Besides, stm32f103Xe includes stm32f103xb, as it is a
extension of this SoC.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add "clocks" property on u(s)arts nodes on stm32 socs
Add a dt clocks binding file and rework clock_control
header file include new device tree binding file.
include/dt-bindings folder is introduced as dt-bindings
placeholder
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove memory node from skeleton dtsi and add device_type
property in every memory node in soc dtsi files
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
This patch add the unit-address component to memory and flash
nodes. According to the DT specification, the unit-address of
a node must match the first address specified in the reg
property of the node.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Remove all explicitly defined application state partition child nodes
from DTS flash nodes, in favor of comments noting that they are
reserved for use by the application.
This follows the pattern established in f58b36a ("dts: frdm_k64f: make
application state partition a reserved area"), and fixes an error
introduced in 9f7f83d2 ("dts: 96b_nitrogen: add flash partitions"),
which added both a reserved area comment and an explicit partition
node to 96b_nitrogen's dts.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Remove compatible = "flash" from any node that has it as this doesn't
have any well defined meaning right now. Also update any compatible =
"sram" to be "mmio-sram" (as there's a binding in linux for this).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Update the MCUX I2C driver and related platforms to get their I2C
information from the device tree. We also updated a few of the sensor
drivers found on the FRDM & Hexiwear boards to get their I2C bus name
from the device tree instead of directly from Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch adds #address-cell, #size-cell properties to
cpus container node and device_type, reg properties to
cpu node.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Adds common and Kinetis-specific adc device tree properties, and updates
all Kinetis SoC and board dts files to include adc nodes.
Jira: ZEP-1396
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
patch adds zephyr,uart-pipe to devie tree as chosen property.
This is added for frdmk64f because sanitycheck test was
breaking with changes of generating configs for UART_PIPE
from device tree instead of Kconfig.
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
A number of sectors are declared in the frdm_k64f flash partitions
node as part of an "application state" partition. Rather than require
users to treat this area of flash as a single partition, delete the
application-state node and leave a comment in its place describing its
purpose.
This enables use cases where the flash sectors must be split into
multiple partitions without defining overlapping partitions in overlay
files.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Currently, flash partitions used by mcuboot are defined in the
SoC-level dtsi file for NXP K6X. This should be made more granular so
that product owners can choose partition layouts to suit their
needs. To that end, move the partitions into frdm_k64f.dts.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
The I2C controller nodes are the root of the I2C bus for that controller
and thus may have children nodes that represent the I2C devices on that
controller. Thus we need to specify the #address-cell & #size-cell
properties.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
+ The VBLUno52 board
nRF52832 ARM Cortex-M4F processor
Bluetooth Low Energy 5.0
DAPLink interface
UNO pinout
4 power
+ The following samples were tested:
hello_world
basic/button
basic/blinky
bluetooth/peripheral_hr
bluetooth/beacon
Signed-off-by: Nam Do <robotden@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Since we support uart0 on the cc2650 sensortag we should have a
reference for zephyr,console in chosen for it. This will be useful as
we start to generate Kconfig defines based on zephyr,console.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Configure I2C using DT for the following STM32 boards:
disco_l475_iot1
nucleo_f401re
96b_carbon
olimexino_stm32
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
The SAM4S, SAM3X, SAME70 all use the uart_sam.c serial
driver. This patch puts the configuration in DTS and
out of Kconfig. The SAME70 uses the USART as well.
USART DTS support for the SAME70 is also in this patch.
Signed-off-by: Justin Watson <jwatson5@gmail.com>
+ VBLUno51 board
nRF51822
Bluetooth Low Energy
DAPLink interface
UNO pinout
4 power
+ Wiki: https://vngiotlab.github.io/vbluno/
+ The following samples were tested:
hello_world
basic/button
basic/blinky
bluetooth/peripheral_hr
bluetooth/beacon
Signed-off-by: Nam Do <robotden@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
With this partition: mcuboot up to 64KB, user app up to 432KB, an
application state of 64KB, and a swap sector of 24KB.
Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
Renames k64sim to nxp,k64f-sim to be more consistent with other files.
The sim hardware can vary across Kinetis SoCs, so this dts is not made
to be generic.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Multiple Kinetis SoCs have the same gpio hardware as the k64 and can use
the same mcux driver, so rename the dts to be more generic.
Also fixes some stranded references to kw41z-gpio to the new
kinetis-gpio.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Multiple Kinetis SoCs have the same pinmux hardware as the k64 and can
use the same mcux driver, so rename the dts to be more generic.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Multiple Kinetis SoCs have the same lpuart hardware as the kw41z and can
use the same mcux driver, so rename the dts to be more generic.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Multiple Kinetis SoCs have the same uart hardware as the k64 and can use
the same mcux driver, so rename the dts to be more generic.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add configuration, documentation, pinmux, fixup and dts support for
STM32F103x8 based Minimum System Development board.
Signed-off-by: Siddharth Chandrasekaran <siddharth@embedjournal.com>
Add configuration and memory definitions to support STM32F103x8
Medium-density performance line SoC with 64 KB Flash.
Merge multiple files into single Kconfig.defconfig.stm32f103xx
Signed-off-by: Siddharth Chandrasekaran <siddharth@embedjournal.com>
The Sam4x HAL defines __NVIC_PRIO_BITS to 4. Fixes an issue where
interrupt priorities and masking were not being done correctly.
Issue: ZEP-2243
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Update driver to use DTS-generated #defines for port names,
and not obsolete Kconfig variables.
Signed-off-by: Geoffrey Le Gourriérec <geoffrey.legourrierec@smile.fr>
Recent changes (69255043, 91f67a13, 84628e8b, fa4a3932) add support
for a partition table in the flash. Add support for this to the nxp
k6x dtsi file. By default, code will occupy the entire flash. By
setting a chosen node in an application, the code can be linked into
one of the partitions. For example, and app could create a
'frdm_k64f.overlay' file at the top of their project with:
/ {
chosen {
zephyr,code-partition = &slot0_partition;
};
};
to place an application in slot 0.
Signed-off-by: David Brown <david.brown@linaro.org>
- board name olimex_stm32_e407
- CPU STM32F407ZGT6 Cortex M4
- LED/BUTTON support
- Console on USART1 with 8n1 115200 baud
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
The Sam3x HAL defines __NVIC_PRIO_BITS to 4.
Fixes an issue where interrupt priorities and masking
were not being done correctly.
Issue: ZEP-2243
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add necessary board files, pinmux and device tree in order to have a
usable debug console.
Origin: Original
Change-Id: I43a9d278c3f2c936a714263626722f630367b663
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Add necessary Kconfig and minimal device tree in order to support
STM32F412ZG variant as found on the Nucleo STM32F412 board.
Origin: Original
Change-Id: Ic98a686f478ce551dc6101466ed0cf16924109e8
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
This commit rework stm32f4 series dtsi files hierarchy.
stm32f4.dtsi was used as maximum common set of IP while it should
be considered as the minimum common subset.
Then, following on stm32f4 series hierarchy and inheritance rules,
stm32f4xxx.dtsi files are reworked to include the "parent" soc dtsi
file and then add own IPs to each SoC.
Change-Id: I394278c84a8ea38921f9f143f4fc52ef1c645d05
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In stm32 dtsi linux files, uart generic node name is serial.
Rename uart node names of stm32 dtsi files from uart@ to serial@
Change-Id: Iac5cbf7955f23cee520bc1790b0f324a17bfcf9e
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit fixes uart only nodes situation for stm32 devices.
st,stm32-uart yaml description is added to enable compilation
Change-Id: Iea78693bdfb90fbb09612b75685ed7ca0ccca6d6
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add configuration, dtsi and memory configuration fixup for the
STM32F469XI High Performance SoC.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The chosen property that sets which serial port is being used for the
console device wasn't set. Add the property "zephyr,console" to the
Arduino Due, CC3200-LaunchXL, CC3220SF-LaunchXL, and QEMU Cortex M3
boards.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we can utilize label in the device tree we can convert to
getting the device name for the Atmel SAM3 UART out of the device
tree instead of from Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we can utilize label in the device tree we can convert to
getting the device name for the TI Stellaris UART out of the device
tree instead of from Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we can utilize label in the device tree we can convert to
getting the device name for the TI CC32xx UART out of the device
tree instead of from Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we can utilize label in the device tree we can convert to
getting the device name for the ARM CMSDK APB UART out of the device
tree instead of from Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we can utilize label in the device tree we can convert to
getting the device name for the NXP Kinetis UART out of the device tree
instead of from Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we can utilize label in the device tree we can convert to
getting the device name for the NRF UART out of the device tree
instead of from Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we can utilize label in the device tree we can convert to
getting the device name for the STM32 UART out of the device tree
instead of from Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add configuration, pinmux, dts and documentation for the STM32L496G
Discovery board based on the STM32L496AG SoC.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add missing UARTs from the main device tree. They are declared as
disabled and can be enabled individually by each board.
Change-Id: I0ec73c59b4c3c4ee56f12ae70f2d6cdbec14fe33
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Add necessary board files, pinmux and device tree in order to have a
usable debug console.
Origin: Original
Change-Id: I280320700352fd36a544c03f4e57d2eeec2449e5
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Add necessary Kconfig and minimal device tree in order to support
STM32F413xH variants as found on the Nucleo STM32F413 board.
Origin: Original
Change-Id: I60230c240d6acb610f16a02c62048d448476e9c5
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Rename SOC_STM32F407XX to SOC_STM32F407XG to keep flash
size information.
Aim is to be able to distinguish flash size variants of
the SoC when needed (for instance in dts/arm/st/mem.h file).
Change-Id: I0afa16e86b7c99b9e685004f96beeb888f9e7568
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rename SOC_STM32F429XX to SOC_STM32F429XI to keep flash
size information.
Aim is to be able to distinguish flash size variants of
the SoC when needed (for instance in dts/arm/st/mem.h file)
Change-Id: Id188b7703d2bce0a3ded09132ff0f205efa9c143
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rename SOC_STM32L476XX to SOC_STM32L476XG to keep flash
size information.
Aim is to be able to distinguish flash size variants of
the SoC when needed (for instance in dts/arm/st/mem.h file)
Change-Id: I834bb5b83c24c39e90c0492a2b22a7c7802de361
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The xC tag in the SoC reference indicates the flash size, use it in the
configuration to permit selection of correct flash size for dts.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This patch enables the generation of the ARM CMSDK UART base address
from the device tree.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This adds support for the nRF51 chip on the board.
If you'd like to run Zephyr on the STM32F4 chip on Carbon, you need to
use the 96b_carbon board instead.
The current SPI Bluetooth protocol only uses 5 wires, so we use the
remaining pin as UART TX.
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Add configuration, dts and documentation for the Nucleo L432KC board
based on the STM32L432KC SoC.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Converted Stellaris UART driver over to utilize device tree generated
defines. Added a yaml description for the uart, and converted over the
ti_lm3s6965 SoC & qemu_cortex_m3 board port over to utilize it.
Change-Id: Ie20844eb63d2c68eb59ad4160f7f5b5a35e2943b
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Introduce a simple device tree for the TI lm3s6965 SoC and QEMU
Cortex-M3 board port. We get flash and memory base addresses and sizes
from the device tree as well as the ARM NVIC number of priority bits.
Change-Id: I4452b5543de7be55518997e54837ccbfd4f121df
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add device tree support for nRF51822 SoCs and Arduino 101-BLE,
Curie-BLE, BLE Nano, PCA10028-DK, and Quark-SE BLE boards. This
is minimal support for memory, flash, and UART.
Change-Id: I7e572bea537e384b6d66e520462f023ace0c9b35
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add device tree support for nRF52840 SoC and PCA10056-DK board. This
is minimal support for memory, flash, and UART.
For the nRF52840 we select between "nordic,nrf-uarte", "nordic,nrf-uart"
support for each board.
Change-Id: I1c377e0cb97ff4716ea5489fffaa7c0e2b34d18a
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add device tree support for Nitrogen 96board, BLE Nano 2, and
nRF52-PCA10040 DK boards. This is minimal support for memory, flash,
and UART.
For the nRF52832 we select between "nordic,nrf-uarte", "nordic,nrf-uart"
support for each board.
Change-Id: Ia247b9b710a72416e9ab0de3ca1429bfab8917f8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit provides support for disco_l475_iot1 board
Pinmux driver is provided with initial support definitions
Change-Id: I17b637a8ba0b033014969eca8fffe76319c47c52
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to allow the use of such board, a very preliminar port was
developed. It consists of board files, as well as pinmux, uart, gpio,
spi drivers and device tree files.
Change-Id: I5753064e39e0b023cf4481744c176de26d8dbebb
Signed-off-by: Gustavo Denardin <gustavo.denardin@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The CC3200 doesn't have on chip flash, so we should be including it in
the dts.
Change-Id: I8d4bbe2b09ed1aa563efe4c979da1f4729b93534
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds a shim layer around the mcux lpsci driver to adapt it to the Zephyr
serial interface.
Change-Id: I024f1605e3194f34bb57e8a121900e05b3085a82
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add support for STM32L475xG SoC as a preliminary for
Discovery IOT board support.
stm32l476.dtsi file is now including stm32l475.dtsi
since STM32L476 SoC is a STM32L475 SoC with LCD support
Change-Id: I7567255e4172231cbf4899474617ecae0cd68d64
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This to align with previous patch:
"dts: Align uart "baud-rate" property to device tree spec "current-speed""
Jira: ZEP-1958
Change-Id: I65328cf63e25b0378f270b5f60deb9d6a1f49b8c
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
CC3220SF_LAUNCHXL effectively replaces the CC3200_LAUNCHXL,
with support for the CC3220SF SoC, which is an update for
the CC3200 SoC.
This is supported by the Texas Instruments CC3220 SDK.
Jira: ZEP-1958
Change-Id: I2484d3ee87b7f909c783597d95128f2b45db36f2
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Devicetree.org specifies that serial devices property used to set
baud rate is "current-speed", while zephyr uses "baud-rate".
Align property name in order to keep zephyr dts files compatible
with device tree specification and could be re-used from/to
Linux for instance. We also cleanup a few SoCs that set "baud-rate" in
the SoC dts and not the board.
Jira: ZEP-2048
Change-Id: I097e7439ee46fe77c628b56531772950382fafcc
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This in preparation for adding a cc3220sf DTS file, which
has a different address for sram0 than the cc3200.
Also moved baud-rate out of soc dtsi file to board dts.
Jira: JEP-1958
Change-Id: I641452c0a8a6d1ad4424e132d6ef2de71d8545b4
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Add plumbing to build system and SoC level dtsi for the NRF52832 SoC.
We additionally add the necessary yaml files for the UART on the NRF52
SoCs.
Change-Id: I3b4a821b2993827e33d8e84bdbbc759d1521f8bd
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds initial support and documentation for the kw40z on the hexiwear
board.
Jira: ZEP-1391
Change-Id: Idb58bfb3c2951b1f737a8c547860bde4ef4d9a3e
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds initial support for the kw40z SoC. This SoC has all the same
peripherals as the kw41z but with less flash and ram, so the defconfig
and dts are nearly the same.
Jira: ZEP-1388
Change-Id: Ib804451e8c2c71c4ff7d342bf23f6567d1542a2d
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Converted over all STM32F3 based boards to use device tree and removed
associated bits that now come from the device tree for STM32F3.
Boards that are now using devicetree:
* Nucleo f334r8
* STM32373C Eval
Change-Id: I081a1d83f86e417a98b6864c745354b6b32953b7
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Converted over all STM32F1 based boards to use device tree and removed
associated bits that now come from the device tree for STM32F1. Also
renamed the STM32F10{3,7} SoC dtsi to try and make it clear that the 'X'
is a place holder. Fixedup the top level compatiables in the boards to
be the specific 'X' instead of the generic one.
Boards that are now using devicetree:
* Nucleo f103rb
* STM3210C Eval
* STM32 MINI A15
Change-Id: I29b3634ec7451f974687d55980414efa655e2e96
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Converted over all STM32F4 based boards to use device tree and removed
associated bits that now come from the device tree for STM32F4.
Boards that are now using devicetree:
* 96b_carbon
* nucleo f401re
* nucleo f411re
Change-Id: Ibe197ca0a3f5ad78d594485a578d986403cc824a
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Updated st/mem.h to support the following SoCs:
CONFIG_SOC_STM32F303XC
CONFIG_SOC_STM32F407XX
CONFIG_SOC_STM32F429XX
Change-Id: I1654c1fd8dc0d1eb471c092777a8fd262465dc51
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Introduce a __SIZE_K macro to make things a bit more human readable.
Also fixed up sizes for CONFIG_SOC_STM32F411XE.
Change-Id: I01b8b5f627ad949c2af01ee966428bfabe09e2ee
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commits provides dts files for non ST, STM32 based boards.
Change-Id: Ib324ba418fb27ddbce45a60fbe8e73c7b6896aa4
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit provides dts file for nucleo boards.
For now dtsi files only populates uart nodes so other nodes
are not taken into account into board dts files.
Change-Id: Ide95a8ba3671b91ff0311b7671e77b3bf96db297
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit provides dtsi files for available stm32 base boards.
For now only uart nodes and IRQ number are provided in order to
enable delivery of coherent material.
It also clears additional content from stm32f103xb.dtsi
Change-Id: I62d932c7f22b56e95bcd9566ce39e14a393dd640
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As there can be a large number of FLASH & SRAM sizes for the same SoC
having a dts/dtsi for each one would be extremely painful. Lets just
use some #defines to set that FLASH & SRAM sizes based on the SoC that
is being built.
Change-Id: I06388ada4e49ed3d576da31150288512bb6b4485
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch modifies the DTS file to make the inclusion of the
bluetooth UART port conditional on CONFIG_BLUETOOTH option.
Issue: ZEP-1745
Change-Id: Iea8dc60fe17d131d8e3765e1962b25d157065c67
Signed-off-by: Andy Gross <andy.gross@linaro.org>
In general we should be using hardcoded addresses in the dtsi files
rather than getting ifdef from other places. As the unit address of the
node is typically based on the address in hex w/o the '0x' we can't just
use #defines directly.
Change-Id: I0e17e001151728d16842806d9407e66e6e5129cf
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move the SoC dtsi into a vendor dir so as we grow and possibly share
things with other projects we are hopefully in sync (or closer to it).
Change-Id: I71666cff49f9694eee3f5d92dac8aeea416b730a
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Introduce a system include so that board dts files are able to live in
any location and properly include the things they need.
Change-Id: Icd26433117a4ca9726aeb74eec9f72c6d9df617c
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Recommend to drop the generic arm,nvic and just use arm,v{6,7,8}m-nvic.
Remove the yaml and switch to using arm,v6m-nvic or arm,v7m-nvic in the
various places.
Change-Id: Ide55d558d38ab247ee6d9a8d3d0a7f21b9c859bd
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As part of the transition to Device Tree, a temporary
HAS_DTS configuration variable, and a .fixup file per board
with symbol aliases were added.
This patch removes the cc32xx related fixup file
definitions, except for those used additionally outside
the cc32xx drivers.
Since cc32xx has DTS files, and since HAS_DTS will always be true,
it also removes the 'if !HAS_DTS' blocks from the cc32xx Kconfig
files.
Change-Id: I1c1b9f734795f523342f82ab32f2a38983812c0b
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As per new binding for arm,nvic, rename the 'num-irq-prio-bits' property
to 'arm,num-irq-priority-bits'.
Change-Id: I2182a905de340e134c67ac4aabe926fbb47c0d5a
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworking the ARM NVIC binding and cleaning it up. Towards this
introduce a new compatibility for this new binding. So we rename
arm,armv{6,7}-nvic to arm,v{6,7}-nvic (for new binding). We also just
use the bit more generic arm,nvic in device tree files.
Change-Id: I5a2c45313ed94619d9268f2c035dacbc8acded29
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move back to getting the number of IRQs from Kconfig. We do this
because the number of IRQs should really just be determined by scanning
the device tree and figuring out the highest IRQ value used.
Change-Id: I8e0dbec1d9d036d4e899b237c4dc7d833c422e18
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rather than having a zephyr specific property we will encode the IRQ
priority as part of the interrupt property for ARM NVIC based interrupt
controllers.
Change-Id: I7d1489f0bffa7a6369f0622f748bb70dc83fa0cd
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch adds the base DTS files required to support DTS for the
STM32F103xB based Olimexino STM32 board.
Origin: Original
Change-Id: I2a20d3f3ce8b1d3c20fe92b2ffa584c69fbd96a5
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Only the IRQ prasing was using cell_prefix and cell_string does the same
thing so lets just use that everywhere.
Change-Id: I2ef9b1e2c1baef54b71d811c835b29a9ca8fe81b
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move SRAM and flash nodes out of stm32l476.dtsi
RAM and Flash sizes depend on last letter ("G" in the case).
Hence it must be defined out of soc description file
Update information for leds
Change-Id: I980129c44c335322ddbe57252a7001296094c7cb
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Some files made it through review process with full license header.
Change-Id: I2722b127c40b4b19500042c12e4fde85a165bae9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patch adds the UART ports required by for Bluetooth. Baud rate
was moved from the Kinetis dtsi file to the relevant board files.
Jira: ZEP-1745
Change-Id: Iac4f748fd82217662800dbf48baea087e5d3a1df
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds the base DTS support for the KW41Z Freedom board. The
initial set of changes include SRAM, FLASH, IRQ controller and LPUART
support.
Change-Id: Ic68c4959ddad0c5cfe70d5576a0e58372b93ec9d
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
This patch adds DTS support to the ARM CMSDK UART driver. The DTS
currently specifies the IRQ, IRQ PRIO, and base address of the port.
Change-Id: I8e5bc81c013958be4297d563495bf126b53a83a9
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds the base DTS support for the V2M Beetle board. The
initial set of changes include SRAM, FLASH, and IRQ controller support.
Change-Id: I06685622b9c57ac358544c71350074ce06e3371e
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds device tree support to the STM32 UART driver. The base
address, interrupt, and interrupt priority values can now come from DTS.
Change-Id: I3c383da8b200037601ecb2dc087f99ef103761bb
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds the base DTS and yaml files required to support DTS
for the STM32L476 based Nucleo board.
Change-Id: Ic606a895a25f27d2990f651d0f3c3c5d84818cfd
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds the necessary DTS, YAML, and Makefile changes necessary
to generate proper include information for the CC3200. The initial
base support includes SRAM, FLASH, and UART devices.
Change-Id: I8ef8c24c3915198dbb5cfeb2431aa6dc68267d0e
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds DTS support for the Hexiwear K64 platform. This
includes enabling the DTS config option and adding conditionals around
the options to be replaced.
In addition, a DTS file is provided that customizes the Kinetis
platform to match the hexiwear board. A fixup file is provided to map
the generated information to the current client driver usage. This
file is temporary.
Change-Id: I247d538c6e13e0d1d4141fee74046575a7d2972e
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds DTS support for the FRDM_K64F board. The defconfig
enables the DTS usage and the FRDM K64F specific DTS file provides the
differences from the base Kinetis DTS definitions.
A fixup file is provided to map the generated configuration information
to the driver consumers. The fixup file will be removed once the
drivers are modified to handle the newly generated information.
Change-Id: Ib0ada28faff6a30e8b40eba5c5853e9018ae5fcb
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds DTS support and related files for the NXP Kinetis
platform. The DTS files contain the base definitions for the hardware
nodes on Kinetis platforms. The YAML files provide the definitions of
the contents of the DTS nodes.
The Kconfig changes were put in place to allow for the conversion of
existing drivers. Once those drivers are modified, the Kconfig options
that are replaced by the DTS information will be removed.
Change-Id: If110fffa99c0b12471cf2df206da6687277e4756
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds the base DTS and YAML files that may be referenced by
SoCs. The device tree files provide base definitions for the more well
known ARMV7M device nodes. These files are meant to be included in
SoC vendor specific device tree files.
The YAML files provide definitions for the contents of device tree node
that contain information that will be parsed and used for configuration
in the system.
DTS files define hardware and software configuration and YAML files
provide the markers for knowing which pieces need to be extracted.
Change-Id: I7e90fe19f09afb269b7b2988c2c19c0f26d7ee7c
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support for using device tree configuration files for
configuring ARM platforms.
In this patch, only the FLASH_SIZE, SRAM_SIZE, NUM_IRQS, and
NUM_IRQ_PRIO_BITS were removed from the Kconfig options. A minimal set
of options were removed so that it would be easier to work through the
plumbing of the build system.
It should be noted that the host system must provide access to the
device tree compiler (DTC). The DTC can usually be installed on host
systems through distribution packages or by downloading and compiling
from https://git.kernel.org/pub/scm/utils/dtc/dtc.git
This patch also requires the Python yaml package.
This change implements parts of each of the following Jira:
ZEP-1304
ZEP-1305
ZEP-1306
ZEP-1307
ZEP-1589
Change-Id: If1403801e19d9d85031401b55308935dadf8c9d8
Signed-off-by: Andy Gross <andy.gross@linaro.org>
