drivers/clock_control: Add support to stm32wb series
Add support to stm32wb series in stm32 clock_control driver. Ip is similar to stm32l4 one but AHB bus presacler is renamed to "CPU1" and CPU2 and AHB4 prescalers should be defined. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
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7117f1c4d4
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7 changed files with 149 additions and 17 deletions
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@ -18,4 +18,5 @@ if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X stm32f7x_ll_clock.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L0X stm32l0x_ll_clock.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X stm32l4x_ll_clock.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX stm32wbx_ll_clock.c)
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endif()
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@ -42,7 +42,7 @@ config CLOCK_STM32_SYSCLK_SRC_HSI
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config CLOCK_STM32_SYSCLK_SRC_MSI
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bool "MSI"
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depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X
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depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX
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help
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Use MSI as source of SYSCLK
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@ -92,7 +92,7 @@ default CLOCK_STM32_PLL_SRC_HSI
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config CLOCK_STM32_PLL_SRC_MSI
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bool "MSI"
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depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X
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depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX
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help
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Use MSI as source of PLL
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@ -321,7 +321,7 @@ config CLOCK_STM32_PLL_DIVISOR
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endif # SOC_SERIES_STM32L0X
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if SOC_SERIES_STM32L4X
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if SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX
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config CLOCK_STM32_PLL_M_DIVISOR
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int "PLL divisor"
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@ -377,12 +377,13 @@ config CLOCK_STM32_MSI_PLL_MODE
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help
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Enable hardware auto-calibration with LSE.
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endif # SOC_SERIES_STM32L4X
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endif # SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX
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config CLOCK_STM32_AHB_PRESCALER
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int "AHB prescaler"
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default 1
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range 1 512
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depends on !SOC_SERIES_STM32WBX
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help
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AHB prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128,
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256, 512.
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@ -407,6 +408,34 @@ config CLOCK_STM32_APB2_PRESCALER
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endif # SOC_SERIES_STM32F0X!=y
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if SOC_SERIES_STM32WBX
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config CLOCK_STM32_CPU1_PRESCALER
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int "CPU1 HCLK prescaler"
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default 1
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range 1 512
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help
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CPU1 HCLK prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128,
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256, 512.
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config CLOCK_STM32_CPU2_PRESCALER
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int "CPU2 HCLK prescaler"
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default 1
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range 1 512
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help
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CPU2 HCLK prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128,
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256, 512.
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config CLOCK_STM32_AHB4_PRESCALER
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int "AHB4 HCLK prescaler"
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default 1
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range 1 512
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help
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HCLK4 prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128,
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256, 512.
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endif # SOC_SERIES_STM32WBX
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choice
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prompt "STM32 MCO1 Clock Source"
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default CLOCK_STM32_MCO1_SRC_NOCLOCK
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@ -31,15 +31,30 @@
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#define z_mco2_prescaler(v) LL_RCC_MCO2_DIV_ ## v
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#define mco2_prescaler(v) z_mco2_prescaler(v)
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#ifdef CONFIG_SOC_SERIES_STM32WBX
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#define __LL_RCC_CALC_HCLK_FREQ __LL_RCC_CALC_HCLK1_FREQ
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#endif /* CONFIG_SOC_SERIES_STM32F0X */
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/**
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* @brief fill in AHB/APB buses configuration structure
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*/
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static void config_bus_clk_init(LL_UTILS_ClkInitTypeDef *clk_init)
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{
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#ifdef CONFIG_SOC_SERIES_STM32WBX
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clk_init->CPU1CLKDivider = ahb_prescaler(
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CONFIG_CLOCK_STM32_CPU1_PRESCALER);
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clk_init->CPU2CLKDivider = ahb_prescaler(
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CONFIG_CLOCK_STM32_CPU2_PRESCALER);
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clk_init->AHB4CLKDivider = ahb_prescaler(
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CONFIG_CLOCK_STM32_AHB4_PRESCALER);
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#else
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clk_init->AHBCLKDivider = ahb_prescaler(
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CONFIG_CLOCK_STM32_AHB_PRESCALER);
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#endif /* CONFIG_SOC_SERIES_STM32WBX */
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clk_init->APB1CLKDivider = apb1_prescaler(
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CONFIG_CLOCK_STM32_APB1_PRESCALER);
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#ifndef CONFIG_SOC_SERIES_STM32F0X
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clk_init->APB2CLKDivider = apb2_prescaler(
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CONFIG_CLOCK_STM32_APB2_PRESCALER);
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@ -65,7 +80,8 @@ static inline int stm32_clock_control_on(struct device *dev,
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F4X) || \
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defined(CONFIG_SOC_SERIES_STM32F7X) || \
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defined(CONFIG_SOC_SERIES_STM32F2X)
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defined(CONFIG_SOC_SERIES_STM32F2X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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case STM32_CLOCK_BUS_AHB2:
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LL_AHB2_GRP1_EnableClock(pclken->enr);
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break;
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@ -74,7 +90,9 @@ static inline int stm32_clock_control_on(struct device *dev,
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case STM32_CLOCK_BUS_APB1:
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LL_APB1_GRP1_EnableClock(pclken->enr);
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break;
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F0X)
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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case STM32_CLOCK_BUS_APB1_2:
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LL_APB1_GRP2_EnableClock(pclken->enr);
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break;
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@ -120,7 +138,9 @@ static inline int stm32_clock_control_off(struct device *dev,
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case STM32_CLOCK_BUS_APB1:
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LL_APB1_GRP1_DisableClock(pclken->enr);
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break;
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F0X)
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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case STM32_CLOCK_BUS_APB1_2:
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LL_APB1_GRP2_DisableClock(pclken->enr);
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break;
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@ -173,9 +193,11 @@ static int stm32_clock_control_get_subsys_rate(struct device *clock,
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*rate = ahb_clock;
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break;
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case STM32_CLOCK_BUS_APB1:
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F0X)
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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case STM32_CLOCK_BUS_APB1_2:
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#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X */
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#endif
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*rate = apb1_clock;
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break;
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#ifndef CONFIG_SOC_SERIES_STM32F0X
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@ -238,12 +260,20 @@ static inline void stm32_clock_control_mco_init(void)
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static int stm32_clock_control_init(struct device *dev)
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{
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LL_UTILS_ClkInitTypeDef s_ClkInitStruct;
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u32_t hclk_prescaler;
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ARG_UNUSED(dev);
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/* configure clock for AHB/APB buses */
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config_bus_clk_init((LL_UTILS_ClkInitTypeDef *)&s_ClkInitStruct);
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/* update local hclk prescaler variable */
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#ifdef CONFIG_SOC_SERIES_STM32WBX
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hclk_prescaler = s_ClkInitStruct.CPU1CLKDivider;
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#else
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hclk_prescaler = s_ClkInitStruct.AHBCLKDivider;
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#endif /* CONFIG_SOC_SERIES_STM32WBX */
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/* Some clocks would be activated by default */
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config_enable_default_clocks();
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@ -302,9 +332,13 @@ static int stm32_clock_control_init(struct device *dev)
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#endif /* CONFIG_CLOCK_STM32_HSE_BYPASS */
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/* Switch to PLL with HSE as clock source */
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LL_PLL_ConfigSystemClock_HSE(CONFIG_CLOCK_STM32_HSE_CLOCK, hse_bypass,
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&s_PLLInitStruct,
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&s_ClkInitStruct);
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LL_PLL_ConfigSystemClock_HSE(
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#ifndef CONFIG_SOC_SERIES_STM32WBX
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CONFIG_CLOCK_STM32_HSE_CLOCK,
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#endif
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hse_bypass,
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&s_PLLInitStruct,
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&s_ClkInitStruct);
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/* Disable other clocks */
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LL_RCC_HSI_Disable();
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@ -332,14 +366,14 @@ static int stm32_clock_control_init(struct device *dev)
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/* Set HSE as SYSCLCK source */
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
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LL_RCC_SetAHBPrescaler(s_ClkInitStruct.AHBCLKDivider);
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LL_RCC_SetAHBPrescaler(hclk_prescaler);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
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}
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/* Update SystemCoreClock variable */
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LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(
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CONFIG_CLOCK_STM32_HSE_CLOCK,
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s_ClkInitStruct.AHBCLKDivider));
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hclk_prescaler));
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/* Set APB1 & APB2 prescaler*/
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LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
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/* Set MSI as SYSCLCK source */
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSI);
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LL_RCC_SetAHBPrescaler(s_ClkInitStruct.AHBCLKDivider);
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LL_RCC_SetAHBPrescaler(hclk_prescaler);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSI) {
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}
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@ -389,6 +423,11 @@ static int stm32_clock_control_init(struct device *dev)
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/* Set APB1 & APB2 prescaler*/
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LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
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LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
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#ifdef CONFIG_SOC_SERIES_STM32WBX
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/* Set C2 AHB & AHB4 prescalers */
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LL_C2_RCC_SetAHBPrescaler(s_ClkInitStruct->CPU2CLKDivider);
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LL_RCC_SetAHB4Prescaler(s_ClkInitStruct->AHB4CLKDivider);
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#endif /* CONFIG_SOC_SERIES_STM32WBX */
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/* Set flash latency */
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/* MSI used as SYSCLK (16MHz), set latency to 0 */
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#elif CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI
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stm32_clock_switch_to_hsi(s_ClkInitStruct.AHBCLKDivider);
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stm32_clock_switch_to_hsi(hclk_prescaler);
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/* Update SystemCoreClock variable */
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LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(HSI_VALUE,
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s_ClkInitStruct.AHBCLKDivider));
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hclk_prescaler));
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/* Set APB1 & APB2 prescaler*/
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LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
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43
drivers/clock_control/stm32wbx_ll_clock.c
Normal file
43
drivers/clock_control/stm32wbx_ll_clock.c
Normal file
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/*
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*
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* Copyright (c) 2019 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <soc_registers.h>
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#include <clock_control.h>
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#include <misc/util.h>
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#include <clock_control/stm32_clock_control.h>
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#include "stm32_ll_clock.h"
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#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
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/* Macros to fill up division factors values */
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#define _pllm(v) LL_RCC_PLLM_DIV_ ## v
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#define pllm(v) _pllm(v)
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#define _pllr(v) LL_RCC_PLLR_DIV_ ## v
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#define pllr(v) _pllr(v)
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/**
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* @brief fill in pll configuration structure
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*/
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void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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{
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pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
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pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
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pllinit->PLLR = pllr(CONFIG_CLOCK_STM32_PLL_R_DIVISOR);
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}
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#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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/* Nothing for now */
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}
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@ -38,6 +38,14 @@
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label = "FLASH_STM32";
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};
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};
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rcc: rcc@58000000 {
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compatible = "st,stm32-rcc";
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clocks-controller;
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#clock-cells = <2>;
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reg = <0x58000000 0x400>;
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label = "STM32_CLK_RCC";
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};
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};
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};
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@ -13,5 +13,6 @@ config SOC_SERIES_STM32WBX
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select HAS_STM32CUBE
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select CPU_HAS_ARM_MPU
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select CPU_HAS_SYSTICK
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select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
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help
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Enable support for STM32WB MCU series
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@ -7,6 +7,10 @@
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/**
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* @file SoC configuration macros for the STM32WB family processors.
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*
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* Based on reference manual:
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* TODO: Provide reference when known
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*
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* Chapter 2.2.2: Memory map and register boundary addresses
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*/
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*/
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#include <kernel_includes.h>
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#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
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#include <stm32wbxx_ll_utils.h>
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#include <stm32wbxx_ll_bus.h>
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#include <stm32wbxx_ll_rcc.h>
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#include <stm32wbxx_ll_system.h>
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#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
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#endif /* !_ASMLANGUAGE */
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#endif /* _STM32WBX_SOC_H_ */
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