soc: arm: st_stm32: Add STM32L1 SoC series
Add STM32L1 SoC series support with STM32L15XXB as the target SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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14 changed files with 278 additions and 0 deletions
49
dts/arm/st/l1/stm32l1.dtsi
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49
dts/arm/st/l1/stm32l1.dtsi
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/*
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* Copyright (c) 2019 Linaro Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m3";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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};
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soc {
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flash-controller@40023c00 {
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compatible = "st,stm32l1-flash-controller";
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label = "FLASH_CTRL";
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reg = <0x40023c00 0x400>;
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interrupts = <4 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "soc-nv-flash";
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label = "FLASH_STM32";
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write-block-size = <4>;
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};
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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7
dts/arm/st/l1/stm32l151.dtsi
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7
dts/arm/st/l1/stm32l151.dtsi
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/*
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* Copyright (c) 2019 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/l1/stm32l1.dtsi>
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22
dts/arm/st/l1/stm32l151Xb.dtsi
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22
dts/arm/st/l1/stm32l151Xb.dtsi
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/*
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* Copyright (c) 2019 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/l1/stm32l151.dtsi>
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/ {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(16)>;
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};
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soc {
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flash-controller@40023c00 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(128)>;
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};
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};
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};
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};
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---
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title: STM32 L1 Flash Controller
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version: 0.1
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description: >
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This binding gives a base representation of the STM32 L1 Flash Controller
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inherits:
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!include flash-controller.yaml
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properties:
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compatible:
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constraint: "st,stm32l1-flash-controller"
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...
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4
soc/arm/st_stm32/stm32l1/CMakeLists.txt
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4
soc/arm/st_stm32/stm32l1/CMakeLists.txt
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zephyr_include_directories(${ZEPHYR_BASE}/drivers)
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zephyr_sources(
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soc.c
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)
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15
soc/arm/st_stm32/stm32l1/Kconfig.defconfig.series
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soc/arm/st_stm32/stm32l1/Kconfig.defconfig.series
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# Kconfig - ST Microelectronics STM32L1 MCU line
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#
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# Copyright (c) 2019 Linaro Ltd.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_SERIES_STM32L1X
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source "soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l1*"
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config SOC_SERIES
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default "stm32l1"
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endif # SOC_SERIES_STM32L1X
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18
soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xb
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soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xb
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# Kconfig - ST Microelectronics STM32L151XB MCU
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#
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# Copyright (c) 2019 Linaro Ltd.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_STM32L151XB
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config SOC
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string
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default "stm32l151xb"
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config NUM_IRQS
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int
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default 45
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endif # SOC_STM32L151XB
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soc/arm/st_stm32/stm32l1/Kconfig.series
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soc/arm/st_stm32/stm32l1/Kconfig.series
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# Kconfig - ST Microelectronics STM32L1 MCU series
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#
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# Copyright (c) 2019 Linaro Ltd.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_SERIES_STM32L1X
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bool "STM32L1x Series MCU"
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select CPU_CORTEX_M3
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select SOC_FAMILY_STM32
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select HAS_STM32CUBE
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select CPU_HAS_SYSTICK
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select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
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help
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Enable support for STM32L1 MCU series
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15
soc/arm/st_stm32/stm32l1/Kconfig.soc
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soc/arm/st_stm32/stm32l1/Kconfig.soc
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# Kconfig - ST Microelectronics STM32L1 MCU line
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#
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# Copyright (c) 2019 Linaro Ltd.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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choice
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prompt "STM32L1x MCU Selection"
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depends on SOC_SERIES_STM32L1X
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config SOC_STM32L151XB
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bool "STM32L151XB"
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endchoice
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11
soc/arm/st_stm32/stm32l1/dts_fixup.h
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soc/arm/st_stm32/stm32l1/dts_fixup.h
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/*
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* Copyright (c) 2019 Linaro Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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/* End of SoC Level DTS fixup file */
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9
soc/arm/st_stm32/stm32l1/linker.ld
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soc/arm/st_stm32/stm32l1/linker.ld
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/* linker.ld - Linker command/script file */
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/*
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* Copyright (c) 2019 Linaro Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arch/arm/cortex_m/scripts/linker.ld>
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51
soc/arm/st_stm32/stm32l1/soc.c
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soc/arm/st_stm32/stm32l1/soc.c
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/*
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* Copyright (c) 2019 Linaro Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32L1 processor
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*/
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#include <device.h>
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#include <init.h>
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#include <arch/cpu.h>
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#include <cortex_m/exc.h>
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#include <linker/linker-defs.h>
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#include <string.h>
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int stm32l1_init(struct device *arg)
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{
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u32_t key;
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ARG_UNUSED(arg);
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key = irq_lock();
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z_clearfaults();
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/* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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irq_unlock(key);
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 2.1 MHz from MSI */
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SystemCoreClock = 2097000;
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return 0;
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}
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SYS_INIT(stm32l1_init, PRE_KERNEL_1, 0);
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34
soc/arm/st_stm32/stm32l1/soc.h
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soc/arm/st_stm32/stm32l1/soc.h
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/*
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* Copyright (c) 2019 Linaro Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file SoC configuration macros for the STM32L1 family processors.
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*
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* Based on reference manual:
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* STM32L1X advanced ARM ® -based 32-bit MCUs
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*
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* Chapter 2.2: Memory organization
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*/
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#ifndef _STM32L1_SOC_H_
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#define _STM32L1_SOC_H_
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#ifndef _ASMLANGUAGE
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#include <stm32l1xx.h>
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/* ARM CMSIS definitions must be included before kernel_includes.h.
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* Therefore, it is essential to include kernel_includes.h after including
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* core SOC-specific headers.
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*/
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#include <kernel_includes.h>
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#include <stm32l1xx_ll_system.h>
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#endif /* !_ASMLANGUAGE */
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#endif /* _STM32L1_SOC_H_ */
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12
soc/arm/st_stm32/stm32l1/soc_registers.h
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soc/arm/st_stm32/stm32l1/soc_registers.h
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/*
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* Copyright (c) 2019 Linaro Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _STM32L1X_SOC_REGISTERS_H_
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#define _STM32L1X_SOC_REGISTERS_H_
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/* include register mapping headers */
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#endif /* _STM32L1X_SOC_REGISTERS_H_ */
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