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dts: arm: Put IRQ priority into the interrupt property

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Rather than having a zephyr specific property we will encode the IRQ
priority as part of the interrupt property for ARM NVIC based interrupt
controllers.

Change-Id: I7d1489f0bffa7a6369f0622f748bb70dc83fa0cd
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-03-23 13:41:32 -05:00
commit 94107bc71d
23 changed files with 60 additions and 104 deletions
Download patch file Download diff file Expand all files Collapse all files

2
dts/arm/armv6-m.dtsi
View file

@ -12,7 +12,7 @@
compatible = "arm,armv6m-nvic";
reg = <0xe000e100 0xc00>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
systick: timer@e000e010 {

2
dts/arm/armv7-m.dtsi
View file

@ -12,7 +12,7 @@
compatible = "arm,armv7m-nvic";
reg = <0xe000e100 0xc00>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
systick: timer@e000e010 {

2
dts/arm/cc3200_launchxl.fixup
View file

@ -2,6 +2,6 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define EXCEPTION_UARTA0 TI_CC32XX_UART_4000C000_IRQ_0
#define CONFIG_UART_CC32XX_IRQ_PRI TI_CC32XX_UART_4000C000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_CC32XX_IRQ_PRI TI_CC32XX_UART_4000C000_IRQ_0_PRIORITY
#define UART_CC32XX_BASE_ADDRESS TI_CC32XX_UART_4000C000_BASE_ADDRESS
#define CONFIG_UART_CC32XX_BAUDRATE TI_CC32XX_UART_4000C000_BAUD_RATE

6
dts/arm/cc32xx_launchxl.dtsi
View file

@ -28,8 +28,7 @@
uart0: uart@UARTA0_BASE {
compatible = "ti,cc32xx-uart";
reg = <UARTA0_BASE 0x4c>;
interrupts = <EXP_UARTA0>;
zephyr,irq-prio = <3>;
interrupts = <EXP_UARTA0 3>;
baud-rate = <115200>;
status = "disabled";
};
@ -37,8 +36,7 @@
uart1: uart@UARTA1_BASE {
compatible = "ti,cc32xx-uart";
reg = <UARTA1_BASE 0x4c>;
interrupts = <EXP_UARTA1>;
zephyr,irq-prio = <3>;
interrupts = <EXP_UARTA1 3>;
baud-rate = <115200>;
status = "disabled";
};

12
dts/arm/frdm_k64f.fixup
View file

@ -2,19 +2,19 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE
#define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_IRQ_0_PRIORITY
#define CONFIG_UART_MCUX_1_BAUD_RATE NXP_K64F_UART_4006B000_BAUD_RATE
#define CONFIG_UART_MCUX_1_IRQ_PRI NXP_K64F_UART_4006B000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_MCUX_1_IRQ_PRI NXP_K64F_UART_4006B000_IRQ_0_PRIORITY
#define CONFIG_UART_MCUX_2_BAUD_RATE NXP_K64F_UART_4006C000_BAUD_RATE
#define CONFIG_UART_MCUX_2_IRQ_PRI NXP_K64F_UART_4006C000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_MCUX_2_IRQ_PRI NXP_K64F_UART_4006C000_IRQ_0_PRIORITY
#define CONFIG_UART_MCUX_3_BAUD_RATE NXP_K64F_UART_4006D000_BAUD_RATE
#define CONFIG_UART_MCUX_3_IRQ_PRI NXP_K64F_UART_4006D000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_MCUX_3_IRQ_PRI NXP_K64F_UART_4006D000_IRQ_0_PRIORITY
#define CONFIG_UART_MCUX_4_BAUD_RATE NXP_K64F_UART_400EA000_BAUD_RATE
#define CONFIG_UART_MCUX_4_IRQ_PRI NXP_K64F_UART_400EA000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_MCUX_4_IRQ_PRI NXP_K64F_UART_400EA000_IRQ_0_PRIORITY
#define CONFIG_UART_MCUX_5_BAUD_RATE NXP_K64F_UART_400EB000_BAUD_RATE
#define CONFIG_UART_MCUX_5_IRQ_PRI NXP_K64F_UART_400EB000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_MCUX_5_IRQ_PRI NXP_K64F_UART_400EB000_IRQ_0_PRIORITY

2
dts/arm/frdm_kw41z.fixup
View file

@ -2,4 +2,4 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV6M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define CONFIG_UART_MCUX_LPUART_0_BAUD_RATE NXP_KW41Z_LPUART_40054000_BAUD_RATE
#define CONFIG_UART_MCUX_LPUART_0_IRQ_PRI NXP_KW41Z_LPUART_40054000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_MCUX_LPUART_0_IRQ_PRI NXP_KW41Z_LPUART_40054000_IRQ_0_PRIORITY

12
dts/arm/hexiwear_k64.fixup
View file

@ -2,19 +2,19 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE
#define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_IRQ_0_PRIORITY
#define CONFIG_UART_MCUX_1_BAUD_RATE NXP_K64F_UART_4006B000_BAUD_RATE
#define CONFIG_UART_MCUX_1_IRQ_PRI NXP_K64F_UART_4006B000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_MCUX_1_IRQ_PRI NXP_K64F_UART_4006B000_IRQ_0_PRIORITY
#define CONFIG_UART_MCUX_2_BAUD_RATE NXP_K64F_UART_4006C000_BAUD_RATE
#define CONFIG_UART_MCUX_2_IRQ_PRI NXP_K64F_UART_4006C000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_MCUX_2_IRQ_PRI NXP_K64F_UART_4006C000_IRQ_0_PRIORITY
#define CONFIG_UART_MCUX_3_BAUD_RATE NXP_K64F_UART_4006D000_BAUD_RATE
#define CONFIG_UART_MCUX_3_IRQ_PRI NXP_K64F_UART_4006D000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_MCUX_3_IRQ_PRI NXP_K64F_UART_4006D000_IRQ_0_PRIORITY
#define CONFIG_UART_MCUX_4_BAUD_RATE NXP_K64F_UART_400EA000_BAUD_RATE
#define CONFIG_UART_MCUX_4_IRQ_PRI NXP_K64F_UART_400EA000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_MCUX_4_IRQ_PRI NXP_K64F_UART_400EA000_IRQ_0_PRIORITY
#define CONFIG_UART_MCUX_5_BAUD_RATE NXP_K64F_UART_400EB000_BAUD_RATE
#define CONFIG_UART_MCUX_5_IRQ_PRI NXP_K64F_UART_400EB000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_MCUX_5_IRQ_PRI NXP_K64F_UART_400EB000_IRQ_0_PRIORITY

10
dts/arm/nucleo_l476rg.fixup
View file

@ -10,25 +10,25 @@
#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE
#define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40013800_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40013800_IRQ_0_PRIORITY
#define PORT_1_IRQ ST_STM32_USART_40013800_IRQ_0
#define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_BAUD_RATE
#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY
#define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0
#define CONFIG_UART_STM32_PORT_3_BASE_ADDRESS ST_STM32_USART_40004800_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_3_BAUD_RATE ST_STM32_USART_40004800_BAUD_RATE
#define CONFIG_UART_STM32_PORT_3_IRQ_PRI ST_STM32_USART_40004800_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_STM32_PORT_3_IRQ_PRI ST_STM32_USART_40004800_IRQ_0_PRIORITY
#define PORT_3_IRQ ST_STM32_USART_40004800_IRQ_0
#define CONFIG_UART_STM32_PORT_4_BASE_ADDRESS ST_STM32_USART_40004C00_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_4_BAUD_RATE ST_STM32_USART_40004C00_BAUD_RATE
#define CONFIG_UART_STM32_PORT_4_IRQ_PRI ST_STM32_USART_40004C00_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_STM32_PORT_4_IRQ_PRI ST_STM32_USART_40004C00_IRQ_0_PRIORITY
#define PORT_4_IRQ ST_STM32_USART_40004C00_IRQ_0
#define CONFIG_UART_STM32_PORT_5_BASE_ADDRESS ST_STM32_USART_40005000_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_5_BAUD_RATE ST_STM32_USART_40005000_BAUD_RATE
#define CONFIG_UART_STM32_PORT_5_IRQ_PRI ST_STM32_USART_40005000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_STM32_PORT_5_IRQ_PRI ST_STM32_USART_40005000_IRQ_0_PRIORITY
#define PORT_5_IRQ ST_STM32_USART_40005000_IRQ_0

39
dts/arm/nxp_k6x.dtsi
View file

@ -58,7 +58,7 @@
flash-controller@4001f000 {
compatible = "nxp,k64f-flash-controller";
reg = <0x4001f000 0x27c>;
interrupts = <18>, <19>;
interrupts = <18 0>, <19 0>;
#address-cells = <1>;
#size-cells = <1>;
@ -71,9 +71,8 @@
uart0: uart@4006a000 {
compatible = "nxp,k64f-uart";
reg = <0x4006a000 0x1000>;
interrupts = <31>, <32>;
interrupts = <31 0>, <32 0>;
interrupt-names = "status", "error";
zephyr,irq-prio = <0>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
@ -84,9 +83,8 @@
uart1: uart@4006b000 {
compatible = "nxp,k64f-uart";
reg = <0x4006b000 0x1000>;
interrupts = <33>, <34>;
interrupts = <33 0>, <34 0>;
interrupt-names = "status", "error";
zephyr,irq-prio = <0>;
status = "disabled";
};
@ -94,9 +92,8 @@
uart2: uart@4006c000 {
compatible = "nxp,k64f-uart";
reg = <0x4006c000 0x1000>;
interrupts = <35>, <36>;
interrupts = <35 0>, <36 0>;
interrupt-names = "status", "error";
zephyr,irq-prio = <0>;
status = "disabled";
};
@ -104,9 +101,8 @@
uart3: uart@4006d000 {
compatible = "nxp,k64f-uart";
reg = <0x4006d000 0x1000>;
interrupts = <37>, <38>;
interrupts = <37 0>, <38 0>;
interrupt-names = "status", "error";
zephyr,irq-prio = <0>;
status = "disabled";
};
@ -114,9 +110,8 @@
uart4: uart@400ea000 {
compatible = "nxp,k64f-uart";
reg = <0x400ea000 0x1000>;
interrupts = <66>, <67>;
interrupts = <66 0>, <67 0>;
interrupt-names = "status", "error";
zephyr,irq-prio = <0>;
status = "disabled";
};
@ -124,9 +119,8 @@
uart5: uart@400eb000 {
compatible = "nxp,k64f-uart";
reg = <0x400eb000 0x1000>;
interrupts = <68>, <69>;
interrupts = <68 0>, <69 0>;
interrupt-names = "status", "error";
zephyr,irq-prio = <0>;
status = "disabled";
};
@ -186,8 +180,7 @@
gpioa: gpio@400ff000 {
compatible = "nxp,k64f-gpio";
reg = <0x400ff000 0x40>;
interrupts = <59>;
zephyr,irq-prio = <2>;
interrupts = <59 2>;
gpio-controller;
#gpio-cells = <2>;
@ -196,9 +189,8 @@
gpiob: gpio@400ff040 {
compatible = "nxp,k64f-gpio";
reg = <0x400ff040 0x40>;
interrupts = <60>;
interrupts = <60 2>;
zephyr,irq-prio = <2>;
gpio-controller;
#gpio-cells = <2>;
};
@ -206,9 +198,8 @@
gpioc: gpio@400ff080 {
compatible = "nxp,k64f-gpio";
reg = <0x400ff080 0x40>;
interrupts = <61>;
interrupts = <61 2>;
zephyr,irq-prio = <2>;
gpio-controller;
#gpio-cells = <2>;
};
@ -216,8 +207,7 @@
gpiod: gpio@400ff0c0 {
compatible = "nxp,k64f-gpio";
reg = <0x400ff0c0 0x40>;
interrupts = <62>;
zephyr,irq-prio = <2>;
interrupts = <62 2>;
gpio-controller;
#gpio-cells = <2>;
@ -226,8 +216,7 @@
gpioe: gpio@400ff100 {
compatible = "nxp,k64f-gpio";
reg = <0x400ff100 0x40>;
interrupts = <63>;
zephyr,irq-prio = <2>;
interrupts = <63 2>;
gpio-controller;
#gpio-cells = <2>;
@ -236,7 +225,7 @@
spi0: spi@4002c000 {
compatible = "nxp,k64f-spi";
reg = <0x4002c000 0x88>;
interrupts = <26>;
interrupts = <26 0>;
clocks = <&sim 0x103C 12>; /* clk gate */
cs = <&gpiob 10 0>, <&gpiob 9 0>;
@ -247,7 +236,7 @@
spi1: spi@4002d000 {
compatible = "nxp,k64f-spi";
reg = <0x4002d000 0x88>;
interrupts = <0>;
interrupts = <0 0>;
clocks = <&sim 0x103C 13>; /* clk gate */
status = "disabled";
};

16
dts/arm/nxp_kw41z.dtsi
View file

@ -47,8 +47,7 @@
lpuart0: lpuart@40054000 {
compatible = "nxp,kw41z-lpuart";
reg = <0x40054000 0x18>;
interrupts = <12>;
zephyr,irq-prio = <0>;
interrupts = <12 0>;
baud-rate = <115200>;
pinctrl-0 = <&lpuart0_default>;
@ -113,8 +112,7 @@
gpioa: gpio@400ff000 {
compatible = "nxp,kw41z-gpio";
reg = <0x400ff000 0x40>;
interrupts = <30>;
zephyr,irq-prio = <2>;
interrupts = <30 2>;
gpio-controller;
#gpio-cells = <2>;
};
@ -122,8 +120,7 @@
gpiob: gpio@400ff040 {
compatible = "nxp,kw41z-gpio";
reg = <0x400ff040 0x40>;
interrupts = <31>;
zephyr,irq-prio = <2>;
interrupts = <31 2>;
gpio-controller;
#gpio-cells = <2>;
};
@ -131,8 +128,7 @@
gpioc: gpio@400ff080 {
compatible = "nxp,kw41z-gpio";
reg = <0x400ff080 0x40>;
interrupts = <31>;
zephyr,irq-prio = <2>;
interrupts = <31 2>;
gpio-controller;
#gpio-cells = <2>;
};
@ -140,7 +136,7 @@
spi0: spi@4002c000 {
compatible = "nxp,kw41z-spi";
reg = <0x4002c000 0x9C>;
interrupts = <10>;
interrupts = <10 0>;
clocks = <&sim 0x103C 12>; /* clk gate */
cs = <&gpiob 18 0>, <&gpiob 17 0>;
@ -151,7 +147,7 @@
spi1: spi@4002d000 {
compatible = "nxp,kw41z-spi";
reg = <0x4002d000 0x9C>;
interrupts = <29>;
interrupts = <29 0>;
clocks = <&sim 0x103C 13>; /* clk gate */
status = "disabled";
};

6
dts/arm/olimexino_stm32.fixup
View file

@ -10,15 +10,15 @@
#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE
#define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40013800_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40013800_IRQ_0_PRIORITY
#define PORT_1_IRQ ST_STM32_USART_40013800_IRQ_0
#define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_BAUD_RATE
#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY
#define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0
#define CONFIG_UART_STM32_PORT_3_BASE_ADDRESS ST_STM32_USART_40004800_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_3_BAUD_RATE ST_STM32_USART_40004800_BAUD_RATE
#define CONFIG_UART_STM32_PORT_3_IRQ_PRI ST_STM32_USART_40004800_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_STM32_PORT_3_IRQ_PRI ST_STM32_USART_40004800_IRQ_0_PRIORITY
#define PORT_3_IRQ ST_STM32_USART_40004800_IRQ_0

9
dts/arm/stm32f103xb.dtsi
View file

@ -27,8 +27,7 @@
usart1: uart@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
interrupts = <37>;
zephyr,irq-prio = <0>;
interrupts = <37 0>;
baud-rate = <115200>;
status = "disabled";
};
@ -36,8 +35,7 @@
usart2: uart@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
zephyr,irq-prio = <0>;
interrupts = <38 0>;
baud-rate = <115200>;
status = "disabled";
};
@ -45,8 +43,7 @@
usart3: uart@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
interrupts = <39>;
zephyr,irq-prio = <0>;
interrupts = <39 0>;
baud-rate = <115200>;
status = "disabled";
};

15
dts/arm/stm32l476.dtsi
View file

@ -20,8 +20,7 @@
usart1: uart@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
interrupts = <37>;
zephyr,irq-prio = <0>;
interrupts = <37 0>;
baud-rate = <115200>;
status = "disabled";
};
@ -29,8 +28,7 @@
usart2: uart@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
zephyr,irq-prio = <0>;
interrupts = <38 0>;
baud-rate = <115200>;
status = "disabled";
};
@ -38,8 +36,7 @@
usart3: uart@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
interrupts = <39>;
zephyr,irq-prio = <0>;
interrupts = <39 0>;
baud-rate = <115200>;
status = "disabled";
};
@ -47,8 +44,7 @@
uart4: uart@40004c00 {
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
interrupts = <52>;
zephyr,irq-prio = <0>;
interrupts = <52 0>;
baud-rate = <115200>;
status = "disabled";
};
@ -56,8 +52,7 @@
uart5: uart@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
interrupts = <53>;
zephyr,irq-prio = <0>;
interrupts = <53 0>;
baud-rate = <115200>;
status = "disabled";
};

6
dts/arm/v2m_beetle.dts
View file

@ -33,16 +33,14 @@
uart0: uart@40004000 {
compatible = "arm,cmsdk-uart";
reg = <0x40004000 0x14>;
interrupts = <IRQ_UART0>;
zephyr,irq-prio = <3>;
interrupts = <IRQ_UART0 3>;
baud-rate = <115200>;
};
uart1: uart@40005000 {
compatible = "arm,cmsdk-uart";
reg = <0x40005000 0x14>;
interrupts = <IRQ_UART1>;
zephyr,irq-prio = <3>;
interrupts = <IRQ_UART1 3>;
baud-rate = <115200>;
};
};

4
dts/arm/v2m_beetle.fixup
View file

@ -2,9 +2,9 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
#define CMSDK_APB_UART_0_IRQ ARM_CMSDK_UART_40004000_IRQ_0
#define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI ARM_CMSDK_UART_40004000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY
#define CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE ARM_CMSDK_UART_40004000_BAUD_RATE
#define CMSDK_APB_UART_1_IRQ ARM_CMSDK_UART_40005000_IRQ_0
#define CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI ARM_CMSDK_UART_40005000_ZEPHYR_IRQ_PRIO
#define CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI ARM_CMSDK_UART_40005000_IRQ_0_PRIORITY
#define CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE ARM_CMSDK_UART_40005000_BAUD_RATE

1
dts/arm/yaml/arm,armv6m-nvic.yaml
View file

@ -34,4 +34,5 @@ cell_string: IRQ
"#cells":
- irq
- priority
...

1
dts/arm/yaml/arm,cmsdk-uart.yaml
View file

@ -8,7 +8,6 @@ description: >
inherits:
- !include uart.yaml
- !include zephyr_devices.yaml
properties:
- compatible:

1
dts/arm/yaml/arm_cortex_m4_nvic.yaml
View file

@ -34,4 +34,5 @@ cell_string: IRQ
"#cells":
- irq
- priority
...

1
dts/arm/yaml/k64uart.yaml
View file

@ -8,7 +8,6 @@ description: >
inherits:
- !include uart.yaml
- !include zephyr_devices.yaml
properties:
- compatible:

1
dts/arm/yaml/nxp,kw41z-lpuart.yaml
View file

@ -8,7 +8,6 @@ description: >
inherits:
- !include uart.yaml
- !include zephyr_devices.yaml
properties:
- compatible:

1
dts/arm/yaml/st,stm32-usart.yaml
View file

@ -8,7 +8,6 @@ description: >
inherits:
- !include uart.yaml
- !include zephyr_devices.yaml
properties:
- compatible:

1
dts/arm/yaml/ti,cc32xx-uart.yaml
View file

@ -8,7 +8,6 @@ description: >
inherits:
- !include uart.yaml
- !include zephyr_devices.yaml
properties:
- compatible:

14
dts/common/yaml/zephyr_devices.yaml
View file

@ -1,14 +0,0 @@
---
title: Zephyr Device Specific Properties
version: 0.1
description: >
This binding describes Zephyr device specific properties
properties:
- zephyr,irq-prio:
category: optional
type: int
description: priority setting
generation: define
...