dts: arm: Put IRQ priority into the interrupt property
Rather than having a zephyr specific property we will encode the IRQ priority as part of the interrupt property for ARM NVIC based interrupt controllers. Change-Id: I7d1489f0bffa7a6369f0622f748bb70dc83fa0cd Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
parent
7bcbd6133a
commit
94107bc71d
23 changed files with 60 additions and 104 deletions
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@ -12,7 +12,7 @@
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compatible = "arm,armv6m-nvic";
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reg = <0xe000e100 0xc00>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#interrupt-cells = <2>;
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};
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systick: timer@e000e010 {
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@ -12,7 +12,7 @@
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compatible = "arm,armv7m-nvic";
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reg = <0xe000e100 0xc00>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#interrupt-cells = <2>;
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};
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systick: timer@e000e010 {
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@ -2,6 +2,6 @@
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define EXCEPTION_UARTA0 TI_CC32XX_UART_4000C000_IRQ_0
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#define CONFIG_UART_CC32XX_IRQ_PRI TI_CC32XX_UART_4000C000_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_CC32XX_IRQ_PRI TI_CC32XX_UART_4000C000_IRQ_0_PRIORITY
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#define UART_CC32XX_BASE_ADDRESS TI_CC32XX_UART_4000C000_BASE_ADDRESS
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#define CONFIG_UART_CC32XX_BAUDRATE TI_CC32XX_UART_4000C000_BAUD_RATE
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@ -28,8 +28,7 @@
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uart0: uart@UARTA0_BASE {
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compatible = "ti,cc32xx-uart";
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reg = <UARTA0_BASE 0x4c>;
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interrupts = <EXP_UARTA0>;
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zephyr,irq-prio = <3>;
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interrupts = <EXP_UARTA0 3>;
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baud-rate = <115200>;
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status = "disabled";
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};
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@ -37,8 +36,7 @@
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uart1: uart@UARTA1_BASE {
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compatible = "ti,cc32xx-uart";
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reg = <UARTA1_BASE 0x4c>;
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interrupts = <EXP_UARTA1>;
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zephyr,irq-prio = <3>;
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interrupts = <EXP_UARTA1 3>;
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baud-rate = <115200>;
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status = "disabled";
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};
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@ -2,19 +2,19 @@
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE
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#define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_IRQ_0_PRIORITY
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#define CONFIG_UART_MCUX_1_BAUD_RATE NXP_K64F_UART_4006B000_BAUD_RATE
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#define CONFIG_UART_MCUX_1_IRQ_PRI NXP_K64F_UART_4006B000_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_MCUX_1_IRQ_PRI NXP_K64F_UART_4006B000_IRQ_0_PRIORITY
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#define CONFIG_UART_MCUX_2_BAUD_RATE NXP_K64F_UART_4006C000_BAUD_RATE
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#define CONFIG_UART_MCUX_2_IRQ_PRI NXP_K64F_UART_4006C000_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_MCUX_2_IRQ_PRI NXP_K64F_UART_4006C000_IRQ_0_PRIORITY
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#define CONFIG_UART_MCUX_3_BAUD_RATE NXP_K64F_UART_4006D000_BAUD_RATE
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#define CONFIG_UART_MCUX_3_IRQ_PRI NXP_K64F_UART_4006D000_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_MCUX_3_IRQ_PRI NXP_K64F_UART_4006D000_IRQ_0_PRIORITY
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#define CONFIG_UART_MCUX_4_BAUD_RATE NXP_K64F_UART_400EA000_BAUD_RATE
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#define CONFIG_UART_MCUX_4_IRQ_PRI NXP_K64F_UART_400EA000_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_MCUX_4_IRQ_PRI NXP_K64F_UART_400EA000_IRQ_0_PRIORITY
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#define CONFIG_UART_MCUX_5_BAUD_RATE NXP_K64F_UART_400EB000_BAUD_RATE
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#define CONFIG_UART_MCUX_5_IRQ_PRI NXP_K64F_UART_400EB000_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_MCUX_5_IRQ_PRI NXP_K64F_UART_400EB000_IRQ_0_PRIORITY
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@ -2,4 +2,4 @@
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV6M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define CONFIG_UART_MCUX_LPUART_0_BAUD_RATE NXP_KW41Z_LPUART_40054000_BAUD_RATE
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#define CONFIG_UART_MCUX_LPUART_0_IRQ_PRI NXP_KW41Z_LPUART_40054000_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_MCUX_LPUART_0_IRQ_PRI NXP_KW41Z_LPUART_40054000_IRQ_0_PRIORITY
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@ -2,19 +2,19 @@
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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#define CONFIG_UART_MCUX_0_BAUD_RATE NXP_K64F_UART_4006A000_BAUD_RATE
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#define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_MCUX_0_IRQ_PRI NXP_K64F_UART_4006A000_IRQ_0_PRIORITY
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#define CONFIG_UART_MCUX_1_BAUD_RATE NXP_K64F_UART_4006B000_BAUD_RATE
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#define CONFIG_UART_MCUX_1_IRQ_PRI NXP_K64F_UART_4006B000_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_MCUX_1_IRQ_PRI NXP_K64F_UART_4006B000_IRQ_0_PRIORITY
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#define CONFIG_UART_MCUX_2_BAUD_RATE NXP_K64F_UART_4006C000_BAUD_RATE
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#define CONFIG_UART_MCUX_2_IRQ_PRI NXP_K64F_UART_4006C000_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_MCUX_2_IRQ_PRI NXP_K64F_UART_4006C000_IRQ_0_PRIORITY
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#define CONFIG_UART_MCUX_3_BAUD_RATE NXP_K64F_UART_4006D000_BAUD_RATE
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#define CONFIG_UART_MCUX_3_IRQ_PRI NXP_K64F_UART_4006D000_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_MCUX_3_IRQ_PRI NXP_K64F_UART_4006D000_IRQ_0_PRIORITY
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#define CONFIG_UART_MCUX_4_BAUD_RATE NXP_K64F_UART_400EA000_BAUD_RATE
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#define CONFIG_UART_MCUX_4_IRQ_PRI NXP_K64F_UART_400EA000_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_MCUX_4_IRQ_PRI NXP_K64F_UART_400EA000_IRQ_0_PRIORITY
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#define CONFIG_UART_MCUX_5_BAUD_RATE NXP_K64F_UART_400EB000_BAUD_RATE
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#define CONFIG_UART_MCUX_5_IRQ_PRI NXP_K64F_UART_400EB000_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_MCUX_5_IRQ_PRI NXP_K64F_UART_400EB000_IRQ_0_PRIORITY
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@ -10,25 +10,25 @@
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#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS
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#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE
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#define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40013800_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40013800_IRQ_0_PRIORITY
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#define PORT_1_IRQ ST_STM32_USART_40013800_IRQ_0
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#define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS
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#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_BAUD_RATE
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#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY
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#define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0
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#define CONFIG_UART_STM32_PORT_3_BASE_ADDRESS ST_STM32_USART_40004800_BASE_ADDRESS
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#define CONFIG_UART_STM32_PORT_3_BAUD_RATE ST_STM32_USART_40004800_BAUD_RATE
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#define CONFIG_UART_STM32_PORT_3_IRQ_PRI ST_STM32_USART_40004800_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_STM32_PORT_3_IRQ_PRI ST_STM32_USART_40004800_IRQ_0_PRIORITY
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#define PORT_3_IRQ ST_STM32_USART_40004800_IRQ_0
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#define CONFIG_UART_STM32_PORT_4_BASE_ADDRESS ST_STM32_USART_40004C00_BASE_ADDRESS
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#define CONFIG_UART_STM32_PORT_4_BAUD_RATE ST_STM32_USART_40004C00_BAUD_RATE
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#define CONFIG_UART_STM32_PORT_4_IRQ_PRI ST_STM32_USART_40004C00_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_STM32_PORT_4_IRQ_PRI ST_STM32_USART_40004C00_IRQ_0_PRIORITY
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#define PORT_4_IRQ ST_STM32_USART_40004C00_IRQ_0
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#define CONFIG_UART_STM32_PORT_5_BASE_ADDRESS ST_STM32_USART_40005000_BASE_ADDRESS
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#define CONFIG_UART_STM32_PORT_5_BAUD_RATE ST_STM32_USART_40005000_BAUD_RATE
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#define CONFIG_UART_STM32_PORT_5_IRQ_PRI ST_STM32_USART_40005000_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_STM32_PORT_5_IRQ_PRI ST_STM32_USART_40005000_IRQ_0_PRIORITY
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#define PORT_5_IRQ ST_STM32_USART_40005000_IRQ_0
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@ -58,7 +58,7 @@
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flash-controller@4001f000 {
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compatible = "nxp,k64f-flash-controller";
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reg = <0x4001f000 0x27c>;
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interrupts = <18>, <19>;
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interrupts = <18 0>, <19 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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@ -71,9 +71,8 @@
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uart0: uart@4006a000 {
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compatible = "nxp,k64f-uart";
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reg = <0x4006a000 0x1000>;
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interrupts = <31>, <32>;
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interrupts = <31 0>, <32 0>;
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interrupt-names = "status", "error";
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zephyr,irq-prio = <0>;
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pinctrl-0 = <&uart0_default>;
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pinctrl-names = "default";
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uart1: uart@4006b000 {
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compatible = "nxp,k64f-uart";
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reg = <0x4006b000 0x1000>;
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interrupts = <33>, <34>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "status", "error";
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zephyr,irq-prio = <0>;
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status = "disabled";
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};
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uart2: uart@4006c000 {
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compatible = "nxp,k64f-uart";
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reg = <0x4006c000 0x1000>;
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interrupts = <35>, <36>;
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interrupts = <35 0>, <36 0>;
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interrupt-names = "status", "error";
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zephyr,irq-prio = <0>;
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status = "disabled";
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};
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uart3: uart@4006d000 {
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compatible = "nxp,k64f-uart";
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reg = <0x4006d000 0x1000>;
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interrupts = <37>, <38>;
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interrupts = <37 0>, <38 0>;
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interrupt-names = "status", "error";
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zephyr,irq-prio = <0>;
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status = "disabled";
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};
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@ -114,9 +110,8 @@
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uart4: uart@400ea000 {
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compatible = "nxp,k64f-uart";
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reg = <0x400ea000 0x1000>;
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interrupts = <66>, <67>;
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interrupts = <66 0>, <67 0>;
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interrupt-names = "status", "error";
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zephyr,irq-prio = <0>;
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status = "disabled";
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};
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uart5: uart@400eb000 {
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compatible = "nxp,k64f-uart";
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reg = <0x400eb000 0x1000>;
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interrupts = <68>, <69>;
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interrupts = <68 0>, <69 0>;
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interrupt-names = "status", "error";
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zephyr,irq-prio = <0>;
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status = "disabled";
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};
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gpioa: gpio@400ff000 {
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compatible = "nxp,k64f-gpio";
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reg = <0x400ff000 0x40>;
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interrupts = <59>;
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zephyr,irq-prio = <2>;
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interrupts = <59 2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpiob: gpio@400ff040 {
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compatible = "nxp,k64f-gpio";
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reg = <0x400ff040 0x40>;
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interrupts = <60>;
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interrupts = <60 2>;
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zephyr,irq-prio = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioc: gpio@400ff080 {
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compatible = "nxp,k64f-gpio";
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reg = <0x400ff080 0x40>;
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interrupts = <61>;
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interrupts = <61 2>;
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zephyr,irq-prio = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpiod: gpio@400ff0c0 {
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compatible = "nxp,k64f-gpio";
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reg = <0x400ff0c0 0x40>;
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interrupts = <62>;
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zephyr,irq-prio = <2>;
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interrupts = <62 2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpioe: gpio@400ff100 {
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compatible = "nxp,k64f-gpio";
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reg = <0x400ff100 0x40>;
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interrupts = <63>;
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zephyr,irq-prio = <2>;
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interrupts = <63 2>;
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gpio-controller;
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#gpio-cells = <2>;
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spi0: spi@4002c000 {
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compatible = "nxp,k64f-spi";
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reg = <0x4002c000 0x88>;
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interrupts = <26>;
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interrupts = <26 0>;
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clocks = <&sim 0x103C 12>; /* clk gate */
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cs = <&gpiob 10 0>, <&gpiob 9 0>;
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spi1: spi@4002d000 {
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compatible = "nxp,k64f-spi";
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reg = <0x4002d000 0x88>;
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interrupts = <0>;
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interrupts = <0 0>;
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clocks = <&sim 0x103C 13>; /* clk gate */
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status = "disabled";
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};
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lpuart0: lpuart@40054000 {
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compatible = "nxp,kw41z-lpuart";
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reg = <0x40054000 0x18>;
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interrupts = <12>;
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zephyr,irq-prio = <0>;
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interrupts = <12 0>;
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baud-rate = <115200>;
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pinctrl-0 = <&lpuart0_default>;
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gpioa: gpio@400ff000 {
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compatible = "nxp,kw41z-gpio";
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reg = <0x400ff000 0x40>;
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interrupts = <30>;
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zephyr,irq-prio = <2>;
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interrupts = <30 2>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpiob: gpio@400ff040 {
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compatible = "nxp,kw41z-gpio";
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reg = <0x400ff040 0x40>;
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interrupts = <31>;
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zephyr,irq-prio = <2>;
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interrupts = <31 2>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioc: gpio@400ff080 {
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compatible = "nxp,kw41z-gpio";
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reg = <0x400ff080 0x40>;
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interrupts = <31>;
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zephyr,irq-prio = <2>;
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interrupts = <31 2>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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spi0: spi@4002c000 {
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compatible = "nxp,kw41z-spi";
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reg = <0x4002c000 0x9C>;
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interrupts = <10>;
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interrupts = <10 0>;
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clocks = <&sim 0x103C 12>; /* clk gate */
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cs = <&gpiob 18 0>, <&gpiob 17 0>;
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spi1: spi@4002d000 {
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compatible = "nxp,kw41z-spi";
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reg = <0x4002d000 0x9C>;
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interrupts = <29>;
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interrupts = <29 0>;
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clocks = <&sim 0x103C 13>; /* clk gate */
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status = "disabled";
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};
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#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS
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#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE
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#define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40013800_ZEPHYR_IRQ_PRIO
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#define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40013800_IRQ_0_PRIORITY
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#define PORT_1_IRQ ST_STM32_USART_40013800_IRQ_0
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#define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS
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#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_BAUD_RATE
|
||||
#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_ZEPHYR_IRQ_PRIO
|
||||
#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY
|
||||
#define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0
|
||||
|
||||
#define CONFIG_UART_STM32_PORT_3_BASE_ADDRESS ST_STM32_USART_40004800_BASE_ADDRESS
|
||||
#define CONFIG_UART_STM32_PORT_3_BAUD_RATE ST_STM32_USART_40004800_BAUD_RATE
|
||||
#define CONFIG_UART_STM32_PORT_3_IRQ_PRI ST_STM32_USART_40004800_ZEPHYR_IRQ_PRIO
|
||||
#define CONFIG_UART_STM32_PORT_3_IRQ_PRI ST_STM32_USART_40004800_IRQ_0_PRIORITY
|
||||
#define PORT_3_IRQ ST_STM32_USART_40004800_IRQ_0
|
||||
|
|
|
@ -27,8 +27,7 @@
|
|||
usart1: uart@40013800 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40013800 0x400>;
|
||||
interrupts = <37>;
|
||||
zephyr,irq-prio = <0>;
|
||||
interrupts = <37 0>;
|
||||
baud-rate = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -36,8 +35,7 @@
|
|||
usart2: uart@40004400 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004400 0x400>;
|
||||
interrupts = <38>;
|
||||
zephyr,irq-prio = <0>;
|
||||
interrupts = <38 0>;
|
||||
baud-rate = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -45,8 +43,7 @@
|
|||
usart3: uart@40004800 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004800 0x400>;
|
||||
interrupts = <39>;
|
||||
zephyr,irq-prio = <0>;
|
||||
interrupts = <39 0>;
|
||||
baud-rate = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
@ -20,8 +20,7 @@
|
|||
usart1: uart@40013800 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40013800 0x400>;
|
||||
interrupts = <37>;
|
||||
zephyr,irq-prio = <0>;
|
||||
interrupts = <37 0>;
|
||||
baud-rate = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -29,8 +28,7 @@
|
|||
usart2: uart@40004400 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004400 0x400>;
|
||||
interrupts = <38>;
|
||||
zephyr,irq-prio = <0>;
|
||||
interrupts = <38 0>;
|
||||
baud-rate = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -38,8 +36,7 @@
|
|||
usart3: uart@40004800 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004800 0x400>;
|
||||
interrupts = <39>;
|
||||
zephyr,irq-prio = <0>;
|
||||
interrupts = <39 0>;
|
||||
baud-rate = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -47,8 +44,7 @@
|
|||
uart4: uart@40004c00 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40004c00 0x400>;
|
||||
interrupts = <52>;
|
||||
zephyr,irq-prio = <0>;
|
||||
interrupts = <52 0>;
|
||||
baud-rate = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -56,8 +52,7 @@
|
|||
uart5: uart@40005000 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40005000 0x400>;
|
||||
interrupts = <53>;
|
||||
zephyr,irq-prio = <0>;
|
||||
interrupts = <53 0>;
|
||||
baud-rate = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
@ -33,16 +33,14 @@
|
|||
uart0: uart@40004000 {
|
||||
compatible = "arm,cmsdk-uart";
|
||||
reg = <0x40004000 0x14>;
|
||||
interrupts = <IRQ_UART0>;
|
||||
zephyr,irq-prio = <3>;
|
||||
interrupts = <IRQ_UART0 3>;
|
||||
baud-rate = <115200>;
|
||||
};
|
||||
|
||||
uart1: uart@40005000 {
|
||||
compatible = "arm,cmsdk-uart";
|
||||
reg = <0x40005000 0x14>;
|
||||
interrupts = <IRQ_UART1>;
|
||||
zephyr,irq-prio = <3>;
|
||||
interrupts = <IRQ_UART1 3>;
|
||||
baud-rate = <115200>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -2,9 +2,9 @@
|
|||
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
|
||||
|
||||
#define CMSDK_APB_UART_0_IRQ ARM_CMSDK_UART_40004000_IRQ_0
|
||||
#define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI ARM_CMSDK_UART_40004000_ZEPHYR_IRQ_PRIO
|
||||
#define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY
|
||||
#define CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE ARM_CMSDK_UART_40004000_BAUD_RATE
|
||||
|
||||
#define CMSDK_APB_UART_1_IRQ ARM_CMSDK_UART_40005000_IRQ_0
|
||||
#define CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI ARM_CMSDK_UART_40005000_ZEPHYR_IRQ_PRIO
|
||||
#define CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI ARM_CMSDK_UART_40005000_IRQ_0_PRIORITY
|
||||
#define CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE ARM_CMSDK_UART_40005000_BAUD_RATE
|
||||
|
|
|
@ -34,4 +34,5 @@ cell_string: IRQ
|
|||
|
||||
"#cells":
|
||||
- irq
|
||||
- priority
|
||||
...
|
||||
|
|
|
@ -8,7 +8,6 @@ description: >
|
|||
|
||||
inherits:
|
||||
- !include uart.yaml
|
||||
- !include zephyr_devices.yaml
|
||||
|
||||
properties:
|
||||
- compatible:
|
||||
|
|
|
@ -34,4 +34,5 @@ cell_string: IRQ
|
|||
|
||||
"#cells":
|
||||
- irq
|
||||
- priority
|
||||
...
|
||||
|
|
|
@ -8,7 +8,6 @@ description: >
|
|||
|
||||
inherits:
|
||||
- !include uart.yaml
|
||||
- !include zephyr_devices.yaml
|
||||
|
||||
properties:
|
||||
- compatible:
|
||||
|
|
|
@ -8,7 +8,6 @@ description: >
|
|||
|
||||
inherits:
|
||||
- !include uart.yaml
|
||||
- !include zephyr_devices.yaml
|
||||
|
||||
properties:
|
||||
- compatible:
|
||||
|
|
|
@ -8,7 +8,6 @@ description: >
|
|||
|
||||
inherits:
|
||||
- !include uart.yaml
|
||||
- !include zephyr_devices.yaml
|
||||
|
||||
properties:
|
||||
- compatible:
|
||||
|
|
|
@ -8,7 +8,6 @@ description: >
|
|||
|
||||
inherits:
|
||||
- !include uart.yaml
|
||||
- !include zephyr_devices.yaml
|
||||
|
||||
properties:
|
||||
- compatible:
|
||||
|
|
|
@ -1,14 +0,0 @@
|
|||
---
|
||||
title: Zephyr Device Specific Properties
|
||||
version: 0.1
|
||||
|
||||
description: >
|
||||
This binding describes Zephyr device specific properties
|
||||
|
||||
properties:
|
||||
- zephyr,irq-prio:
|
||||
category: optional
|
||||
type: int
|
||||
description: priority setting
|
||||
generation: define
|
||||
...
|
Loading…
Add table
Add a link
Reference in a new issue