arch: Add imx6sx m4 soc support
The i.MX 6SoloX SoC is a hybrid multi-core processor composed by one Cortex A9 core and one Cortex M4 core. Zephyr was ported to run on the M4 core. In a later release, it will also communicate with the A9 core (running Linux) via RPMsg. The low level drivers come from NXP FreeRTOS BSP and are located at ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README The A9 core is responsible to load the M4 binary application into the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get the M4 out of reset. The A9 can perform these steps at bootloader level after the Linux system has booted. Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
This commit is contained in:
Stanislav Poboril
Maureen Helm
parent
1112f25274
commit
631eedd334
12 changed files with 713 additions and 0 deletions
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@ -20,6 +20,8 @@ gsource "arch/arm/soc/nxp_imx/*/Kconfig.soc"
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config SOC_PART_NUMBER
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string
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default SOC_PART_NUMBER_IMX_RT if SOC_SERIES_IMX_RT
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default SOC_PART_NUMBER_IMX_6X_M4 if SOC_SERIES_IMX_6X_M4
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default SOC_PART_NUMBER_IMX7_M4 if SOC_SERIES_IMX7_M4
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help
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This string holds the full part number of the SoC. It is a hidden option
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that you should not set directly. The part number selection choice defines
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7
arch/arm/soc/nxp_imx/mcimx6x_m4/CMakeLists.txt
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7
arch/arm/soc/nxp_imx/mcimx6x_m4/CMakeLists.txt
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@ -0,0 +1,7 @@
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#
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# Copyright (c) 2018, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_sources(soc.c)
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39
arch/arm/soc/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4
Normal file
39
arch/arm/soc/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4
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@ -0,0 +1,39 @@
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# Kconfig - i.MX 6SoloX
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#
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# Copyright (c) 2018, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_MCIMX6X_M4
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config SOC
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string
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default "mcimx6x"
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if CLOCK_CONTROL
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config CLOCK_CONTROL_IMX_CCM
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def_bool y
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endif # CLOCK_CONTROL
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if GPIO
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config GPIO_IMX
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def_bool y
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endif # GPIO
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if SERIAL
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config UART_IMX
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def_bool y
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endif # SERIAL
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config DOMAIN_ID
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int
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default 1
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endif # SOC_MCIMX6X_M4
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20
arch/arm/soc/nxp_imx/mcimx6x_m4/Kconfig.defconfig.series
Normal file
20
arch/arm/soc/nxp_imx/mcimx6x_m4/Kconfig.defconfig.series
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@ -0,0 +1,20 @@
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# Kconfig - i.MX 6SoloX M4 core series
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#
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# Copyright (c) 2018, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_SERIES_IMX_6X_M4
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config SOC_SERIES
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default "mcimx6x_m4"
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config NUM_IRQS
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int
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# must be >= the highest interrupt number used
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default 128
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source "arch/arm/soc/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4"
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endif # SOC_SERIES_IMX_6X_M4
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19
arch/arm/soc/nxp_imx/mcimx6x_m4/Kconfig.series
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arch/arm/soc/nxp_imx/mcimx6x_m4/Kconfig.series
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@ -0,0 +1,19 @@
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# Kconfig - i.MX 6SoloX M4 core series
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#
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# Copyright (c) 2018, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_SERIES_IMX_6X_M4
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bool "i.MX 6SoloX M4 Core Series"
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select CPU_CORTEX_M
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select CPU_CORTEX_M4
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select HAS_IMX_HAL
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select SOC_FAMILY_IMX
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select SYS_POWER_LOW_POWER_STATE_SUPPORTED
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select CPU_HAS_FPU
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select CPU_HAS_SYSTICK
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select CLOCK_CONTROL
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help
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Enable support for M4 core of i.MX 6SoloX MCU series
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84
arch/arm/soc/nxp_imx/mcimx6x_m4/Kconfig.soc
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84
arch/arm/soc/nxp_imx/mcimx6x_m4/Kconfig.soc
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@ -0,0 +1,84 @@
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# Kconfig - i.MX 6SoloX M4 core series
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#
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# Copyright (c) 2018, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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choice
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prompt "i.MX 6SoloX Selection"
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depends on SOC_SERIES_IMX_6X_M4
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config SOC_MCIMX6X_M4
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bool "SOC_MCIMX6X_M4"
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select HAS_IMX_HAL
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select HAS_IMX_GPIO
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endchoice
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if SOC_SERIES_IMX_6X_M4
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config SOC_PART_NUMBER_MCIMX6X1EVK10AB
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bool
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config SOC_PART_NUMBER_MCIMX6X1EVK10AC
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bool
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config SOC_PART_NUMBER_MCIMX6X3EVK10AB
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bool
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config SOC_PART_NUMBER_MCIMX6X3EVK10AC
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bool
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config SOC_PART_NUMBER_MCIMX6X1EVO10AB
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bool
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config SOC_PART_NUMBER_MCIMX6X1EVO10AC
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bool
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config SOC_PART_NUMBER_MCIMX6X3EVO10AB
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bool
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config SOC_PART_NUMBER_MCIMX6X3EVO10AC
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bool
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config SOC_PART_NUMBER_MCIMX6X2EVN10AB
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bool
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config SOC_PART_NUMBER_MCIMX6X2EVN10AC
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bool
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config SOC_PART_NUMBER_MCIMX6X3EVN10AB
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bool
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config SOC_PART_NUMBER_MCIMX6X3EVN10AC
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bool
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config SOC_PART_NUMBER_MCIMX6X4EVM10AB
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bool
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config SOC_PART_NUMBER_MCIMX6X4EVM10AC
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bool
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config SOC_PART_NUMBER_IMX_6X_M4
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string
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default "MCIMX6X1EVK10AB" if SOC_PART_NUMBER_MCIMX6X1EVK10AB
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default "MCIMX6X1EVK10AC" if SOC_PART_NUMBER_MCIMX6X1EVK10AC
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default "MCIMX6X3EVK10AB" if SOC_PART_NUMBER_MCIMX6X3EVK10AB
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default "MCIMX6X3EVK10AC" if SOC_PART_NUMBER_MCIMX6X3EVK10AC
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default "MCIMX6X1EVO10AB" if SOC_PART_NUMBER_MCIMX6X1EVO10AB
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default "MCIMX6X1EVO10AC" if SOC_PART_NUMBER_MCIMX6X1EVO10AC
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default "MCIMX6X3EVO10AB" if SOC_PART_NUMBER_MCIMX6X3EVO10AB
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default "MCIMX6X3EVO10AC" if SOC_PART_NUMBER_MCIMX6X3EVO10AC
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default "MCIMX6X2EVN10AB" if SOC_PART_NUMBER_MCIMX6X2EVN10AB
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default "MCIMX6X2EVN10AC" if SOC_PART_NUMBER_MCIMX6X2EVN10AC
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default "MCIMX6X3EVN10AB" if SOC_PART_NUMBER_MCIMX6X3EVN10AB
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default "MCIMX6X3EVN10AC" if SOC_PART_NUMBER_MCIMX6X3EVN10AC
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default "MCIMX6X4EVM10AB" if SOC_PART_NUMBER_MCIMX6X4EVM10AB
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default "MCIMX6X4EVM10AC" if SOC_PART_NUMBER_MCIMX6X4EVM10AC
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help
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This string holds the full part number of the SoC. It is a hidden option
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that you should not set directly. The part number selection choice defines
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the default value for this string.
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endif # SOC_SERIES_IMX_6X_M4
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98
arch/arm/soc/nxp_imx/mcimx6x_m4/dts.fixup
Normal file
98
arch/arm/soc/nxp_imx/mcimx6x_m4/dts.fixup
Normal file
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@ -0,0 +1,98 @@
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/*
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* Copyright (c) 2018, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define CONFIG_GPIO_IMX_PORT_1_BASE_ADDRESS NXP_IMX_GPIO_4209C000_BASE_ADDRESS
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#define CONFIG_GPIO_IMX_PORT_1_NAME NXP_IMX_GPIO_4209C000_LABEL
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#define CONFIG_GPIO_IMX_PORT_1_IRQ_0 NXP_IMX_GPIO_4209C000_IRQ_0
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#define CONFIG_GPIO_IMX_PORT_1_IRQ_0_PRI NXP_IMX_GPIO_4209C000_IRQ_0_PRIORITY
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#define CONFIG_GPIO_IMX_PORT_1_IRQ_1 NXP_IMX_GPIO_4209C000_IRQ_1
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#define CONFIG_GPIO_IMX_PORT_1_IRQ_1_PRI NXP_IMX_GPIO_4209C000_IRQ_1_PRIORITY
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#define CONFIG_GPIO_IMX_PORT_2_BASE_ADDRESS NXP_IMX_GPIO_420A0000_BASE_ADDRESS
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#define CONFIG_GPIO_IMX_PORT_2_NAME NXP_IMX_GPIO_420A0000_LABEL
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#define CONFIG_GPIO_IMX_PORT_2_IRQ_0 NXP_IMX_GPIO_420A0000_IRQ_0
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#define CONFIG_GPIO_IMX_PORT_2_IRQ_0_PRI NXP_IMX_GPIO_420A0000_IRQ_0_PRIORITY
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#define CONFIG_GPIO_IMX_PORT_2_IRQ_1 NXP_IMX_GPIO_420A0000_IRQ_1
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#define CONFIG_GPIO_IMX_PORT_2_IRQ_1_PRI NXP_IMX_GPIO_420A0000_IRQ_1_PRIORITY
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#define CONFIG_GPIO_IMX_PORT_3_BASE_ADDRESS NXP_IMX_GPIO_420A4000_BASE_ADDRESS
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#define CONFIG_GPIO_IMX_PORT_3_NAME NXP_IMX_GPIO_420A4000_LABEL
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#define CONFIG_GPIO_IMX_PORT_3_IRQ_0 NXP_IMX_GPIO_420A4000_IRQ_0
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#define CONFIG_GPIO_IMX_PORT_3_IRQ_0_PRI NXP_IMX_GPIO_420A4000_IRQ_0_PRIORITY
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#define CONFIG_GPIO_IMX_PORT_3_IRQ_1 NXP_IMX_GPIO_420A4000_IRQ_1
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#define CONFIG_GPIO_IMX_PORT_3_IRQ_1_PRI NXP_IMX_GPIO_420A4000_IRQ_1_PRIORITY
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#define CONFIG_GPIO_IMX_PORT_4_BASE_ADDRESS NXP_IMX_GPIO_420A8000_BASE_ADDRESS
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#define CONFIG_GPIO_IMX_PORT_4_NAME NXP_IMX_GPIO_420A8000_LABEL
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#define CONFIG_GPIO_IMX_PORT_4_IRQ_0 NXP_IMX_GPIO_420A8000_IRQ_0
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#define CONFIG_GPIO_IMX_PORT_4_IRQ_0_PRI NXP_IMX_GPIO_420A8000_IRQ_0_PRIORITY
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#define CONFIG_GPIO_IMX_PORT_4_IRQ_1 NXP_IMX_GPIO_420A8000_IRQ_1
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#define CONFIG_GPIO_IMX_PORT_4_IRQ_1_PRI NXP_IMX_GPIO_420A8000_IRQ_1_PRIORITY
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#define CONFIG_GPIO_IMX_PORT_5_BASE_ADDRESS NXP_IMX_GPIO_420AC000_BASE_ADDRESS
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#define CONFIG_GPIO_IMX_PORT_5_NAME NXP_IMX_GPIO_420AC000_LABEL
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#define CONFIG_GPIO_IMX_PORT_5_IRQ_0 NXP_IMX_GPIO_420AC000_IRQ_0
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#define CONFIG_GPIO_IMX_PORT_5_IRQ_0_PRI NXP_IMX_GPIO_420AC000_IRQ_0_PRIORITY
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#define CONFIG_GPIO_IMX_PORT_5_IRQ_1 NXP_IMX_GPIO_420AC000_IRQ_1
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#define CONFIG_GPIO_IMX_PORT_5_IRQ_1_PRI NXP_IMX_GPIO_420AC000_IRQ_1_PRIORITY
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#define CONFIG_GPIO_IMX_PORT_6_BASE_ADDRESS NXP_IMX_GPIO_420B0000_BASE_ADDRESS
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#define CONFIG_GPIO_IMX_PORT_6_NAME NXP_IMX_GPIO_420B0000_LABEL
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#define CONFIG_GPIO_IMX_PORT_6_IRQ_0 NXP_IMX_GPIO_420B0000_IRQ_0
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#define CONFIG_GPIO_IMX_PORT_6_IRQ_0_PRI NXP_IMX_GPIO_420B0000_IRQ_0_PRIORITY
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#define CONFIG_GPIO_IMX_PORT_6_IRQ_1 NXP_IMX_GPIO_420B0000_IRQ_1
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#define CONFIG_GPIO_IMX_PORT_6_IRQ_1_PRI NXP_IMX_GPIO_420B0000_IRQ_1_PRIORITY
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#define CONFIG_GPIO_IMX_PORT_7_BASE_ADDRESS NXP_IMX_GPIO_420B4000_BASE_ADDRESS
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#define CONFIG_GPIO_IMX_PORT_7_NAME NXP_IMX_GPIO_420B4000_LABEL
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#define CONFIG_GPIO_IMX_PORT_7_IRQ_0 NXP_IMX_GPIO_420B4000_IRQ_0
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#define CONFIG_GPIO_IMX_PORT_7_IRQ_0_PRI NXP_IMX_GPIO_420B4000_IRQ_0_PRIORITY
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#define CONFIG_GPIO_IMX_PORT_7_IRQ_1 NXP_IMX_GPIO_420B4000_IRQ_1
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#define CONFIG_GPIO_IMX_PORT_7_IRQ_1_PRI NXP_IMX_GPIO_420B4000_IRQ_1_PRIORITY
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#define CONFIG_UART_IMX_UART_1_BASE_ADDRESS NXP_IMX_UART_42020000_BASE_ADDRESS
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#define CONFIG_UART_IMX_UART_1_NAME NXP_IMX_UART_42020000_LABEL
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#define CONFIG_UART_IMX_UART_1_IRQ_NUM NXP_IMX_UART_42020000_IRQ_0
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#define CONFIG_UART_IMX_UART_1_IRQ_PRI NXP_IMX_UART_42020000_IRQ_0_PRIORITY
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#define CONFIG_UART_IMX_UART_1_BAUD_RATE NXP_IMX_UART_42020000_CURRENT_SPEED
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#define CONFIG_UART_IMX_UART_1_MODEM_MODE NXP_IMX_UART_42020000_MODEM_MODE
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#define CONFIG_UART_IMX_UART_2_BASE_ADDRESS NXP_IMX_UART_421E8000_BASE_ADDRESS
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#define CONFIG_UART_IMX_UART_2_NAME NXP_IMX_UART_421E8000_LABEL
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#define CONFIG_UART_IMX_UART_2_IRQ_NUM NXP_IMX_UART_421E8000_IRQ_0
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#define CONFIG_UART_IMX_UART_2_IRQ_PRI NXP_IMX_UART_421E8000_IRQ_0_PRIORITY
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#define CONFIG_UART_IMX_UART_2_BAUD_RATE NXP_IMX_UART_421E8000_CURRENT_SPEED
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#define CONFIG_UART_IMX_UART_2_MODEM_MODE NXP_IMX_UART_421E8000_MODEM_MODE
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#define CONFIG_UART_IMX_UART_3_BASE_ADDRESS NXP_IMX_UART_421EC000_BASE_ADDRESS
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#define CONFIG_UART_IMX_UART_3_NAME NXP_IMX_UART_421EC000_LABEL
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#define CONFIG_UART_IMX_UART_3_IRQ_NUM NXP_IMX_UART_421EC000_IRQ_0
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#define CONFIG_UART_IMX_UART_3_IRQ_PRI NXP_IMX_UART_421EC000_IRQ_0_PRIORITY
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#define CONFIG_UART_IMX_UART_3_BAUD_RATE NXP_IMX_UART_421EC000_CURRENT_SPEED
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#define CONFIG_UART_IMX_UART_3_MODEM_MODE NXP_IMX_UART_421EC000_MODEM_MODE
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#define CONFIG_UART_IMX_UART_4_BASE_ADDRESS NXP_IMX_UART_421F0000_BASE_ADDRESS
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#define CONFIG_UART_IMX_UART_4_NAME NXP_IMX_UART_421F0000_LABEL
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#define CONFIG_UART_IMX_UART_4_IRQ_NUM NXP_IMX_UART_421F0000_IRQ_0
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#define CONFIG_UART_IMX_UART_4_IRQ_PRI NXP_IMX_UART_421F0000_IRQ_0_PRIORITY
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#define CONFIG_UART_IMX_UART_4_BAUD_RATE NXP_IMX_UART_421F0000_CURRENT_SPEED
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#define CONFIG_UART_IMX_UART_4_MODEM_MODE NXP_IMX_UART_421F0000_MODEM_MODE
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#define CONFIG_UART_IMX_UART_5_BASE_ADDRESS NXP_IMX_UART_421F4000_BASE_ADDRESS
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#define CONFIG_UART_IMX_UART_5_NAME NXP_IMX_UART_421F4000_LABEL
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#define CONFIG_UART_IMX_UART_5_IRQ_NUM NXP_IMX_UART_421F4000_IRQ_0
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#define CONFIG_UART_IMX_UART_5_IRQ_PRI NXP_IMX_UART_421F4000_IRQ_0_PRIORITY
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#define CONFIG_UART_IMX_UART_5_BAUD_RATE NXP_IMX_UART_421F4000_CURRENT_SPEED
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#define CONFIG_UART_IMX_UART_5_MODEM_MODE NXP_IMX_UART_421F4000_MODEM_MODE
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#define CONFIG_UART_IMX_UART_6_BASE_ADDRESS NXP_IMX_UART_422A0000_BASE_ADDRESS
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#define CONFIG_UART_IMX_UART_6_NAME NXP_IMX_UART_422A0000_LABEL
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#define CONFIG_UART_IMX_UART_6_IRQ_NUM NXP_IMX_UART_422A0000_IRQ_0
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#define CONFIG_UART_IMX_UART_6_IRQ_PRI NXP_IMX_UART_422A0000_IRQ_0_PRIORITY
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#define CONFIG_UART_IMX_UART_6_BAUD_RATE NXP_IMX_UART_422A0000_CURRENT_SPEED
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#define CONFIG_UART_IMX_UART_6_MODEM_MODE NXP_IMX_UART_422A0000_MODEM_MODE
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8
arch/arm/soc/nxp_imx/mcimx6x_m4/linker.ld
Normal file
8
arch/arm/soc/nxp_imx/mcimx6x_m4/linker.ld
Normal file
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <autoconf.h>
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#include <arch/arm/cortex_m/scripts/linker.ld>
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202
arch/arm/soc/nxp_imx/mcimx6x_m4/soc.c
Normal file
202
arch/arm/soc/nxp_imx/mcimx6x_m4/soc.c
Normal file
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/*
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* Copyright (c) 2018, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include <soc.h>
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#include <cortex_m/exc.h>
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#include "wdog_imx.h"
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/* Initialize Resource Domain Controller. */
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static void SOC_RdcInit(void)
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{
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/* Move M4 core to the configured RDC domain */
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RDC_SetDomainID(RDC, rdcMdaM4, CONFIG_DOMAIN_ID, false);
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/* Set access to WDOG3 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapWdog3,
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RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
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false, false);
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#ifdef CONFIG_UART_IMX_UART_1
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/* Set access to UART_1 for M4 core */
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RDC_SetPdapAccess(RDC, rdcPdapUart1,
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RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
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false, false);
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#endif /* CONFIG_UART_IMX_UART_1 */
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#ifdef CONFIG_UART_IMX_UART_2
|
||||
/* Set access to UART_2 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapUart2,
|
||||
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
|
||||
false, false);
|
||||
#endif /* CONFIG_UART_IMX_UART_2 */
|
||||
#ifdef CONFIG_UART_IMX_UART_3
|
||||
/* Set access to UART_3 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapUart3,
|
||||
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
|
||||
false, false);
|
||||
#endif /* CONFIG_UART_IMX_UART_3 */
|
||||
#ifdef CONFIG_UART_IMX_UART_4
|
||||
/* Set access to UART_4 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapUart4,
|
||||
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
|
||||
false, false);
|
||||
#endif /* CONFIG_UART_IMX_UART_4 */
|
||||
#ifdef CONFIG_UART_IMX_UART_5
|
||||
/* Set access to UART_5 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapUart5,
|
||||
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
|
||||
false, false);
|
||||
#endif /* CONFIG_UART_IMX_UART_5 */
|
||||
#ifdef CONFIG_UART_IMX_UART_6
|
||||
/* Set access to UART_6 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapUart6,
|
||||
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
|
||||
false, false);
|
||||
#endif /* CONFIG_UART_IMX_UART_6 */
|
||||
#ifdef CONFIG_GPIO_IMX_PORT_1
|
||||
/* Set access to GPIO_1 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio1,
|
||||
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
|
||||
false, false);
|
||||
#endif /* CONFIG_GPIO_IMX_PORT_1 */
|
||||
#ifdef CONFIG_GPIO_IMX_PORT_2
|
||||
/* Set access to GPIO_2 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio2,
|
||||
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
|
||||
false, false);
|
||||
#endif /* CONFIG_GPIO_IMX_PORT_2 */
|
||||
#ifdef CONFIG_GPIO_IMX_PORT_3
|
||||
/* Set access to GPIO_3 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio3,
|
||||
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
|
||||
false, false);
|
||||
#endif /* CONFIG_GPIO_IMX_PORT_3 */
|
||||
#ifdef CONFIG_GPIO_IMX_PORT_4
|
||||
/* Set access to GPIO_4 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio4,
|
||||
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
|
||||
false, false);
|
||||
#endif /* CONFIG_GPIO_IMX_PORT_4 */
|
||||
#ifdef CONFIG_GPIO_IMX_PORT_5
|
||||
/* Set access to GPIO_5 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio5,
|
||||
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
|
||||
false, false);
|
||||
#endif /* CONFIG_GPIO_IMX_PORT_5 */
|
||||
#ifdef CONFIG_GPIO_IMX_PORT_6
|
||||
/* Set access to GPIO_6 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio6,
|
||||
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
|
||||
false, false);
|
||||
#endif /* CONFIG_GPIO_IMX_PORT_6 */
|
||||
#ifdef CONFIG_GPIO_IMX_PORT_7
|
||||
/* Set access to GPIO_7 for M4 core */
|
||||
RDC_SetPdapAccess(RDC, rdcPdapGpio7,
|
||||
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
|
||||
false, false);
|
||||
#endif /* CONFIG_GPIO_IMX_PORT_7 */
|
||||
}
|
||||
|
||||
/* Initialize cache. */
|
||||
static void SOC_CacheInit(void)
|
||||
{
|
||||
/* Enable System Bus Cache */
|
||||
/* set command to invalidate all ways and write GO bit
|
||||
* to initiate command
|
||||
*/
|
||||
LMEM_PSCCR = LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK;
|
||||
LMEM_PSCCR |= LMEM_PSCCR_GO_MASK;
|
||||
/* Wait until the command completes */
|
||||
while (LMEM_PSCCR & LMEM_PSCCR_GO_MASK)
|
||||
;
|
||||
/* Enable system bus cache, enable write buffer */
|
||||
LMEM_PSCCR = (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK);
|
||||
__ISB();
|
||||
|
||||
/* Enable Code Bus Cache */
|
||||
/* set command to invalidate all ways and write GO bit
|
||||
* to initiate command
|
||||
*/
|
||||
LMEM_PCCCR = LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
|
||||
LMEM_PCCCR |= LMEM_PCCCR_GO_MASK;
|
||||
/* Wait until the command completes */
|
||||
while (LMEM_PCCCR & LMEM_PCCCR_GO_MASK)
|
||||
;
|
||||
/* Enable code bus cache, enable write buffer */
|
||||
LMEM_PCCCR = (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
|
||||
__ISB();
|
||||
__DSB();
|
||||
}
|
||||
|
||||
/* Initialize clock. */
|
||||
static void SOC_ClockInit(void)
|
||||
{
|
||||
/* OSC/PLL is already initialized by Cortex-A9 core */
|
||||
|
||||
/* Enable IP bridge and IO mux clock */
|
||||
CCM_ControlGate(CCM, ccmCcgrGateIomuxIptClkIo, ccmClockNeededAll);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateIpmux1Clk, ccmClockNeededAll);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateIpmux2Clk, ccmClockNeededAll);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateIpmux3Clk, ccmClockNeededAll);
|
||||
|
||||
#ifdef CONFIG_UART_IMX
|
||||
/* Set UART clock is derived from OSC clock (24M) */
|
||||
CCM_SetRootMux(CCM, ccmRootUartClkSel, ccmRootmuxUartClkOsc24m);
|
||||
|
||||
/* Configure UART divider */
|
||||
CCM_SetRootDivider(CCM, ccmRootUartClkPodf, 0);
|
||||
|
||||
/* Enable UART clock */
|
||||
CCM_ControlGate(CCM, ccmCcgrGateUartClk, ccmClockNeededAll);
|
||||
CCM_ControlGate(CCM, ccmCcgrGateUartSerialClk, ccmClockNeededAll);
|
||||
#endif /* CONFIG_UART_IMX */
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Perform basic hardware initialization
|
||||
*
|
||||
* Initialize the interrupt controller device drivers.
|
||||
* Also initialize the timer device driver, if required.
|
||||
*
|
||||
* @return 0
|
||||
*/
|
||||
static int mcimx6x_m4_init(struct device *arg)
|
||||
{
|
||||
ARG_UNUSED(arg);
|
||||
|
||||
int oldLevel; /* Old interrupt lock level */
|
||||
|
||||
/* Disable interrupts */
|
||||
oldLevel = irq_lock();
|
||||
|
||||
/* Configure RDC */
|
||||
SOC_RdcInit();
|
||||
|
||||
/* Disable WDOG3 powerdown */
|
||||
WDOG_DisablePowerdown(WDOG3);
|
||||
|
||||
/* Initialize Cache */
|
||||
SOC_CacheInit();
|
||||
|
||||
_ClearFaults();
|
||||
|
||||
/* Initialize clock */
|
||||
SOC_ClockInit();
|
||||
|
||||
/*
|
||||
* Install default handler that simply resets the CPU
|
||||
* if configured in the kernel, NOP otherwise
|
||||
*/
|
||||
NMI_INIT();
|
||||
|
||||
/* Restore interrupt state */
|
||||
irq_unlock(oldLevel);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(mcimx6x_m4_init, PRE_KERNEL_1, 0);
|
||||
34
arch/arm/soc/nxp_imx/mcimx6x_m4/soc.h
Normal file
34
arch/arm/soc/nxp_imx/mcimx6x_m4/soc.h
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright (c) 2018, NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC__H_
|
||||
#define _SOC__H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include "rdc.h"
|
||||
#include "rdc_defs_imx6sx.h"
|
||||
#include "ccm_imx6sx.h"
|
||||
#include "clock_freq.h"
|
||||
|
||||
#define RDC_DOMAIN_PERM_NONE (0x0)
|
||||
#define RDC_DOMAIN_PERM_W (0x1)
|
||||
#define RDC_DOMAIN_PERM_R (0x2)
|
||||
#define RDC_DOMAIN_PERM_RW (RDC_DOMAIN_PERM_W|RDC_DOMAIN_PERM_R)
|
||||
|
||||
#define RDC_DOMAIN_PERM(domain, perm) (perm << (domain * 2))
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC__H_ */
|
||||
195
dts/arm/nxp/nxp_imx6sx_m4.dtsi
Normal file
195
dts/arm/nxp/nxp_imx6sx_m4.dtsi
Normal file
|
|
@ -0,0 +1,195 @@
|
|||
/*
|
||||
* Copyright (c) 2018, NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-m4f";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcml:memory@1FFF8000 {
|
||||
device_type = "memory";
|
||||
compatible = "nxp,imx-code-bus";
|
||||
reg = <0x1FFF8000 0x00008000>;
|
||||
label = "TCML";
|
||||
};
|
||||
|
||||
tcmu:memory@20000000 {
|
||||
device_type = "memory";
|
||||
compatible = "nxp,imx-sys-bus";
|
||||
reg = <0x20000000 0x00008000>;
|
||||
label = "TCMU";
|
||||
};
|
||||
|
||||
ocram_s:memory@208F8000 {
|
||||
device_type = "memory";
|
||||
compatible = "nxp,imx-sys-bus";
|
||||
reg = <0x208F8000 0x00004000>;
|
||||
label = "OCRAM_S";
|
||||
};
|
||||
|
||||
ocram:memory@20900000 {
|
||||
device_type = "memory";
|
||||
compatible = "nxp,imx-sys-bus";
|
||||
reg = <0x20900000 0x00020000>;
|
||||
label = "OCRAM";
|
||||
};
|
||||
|
||||
ddr:memory@80000000 {
|
||||
device_type = "memory";
|
||||
compatible = "nxp,imx-sys-bus";
|
||||
reg = <0x80000000 0x60000000>;
|
||||
label = "DDR";
|
||||
};
|
||||
|
||||
flash:memory@DT_FLASH_ADDR {
|
||||
reg = <DT_FLASH_ADDR DT_FLASH_SIZE>;
|
||||
};
|
||||
|
||||
sram:memory@DT_SRAM_ADDR {
|
||||
reg = <DT_SRAM_ADDR DT_SRAM_SIZE>;
|
||||
};
|
||||
|
||||
soc {
|
||||
uart1:uart@42020000 {
|
||||
compatible = "nxp,imx-uart";
|
||||
reg = <0x42020000 0x00004000>;
|
||||
interrupts = <26 0>;
|
||||
label = "UART_1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2:uart@421E8000 {
|
||||
compatible = "nxp,imx-uart";
|
||||
reg = <0x421E8000 0x00004000>;
|
||||
interrupts = <27 0>;
|
||||
label = "UART_2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3:uart@421EC000 {
|
||||
compatible = "nxp,imx-uart";
|
||||
reg = <0x421EC000 0x00004000>;
|
||||
interrupts = <28 0>;
|
||||
label = "UART_3";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4:uart@421F0000 {
|
||||
compatible = "nxp,imx-uart";
|
||||
reg = <0x421F0000 0x00004000>;
|
||||
interrupts = <29 0>;
|
||||
label = "UART_4";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5:uart@421F4000 {
|
||||
compatible = "nxp,imx-uart";
|
||||
reg = <0x421F4000 0x00004000>;
|
||||
interrupts = <30 0>;
|
||||
label = "UART_5";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6:uart@422A0000 {
|
||||
compatible = "nxp,imx-uart";
|
||||
reg = <0x422A0000 0x00004000>;
|
||||
interrupts = <17 0>;
|
||||
label = "UART_6";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1:gpio@4209C000 {
|
||||
compatible = "nxp,imx-gpio";
|
||||
reg = <0x4209C000 0x4000>;
|
||||
interrupts = <66 0>, <67 0>;
|
||||
label = "GPIO_1";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio2:gpio@420A0000 {
|
||||
compatible = "nxp,imx-gpio";
|
||||
reg = <0x420A0000 0x4000>;
|
||||
interrupts = <68 0>, <69 0>;
|
||||
label = "GPIO_2";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio3:gpio@420A4000 {
|
||||
compatible = "nxp,imx-gpio";
|
||||
reg = <0x420A4000 0x4000>;
|
||||
interrupts = <70 0>, <71 0>;
|
||||
label = "GPIO_3";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio4:gpio@420A8000 {
|
||||
compatible = "nxp,imx-gpio";
|
||||
reg = <0x420A8000 0x4000>;
|
||||
interrupts = <72 0>, <73 0>;
|
||||
label = "GPIO_4";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio5:gpio@420AC000 {
|
||||
compatible = "nxp,imx-gpio";
|
||||
reg = <0x420AC000 0x4000>;
|
||||
interrupts = <74 0>, <74 0>;
|
||||
label = "GPIO_5";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio6:gpio@420B0000 {
|
||||
compatible = "nxp,imx-gpio";
|
||||
reg = <0x420B0000 0x4000>;
|
||||
interrupts = <76 0>, <77 0>;
|
||||
label = "GPIO_6";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio7:gpio@420B4000 {
|
||||
compatible = "nxp,imx-gpio";
|
||||
reg = <0x420B4000 0x4000>;
|
||||
interrupts = <78 0>, <79 0>;
|
||||
label = "GPIO_7";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <4>;
|
||||
};
|
||||
|
|
@ -5,5 +5,10 @@ zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_IMX_CCM ccm_imx7d.c)
|
|||
zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_IMX_CCM ccm_analog_imx7d.c)
|
||||
endif()
|
||||
|
||||
if(CONFIG_SOC_MCIMX6X_M4)
|
||||
zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_IMX_CCM ccm_imx6sx.c)
|
||||
zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_IMX_CCM ccm_analog_imx6sx.c)
|
||||
endif()
|
||||
|
||||
zephyr_sources_ifdef(CONFIG_UART_IMX uart_imx.c)
|
||||
zephyr_sources_ifdef(CONFIG_GPIO_IMX gpio_imx.c)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue