dts: arm: nordic: nRF5340 Application MCU DTS structure
- Adding nRF5340 Application (CPU APP) common (Secure/Non-Secure) peripheral DTS representation. - Adding nrf5340 Application (CPU APP) default (Secure) .dtsi headers - Adding nrf5340 Application (CPU APP) Non-Secure .dtsi headers - Added nRF53 flash controller binding Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit is contained in:
Ioannis Glaropoulos
Carles Cufí
parent
92625d710d
commit
b15ce8800d
6 changed files with 576 additions and 0 deletions
110
dts/arm/nordic/nrf5340_cpuapp.dtsi
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110
dts/arm/nordic/nrf5340_cpuapp.dtsi
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/*
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* Copyright (c) 2019 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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arm,num-mpu-regions = <16>;
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};
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};
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};
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aliases {
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flash-controller = &flash_controller;
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rtc-0 = &rtc0;
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rtc-1 = &rtc1;
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uart-0 = &uart0;
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uart-1 = &uart1;
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adc-0 = &adc;
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egu-0 = &egu0;
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egu-1 = &egu1;
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egu-2 = &egu2;
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egu-3 = &egu3;
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egu-4 = &egu4;
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egu-5 = &egu5;
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gpio-0 = &gpio0;
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gpio-1 = &gpio1;
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gpiote-0 = &gpiote;
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i2c-0 = &i2c0;
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i2c-1 = &i2c1;
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pdm-0 = &pdm0;
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spi-0 = &spi0;
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spi-1 = &spi1;
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spi-2 = &spi2;
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pwm-0 = &pwm0;
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pwm-1 = &pwm1;
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pwm-2 = &pwm2;
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wdt-0 = &wdt;
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timer-0 = &timer0;
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timer-1 = &timer1;
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timer-2 = &timer2;
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};
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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peripheral@50000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x50000000 0x10000000>;
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/* Common nRF5340 Application MCU
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* peripheral description
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*/
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#include "nrf5340_cpuapp_common.dtsi"
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};
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/* Additional Secure peripherals */
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gpiote: gpiote@5000d000 {
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compatible = "nordic,nrf-gpiote";
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reg = <0x5000d000 0x1000>;
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interrupts = <13 5>;
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status = "disabled";
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label = "GPIOTE_0";
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};
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spu: spu@50003000 {
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compatible = "nordic,nrf-spu";
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reg = <0x50003000 0x1000>;
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interrupts = <3 1>;
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status = "okay";
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};
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ficr: ficr@ff0000 {
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compatible = "nordic,nrf-ficr";
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reg = <0xff0000 0x1000>;
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status = "okay";
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};
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uicr: uicr@ff8000 {
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compatible = "nordic,nrf-uicr";
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reg = <0xff8000 0x1000>;
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status = "okay";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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327
dts/arm/nordic/nrf5340_cpuapp_common.dtsi
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327
dts/arm/nordic/nrf5340_cpuapp_common.dtsi
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/*
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* Copyright (c) 2019 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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flash_controller: flash-controller@39000 {
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compatible = "nordic,nrf53-flash-controller";
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reg = <0x39000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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label = "NRF_FLASH_DRV_NAME";
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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label = "NRF_FLASH";
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erase-block-size = <4096>;
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write-block-size = <4>;
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};
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};
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adc: adc@e000 {
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compatible = "nordic,nrf-saadc";
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reg = <0xe000 0x1000>;
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interrupts = <14 1>;
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status = "disabled";
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label = "ADC_0";
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#io-channel-cells = <1>;
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};
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dppic: dppic@17000 {
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compatible = "nordic,nrf-dppic";
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reg = <0x17000 0x1000>;
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status = "okay";
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label = "DPPIC";
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};
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egu0: egu@1b000 {
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compatible = "nordic,nrf-egu";
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reg = <0x1b000 0x1000>;
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interrupts = <27 1>;
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status = "okay";
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};
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egu1: egu@1c000 {
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compatible = "nordic,nrf-egu";
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reg = <0x1c000 0x1000>;
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interrupts = <28 1>;
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status = "okay";
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};
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egu2: egu@1d000 {
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compatible = "nordic,nrf-egu";
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reg = <0x1d000 0x1000>;
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interrupts = <29 1>;
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status = "okay";
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};
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egu3: egu@1e000 {
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compatible = "nordic,nrf-egu";
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reg = <0x1e000 0x1000>;
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interrupts = <30 1>;
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status = "okay";
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};
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egu4: egu@1f000 {
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compatible = "nordic,nrf-egu";
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reg = <0x1f000 0x1000>;
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interrupts = <31 1>;
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status = "okay";
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};
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egu5: egu@20000 {
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compatible = "nordic,nrf-egu";
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reg = <0x20000 0x1000>;
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interrupts = <32 1>;
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status = "okay";
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};
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i2s0: i2s@28000 {
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compatible = "nordic,nrf-i2s";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x28000 0x1000>;
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interrupts = <40 1>;
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status = "disabled";
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label = "I2S_0";
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};
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ipc: ipc@2a000 {
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compatible = "nordic,nrf-ipc";
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reg = <0x2a000 0x1000>;
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interrupts = <42 1>;
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status = "okay";
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label = "IPC";
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};
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kmu: kmu@39000 {
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compatible = "nordic,nrf-kmu";
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reg = <0x39000 0x1000>;
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interrupts = <57 1>;
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status = "okay";
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};
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pdm0: pdm@26000 {
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compatible = "nordic,nrf-pdm";
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reg = <0x26000 0x1000>;
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interrupts = <38 1>;
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status = "disabled";
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label = "PDM_0";
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};
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regulators: regulator@4000 {
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compatible = "nordic,nrf-regulators";
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reg = <0x4000 0x1000>;
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status = "okay";
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};
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vmc: vmc@81000 {
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compatible = "nordic,nrf-vmc";
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reg = <0x81000 0x1000>;
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status = "okay";
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};
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uart0: uart@8000 {
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compatible = "nordic,nrf-uarte";
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reg = <0x8000 0x1000>;
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interrupts = <8 1>;
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status = "disabled";
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label = "UART_0";
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};
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uart1: uart@9000 {
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compatible = "nordic,nrf-uarte";
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reg = <0x9000 0x1000>;
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interrupts = <9 1>;
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status = "disabled";
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label = "UART_1";
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};
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i2c0: i2c@8000 {
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/*
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* This i2c node can be either TWIM or TWIS, for the user to pick:
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* compatible = "nordic,nrf-twim" or
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* "nordic,nrf-twis".
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*/
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x8000 0x1000>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <8 1>;
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status = "disabled";
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label = "I2C_0";
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};
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i2c1: i2c@9000 {
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/*
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* This i2c node can be TWIM or TWIS,
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* for the user to pick:
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* compatible = "nordic,nrf-twim" or
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* "nordic,nrf-twis".
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*/
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x9000 0x1000>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <9 1>;
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status = "disabled";
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label = "I2C_1";
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};
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spi0: spi@8000 {
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/*
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* This spi node can be either SPIM or SPIS,
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* for the user to pick:
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* compatible = "nordic,nrf-spim" or
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* "nordic,nrf-spis".
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*/
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x8000 0x1000>;
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interrupts = <8 1>;
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status = "disabled";
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label = "SPI_0";
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};
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spi1: spi@9000 {
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/*
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* This spi node can be either SPIM or SPIS,
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* for the user to pick:
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* compatible = "nordic,nrf-spim" or
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* "nordic,nrf-spis".
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*/
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x9000 0x1000>;
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interrupts = <9 1>;
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status = "disabled";
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label = "SPI_1";
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};
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spi2: spi@a000 {
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compatible = "nordic,nrf-spim";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xa000 0x1000>;
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interrupts = <10 1>;
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status = "disabled";
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label = "SPI_2";
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};
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pwm0: pwm@21000 {
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compatible = "nordic,nrf-pwm";
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reg = <0x21000 0x1000>;
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interrupts = <33 1>;
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status = "disabled";
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label = "PWM_0";
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#pwm-cells = <1>;
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};
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pwm1: pwm@22000 {
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compatible = "nordic,nrf-pwm";
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reg = <0x22000 0x1000>;
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interrupts = <34 1>;
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status = "disabled";
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label = "PWM_1";
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#pwm-cells = <1>;
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};
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pwm2: pwm@23000 {
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compatible = "nordic,nrf-pwm";
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reg = <0x23000 0x1000>;
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interrupts = <35 1>;
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status = "disabled";
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label = "PWM_2";
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#pwm-cells = <1>;
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};
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gpio0: gpio@842500 {
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compatible = "nordic,nrf-gpio";
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gpio-controller;
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reg = <0x842500 0x300>;
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#gpio-cells = <2>;
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label = "GPIO_0";
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status = "disabled";
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};
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gpio1: gpio@842800 {
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compatible = "nordic,nrf-gpio";
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gpio-controller;
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reg = <0x842800 0x300>;
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#gpio-cells = <2>;
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label = "GPIO_1";
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status = "disabled";
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};
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rtc0: rtc@14000 {
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compatible = "nordic,nrf-rtc";
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reg = <0x14000 0x1000>;
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interrupts = <20 1>;
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status = "okay";
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clock-frequency = <32768>;
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prescaler = <1>;
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label = "RTC_0";
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};
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rtc1: rtc@15000 {
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compatible = "nordic,nrf-rtc";
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reg = <0x15000 0x1000>;
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interrupts = <21 1>;
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status = "okay";
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clock-frequency = <32768>;
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prescaler = <1>;
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label = "RTC_1";
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};
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clock: clock@5000 {
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compatible = "nordic,nrf-clock";
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reg = <0x5000 0x1000>;
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interrupts = <5 1>;
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status = "okay";
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label = "CLOCK";
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};
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power: power@5000 {
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compatible = "nordic,nrf-power";
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reg = <0x5000 0x1000>;
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interrupts = <5 1>;
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status = "okay";
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};
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wdt: watchdog@18000 {
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compatible = "nordic,nrf-watchdog";
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reg = <0x18000 0x1000>;
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interrupts = <24 1>;
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status = "okay";
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label = "WDT";
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};
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timer0: timer@f000 {
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compatible = "nordic,nrf-timer";
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status = "disabled";
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reg = <0xf000 0x1000>;
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interrupts = <15 1>;
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prescaler = <0>;
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label = "TIMER_0";
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};
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timer1: timer@10000 {
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compatible = "nordic,nrf-timer";
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status = "disabled";
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reg = <0x10000 0x1000>;
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interrupts = <16 1>;
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prescaler = <0>;
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label = "TIMER_1";
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};
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timer2: timer@11000 {
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compatible = "nordic,nrf-timer";
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status = "disabled";
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reg = <0x11000 0x1000>;
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interrupts = <17 1>;
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prescaler = <0>;
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label = "TIMER_2";
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};
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22
dts/arm/nordic/nrf5340_cpuapp_qkaa.dtsi
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22
dts/arm/nordic/nrf5340_cpuapp_qkaa.dtsi
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/*
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* Copyright (c) 2019 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <nordic/nrf5340_cpuapp.dtsi>
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&flash0 {
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reg = <0x00000000 DT_SIZE_K(1024)>;
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(512)>;
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};
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/ {
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soc {
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compatible = "nordic,nRF5340-CPU0-QKAA", "nordic,nRF5340-CPU0", "nordic,nRF53", "simple-bus";
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};
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};
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87
dts/arm/nordic/nrf5340_cpuappns.dtsi
Normal file
87
dts/arm/nordic/nrf5340_cpuappns.dtsi
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/*
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* Copyright (c) 2019 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* .dtsi header for nRF5340 CPUAPP (Application MCU), Non-Secure domain */
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#include <arm/armv8-m.dtsi>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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arm,num-mpu-regions = <16>;
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};
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};
|
||||
};
|
||||
|
||||
aliases {
|
||||
flash-controller = &flash_controller;
|
||||
rtc-0 = &rtc0;
|
||||
rtc-1 = &rtc1;
|
||||
uart-0 = &uart0;
|
||||
uart-1 = &uart1;
|
||||
adc-0 = &adc;
|
||||
gpio-0 = &gpio0;
|
||||
gpio-1 = &gpio1;
|
||||
gpiote-0 = &gpiote;
|
||||
i2c-0 = &i2c0;
|
||||
i2c-1 = &i2c1;
|
||||
spi-0 = &spi0;
|
||||
spi-1 = &spi1;
|
||||
spi-2 = &spi2;
|
||||
pwm-0 = &pwm0;
|
||||
pwm-1 = &pwm1;
|
||||
pwm-2 = &pwm2;
|
||||
wdt-0 = &wdt;
|
||||
timer-0 = &timer0;
|
||||
timer-1 = &timer1;
|
||||
timer-2 = &timer2;
|
||||
};
|
||||
|
||||
soc {
|
||||
sram0: memory@20000000 {
|
||||
device_type = "memory";
|
||||
compatible = "mmio-sram";
|
||||
};
|
||||
|
||||
peripheral@40000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x40000000 0x10000000>;
|
||||
|
||||
/* Common nRF5340 Application MCU
|
||||
* peripheral description
|
||||
*/
|
||||
#include "nrf5340_cpuapp_common.dtsi"
|
||||
};
|
||||
|
||||
/* Additional Non-Secure peripherals */
|
||||
gpiote: gpiote@4002f000 {
|
||||
compatible = "nordic,nrf-gpiote";
|
||||
reg = <0x4002f000 0x1000>;
|
||||
interrupts = <47 5>;
|
||||
status = "disabled";
|
||||
label = "GPIOTE_1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
22
dts/arm/nordic/nrf5340_cpuappns_qkaa.dtsi
Normal file
22
dts/arm/nordic/nrf5340_cpuappns_qkaa.dtsi
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <nordic/nrf5340_cpuappns.dtsi>
|
||||
|
||||
&flash0 {
|
||||
reg = <0x00000000 DT_SIZE_K(1024)>;
|
||||
};
|
||||
|
||||
&sram0 {
|
||||
reg = <0x20000000 DT_SIZE_K(512)>;
|
||||
};
|
||||
|
||||
/ {
|
||||
soc {
|
||||
compatible = "nordic,nRF5340-CPU0-QKAA", "nordic,nRF5340-CPU0", "nordic,nRF53", "simple-bus";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
title: Nordic NVMC
|
||||
|
||||
description: |
|
||||
This binding gives a base representation of the Nordic NVMC
|
||||
|
||||
compatible: "nordic,nrf53-flash-controller"
|
||||
|
||||
include: flash-controller.yaml
|
||||
Loading…
Add table
Add a link
Reference in a new issue