boards: arm: Add support for Silabs EFR32 SLWSTK6061A board

The EFR32 Flex Gecko Wireless Starter Kit contains sensors and
peripherals demonstarting the usage of the EFR32FG1P SoC
family. This patch add basic support for this board.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>

boards/arm/efr32_slwstk6061a/CMakeLists.txt

@@ -0,0 +1,5 @@
+if(CONFIG_UART_GECKO)
+  zephyr_library()
+  zephyr_library_sources(board.c)
+  zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)
+endif()

boards/arm/efr32_slwstk6061a/Kconfig

@@ -0,0 +1,19 @@
+# Kconfig - EFR32 SLWSTK6061A board configuration
+#
+# Copyright (c) 2018 Christian Taedcke
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_EFR32_SLWSTK6061A
+
+config BOARD_INIT_PRIORITY
+	int
+
+	# omit prompt to signify a "hidden" option
+	default KERNEL_INIT_PRIORITY_DEFAULT
+	depends on GPIO
+	help
+	  Board initialization priority. This must be bigger than
+	  GPIO_GECKO_COMMON_INIT_PRIORITY.
+
+endif # BOARD_EFR32_SLWSTK6061A

boards/arm/efr32_slwstk6061a/Kconfig.board

@@ -0,0 +1,11 @@
+# Kconfig - EFR32 SLWSTK6061A board
+#
+# Copyright (c) 2018, Christian Taedcke
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_EFR32_SLWSTK6061A
+	bool "SiLabs EFR32-SLWSTK6061A (Flex Gecko)"
+	depends on SOC_SERIES_EFR32FG1P
+	select SOC_PART_NUMBER_EFR32FG1P133F256GM48

boards/arm/efr32_slwstk6061a/Kconfig.defconfig

@@ -0,0 +1,51 @@
+# Kconfig - EFR32 SLWSTK6061A board
+#
+# Copyright (c) 2018, Christian Taedcke
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_EFR32_SLWSTK6061A
+
+config BOARD
+	default "efr32_slwstk6061a"
+
+config CMU_HFXO_FREQ
+	default 38400000
+
+config CMU_LFXO_FREQ
+	default 32768
+
+if GPIO_GECKO
+
+config GPIO_GECKO_PORTA
+	def_bool y
+
+config GPIO_GECKO_PORTB
+	def_bool y
+
+config GPIO_GECKO_PORTC
+	def_bool y
+
+config GPIO_GECKO_PORTD
+	def_bool y
+
+config GPIO_GECKO_PORTE
+	def_bool n
+
+config GPIO_GECKO_PORTF
+	def_bool y
+
+endif # GPIO_GECKO
+
+if UART_GECKO
+
+config USART_GECKO_0
+	def_bool y
+
+config USART_GECKO_0_GPIO_LOC
+	default 0
+
+endif # UART_GECKO
+
+endif # BOARD_EFR32_SLWSTK6061A

boards/arm/efr32_slwstk6061a/board.c

@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018 Christian Taedcke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <init.h>
+#include <board.h>
+#include <gpio.h>
+#include <misc/printk.h>
+
+static int efr32_slwstk6061a_init(struct device *dev)
+{
+	struct device *bce_dev; /* Board Controller Enable Gpio Device */
+
+	ARG_UNUSED(dev);
+
+	/* Enable the board controller to be able to use the serial port */
+	bce_dev = device_get_binding(BC_ENABLE_GPIO_NAME);
+
+	if (!bce_dev) {
+		printk("Board controller gpio port was not found!\n");
+		return -ENODEV;
+	}
+
+	gpio_pin_configure(bce_dev, BC_ENABLE_GPIO_PIN, GPIO_DIR_OUT);
+	gpio_pin_write(bce_dev, BC_ENABLE_GPIO_PIN, 1);
+
+	return 0;
+}
+
+/* needs to be done after GPIO driver init */
+SYS_INIT(efr32_slwstk6061a_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);

boards/arm/efr32_slwstk6061a/board.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2018 Christian Taedcke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_BOARD_H
+#define __INC_BOARD_H
+
+#include <soc.h>
+
+/* Push button PB0 */
+#define PB0_GPIO_NAME	CONFIG_GPIO_GECKO_PORTF_NAME
+#define PB0_GPIO_PIN	6
+
+/* Push button PB1 */
+#define PB1_GPIO_NAME	CONFIG_GPIO_GECKO_PORTF_NAME
+#define PB1_GPIO_PIN	7
+
+/* LED 0 */
+#define LED0_GPIO_NAME	CONFIG_GPIO_GECKO_PORTF_NAME
+#define LED0_GPIO_PORT  LED0_GPIO_NAME
+#define LED0_GPIO_PIN	4
+
+/* LED 1 */
+#define LED1_GPIO_NAME	CONFIG_GPIO_GECKO_PORTF_NAME
+#define LED1_GPIO_PIN	5
+
+/* Push button switch 0. There is no physical switch on the board with this
+ * name, so create an alias to SW3 to make the basic button sample work.
+ */
+#define SW0_GPIO_NAME	PB0_GPIO_NAME
+#define SW0_GPIO_PIN	PB0_GPIO_PIN
+
+/* This pin is used to enable the serial port using the board controller */
+#define BC_ENABLE_GPIO_NAME  CONFIG_GPIO_GECKO_PORTA_NAME
+#define BC_ENABLE_GPIO_PIN   5
+
+#endif /* __INC_BOARD_H */

boards/arm/efr32_slwstk6061a/doc/efr32_slwstk6061a.rst

@@ -0,0 +1,188 @@
+.. _efr32_slwstk6061a:
+
+EFR32-SLWSTK6061A
+#################
+
+Overview
+********
+
+The EFR32 Flex Gecko Wireless Starter Kit SLWSTK6061A contains a Wireless
+System-On-Chip from the EFR32FG family built on an ARM® Cortex®-M4F processor
+with excellent low power capabilities.
+
+.. figure:: efr32-flex-gecko-starter-kit.png
+   :width: 375px
+   :align: center
+   :alt: EFR32-SLWSTK6061A
+
+   EFR32-SLWSTK6061A (image courtesy of Silicon Labs)
+
+Hardware
+********
+
+The SLWRB4250B radio board plugs into the Wireless Starter Kit Mainboard BRD4001A.
+
+Wireless Starter Kit Mainboard:
+
+- Advanced Energy Monitoring provides real-time information about the energy
+  consumption of an application or prototype design.
+- Ultra-low power 128x128 pixel memory LCD
+- 2 user buttons and 2 LEDs
+- Si7021 Humidity and Temperature Sensor
+- On-board Segger J-Link USB and Ethernet debugger
+
+Radio Board:
+
+- EFR32FG1P133F256GM48 Flex Gecko SoC
+- 8Mbit SPI NOR Flash
+
+For more information about the EFR32FG1 SoC and EFR32-SLWSTK6061A board, refer
+to these documents:
+
+- `EFR32FG Website`_
+- `EFR32FG1 Datasheet`_
+- `EFR32xG1 Reference Manual`_
+- `EFR32-SLWSTK6061A Website`_
+- `EFR32-SLWSTK6061A User Guide`_
+- `WSTK Main Board BRD4001A Schematics`_
+- `EFR32FG1-BRD4250B Schematics`_
+
+
+Supported Features
+==================
+
+The efr32_slwstk6061a board configuration supports the following hardware features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| SYSTICK   | on-chip    | systick                             |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling;                |
+|           |            | serial port-interrupt               |
++-----------+------------+-------------------------------------+
+
+The default configuration can be found in the defconfig file:
+
+	``boards/arm/efr32_slwstk6061a/efr32_slwstk6061a_defconfig``
+
+Other hardware features are currently not supported by the port.
+
+Connections and IOs
+===================
+
+The EFR32FG1P SoC has five GPIO controllers (PORTA to PORTD and PORTF). All of
+them are enabled for the EFR32-SLWSTK6061A board.
+
+In the following table, the column **Name** contains Pin names. For example, PA2
+means Pin number 2 on PORTA, as used in the board's datasheets and manuals.
+
++-------+-------------+-------------------------------------+
+| Name  | Function    | Usage                               |
++=======+=============+=====================================+
+| PF4   | GPIO        | LED0                                |
++-------+-------------+-------------------------------------+
+| PF5   | GPIO        | LED1                                |
++-------+-------------+-------------------------------------+
+| PF6   | GPIO        | Push Button PB0                     |
++-------+-------------+-------------------------------------+
+| PF7   | GPIO        | Push Button PB1                     |
++-------+-------------+-------------------------------------+
+| PA5   | GPIO        | Board Controller Enable             |
+|       |             | EFM_BC_EN                           |
++-------+-------------+-------------------------------------+
+| PA0   | USART0_TX   | UART Console EFM_BC_TX US0_TX #0    |
++-------+-------------+-------------------------------------+
+| PA1   | USART0_RX   | UART Console EFM_BC_RX US0_RX #0    |
++-------+-------------+-------------------------------------+
+
+System Clock
+============
+
+The EFR32FG1P SoC is configured to use the 38.4 MHz external oscillator on the
+board.
+
+Serial Port
+===========
+
+The EFR32FG1P SoC has two USARTs and one Low Energy UARTs (LEUART).
+USART0 is connected to the board controller and is used for the console.
+
+Programming and Debugging
+*************************
+
+.. note::
+   Before using the kit the first time, you should update the J-Link firmware
+   from `J-Link-Downloads`_
+
+Flashing
+========
+
+The EFR32-SLWSTK6061A includes an `J-Link`_ serial and debug adaptor built into the
+board. The adaptor provides:
+
+- A USB connection to the host computer, which exposes a debug interface and a
+  USB Serial Port.
+- A physical UART connection which is relayed over interface USB Serial port.
+- An Ethernet connection to support remote debugging.
+
+Flashing an application to EFR32-SLWstk6061A
+--------------------------------------------
+
+The sample application :ref:`hello_world` is used for this example.
+Build the Zephyr kernel and application:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: efr32_slwstk6061a
+   :goals: build
+
+Connect the EFR32-SLWSTK6061A to your host computer using the USB port and you
+should see a USB Serial Port. Use `J-Link`_ or Silicon Labs Simplicity Studio
+to flash the generated zephyr.bin.
+
+Open a serial terminal (minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Reset the board and you should be able to see on the corresponding Serial Port
+the following message:
+
+.. code-block:: console
+
+   Hello World! arm
+
+
+.. _EFR32-SLWSTK6061A Website:
+   https://www.silabs.com/products/development-tools/wireless/proprietary/slwstk6061a-efr32-flex-gecko-868-mhz-2-4-ghz-and-sub-ghz-starter-kit
+
+.. _EFR32-SLWSTK6061A User Guide:
+   https://www.silabs.com/documents/public/user-guides/UG182-WSTK6061-User-Guide.pdf
+
+.. _WSTK Main Board BRD4001A Schematics:
+   https://www.silabs.com/documents/public/schematic-files/WSTK-Main-BRD4001A-A01-schematic.pdf
+
+.. _EFR32FG1-BRD4250B Schematics:
+   https://www.silabs.com/documents/public/schematic-files/EFR32FG1-BRD4250B-B02-schematic.pdf
+
+.. _EFR32FG Website:
+   https://www.silabs.com/products/wireless/proprietary/efr32-flex-gecko-2-4-ghz-sub-ghz
+
+.. _EFR32FG1 Datasheet:
+   https://www.silabs.com/documents/public/data-sheets/efr32fg1-datasheet.pdf
+
+.. _EFR32xG1 Reference Manual:
+   https://www.silabs.com/documents/public/reference-manuals/efr32xg1-rm.pdf
+
+.. _J-Link:
+   https://www.segger.com/jlink-debug-probes.html
+
+.. _J-Link-Downloads:
+   https://www.segger.com/downloads/jlink

boards/arm/efr32_slwstk6061a/efr32_slwstk6061a.dts

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018 Christian Taedcke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <silabs/efr32fg1p.dtsi>
+
+/ {
+	model = "Silicon Labs EFR32 SLWSTK6061A board";
+	compatible = "silabs,efr32_slwstk6061a", "silabs,efr32fg1p";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+};
+
+&uart0 {
+	current-speed = <115200>;
+	status = "ok";
+};

boards/arm/efr32_slwstk6061a/efr32_slwstk6061a.yaml

@@ -0,0 +1,13 @@
+identifier: efr32_slwstk6061a
+name: EFR32-SLWSTK6061A
+type: mcu
+arch: arm
+ram: 32
+flash: 256
+toolchain:
+  - zephyr
+  - gccarmemb
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/arm/efr32_slwstk6061a/efr32_slwstk6061a_defconfig

@@ -0,0 +1,11 @@
+CONFIG_ARM=y
+CONFIG_SOC_FAMILY_EXX32=y
+CONFIG_SOC_SERIES_EFR32FG1P=y
+CONFIG_BOARD_EFR32_SLWSTK6061A=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_CORTEX_M_SYSTICK=y
+CONFIG_GPIO=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000
+CONFIG_CMU_HFCLK_HFXO=y

dts/arm/silabs/efr32fg1p.dtsi

@@ -0,0 +1,42 @@
+#include <arm/armv7-m.dtsi>
+#include <silabs/mem.h>
+
+/ {
+	cpus {
+		cpu@0 {
+			compatible = "arm,cortex-m4f";
+		};
+	};
+
+	flash0: flash {
+		compatible = "soc-nv-flash";
+		label = "FLASH_0";
+		reg = <0 DT_FLASH_SIZE>;
+	};
+
+	sram0: memory {
+		reg = <0x20000000 DT_SRAM_SIZE>;
+	};
+
+	soc {
+		uart0: uart@40010000 { /* USART0 */
+			compatible = "silabs,efm32-usart";
+			reg = <0x40010000 0x400>;
+			interrupts = <11 0 12 0>;
+			status = "disabled";
+			label = "UART_0";
+		};
+
+		uart1: uart@40010400 { /* USART1 */
+			compatible = "silabs,efm32-usart";
+			reg = <0x40010400 0x400>;
+			interrupts = <19 0 20 0>;
+			status = "disabled";
+			label = "UART_1";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};

dts/arm/silabs/mem.h

@@ -6,6 +6,9 @@
 #if defined(CONFIG_SOC_PART_NUMBER_EFM32WG990F256)
 #define DT_FLASH_SIZE		__SIZE_K(256)
 #define DT_SRAM_SIZE		__SIZE_K(32)
+#elif defined(CONFIG_SOC_PART_NUMBER_EFR32FG1P133F256GM48)
+#define DT_FLASH_SIZE		__SIZE_K(256)
+#define DT_SRAM_SIZE		__SIZE_K(32)
 #else
 #error "Flash and RAM sizes not defined for this chip"
 #endif