drivers: can: Prepare STM32 driver for other series than STM32F0
This commit splits the common interrupt into rx and tx parts because only STM32F0 series has a common interrupt. Moved clock source definition to device-tree. Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
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13a96574cd
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ebc31f6235
3 changed files with 115 additions and 45 deletions
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@ -43,18 +43,47 @@ static inline void can_stm32_get_msg_fifo(CAN_FIFOMailBox_TypeDef *mbox,
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msg->data_32[1] = mbox->RDHR;
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}
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static void can_stm32_isr(void *arg)
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static inline
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void can_stm32_rx_isr_handler(CAN_TypeDef *can, struct can_stm32_data *data)
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{
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struct device *dev;
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struct can_stm32_data *data;
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const struct can_stm32_config *cfg;
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CAN_TypeDef *can;
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u32_t bus_off;
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CAN_FIFOMailBox_TypeDef *mbox;
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int filter_match_index;
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struct can_msg msg;
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dev = (struct device *)arg;
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data = DEV_DATA(dev);
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cfg = DEV_CFG(dev);
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can = cfg->can;
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while (can->RF0R & CAN_RF0R_FMP0) {
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mbox = &can->sFIFOMailBox[0];
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filter_match_index = ((mbox->RDTR & CAN_RDT0R_FMI)
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>> CAN_RDT0R_FMI_Pos);
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if (filter_match_index >= CONFIG_CAN_MAX_FILTER) {
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break;
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}
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SYS_LOG_DBG("Message on filter index %d", filter_match_index);
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can_stm32_get_msg_fifo(mbox, &msg);
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if (data->rx_response[filter_match_index]) {
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if (data->response_type & (1ULL << filter_match_index)) {
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struct k_msgq *msg_q =
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data->rx_response[filter_match_index];
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k_msgq_put(msg_q, &msg, K_NO_WAIT);
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} else {
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can_rx_callback_t callback =
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data->rx_response[filter_match_index];
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callback(&msg);
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}
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}
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/* Release message */
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can->RF0R |= CAN_RF0R_RFOM0;
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}
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}
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static inline
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void can_stm32_tx_isr_handler(CAN_TypeDef *can, struct can_stm32_data *data)
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{
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u32_t bus_off;
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bus_off = can->ESR & CAN_ESR_BOFF;
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@ -97,41 +126,61 @@ static void can_stm32_isr(void *arg)
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if (can->TSR & CAN_TSR_TME) {
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k_sem_give(&data->tx_int_sem);
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}
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while (can->RF0R & CAN_RF0R_FMP0) {
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CAN_FIFOMailBox_TypeDef *mbox;
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int filter_match_index;
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struct can_msg msg;
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mbox = &can->sFIFOMailBox[0];
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filter_match_index = ((mbox->RDTR & CAN_RDT0R_FMI)
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>> CAN_RDT0R_FMI_Pos);
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if (filter_match_index >= CONFIG_CAN_MAX_FILTER) {
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break;
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}
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SYS_LOG_DBG("Message on filter index %d", filter_match_index);
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can_stm32_get_msg_fifo(mbox, &msg);
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if (data->rx_response[filter_match_index]) {
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if (data->response_type & (1ULL << filter_match_index)) {
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struct k_msgq *msg_q =
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data->rx_response[filter_match_index];
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k_msgq_put(msg_q, &msg, K_NO_WAIT);
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} else {
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can_rx_callback_t callback =
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data->rx_response[filter_match_index];
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callback(&msg);
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}
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}
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/* Release message */
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can->RF0R |= CAN_RF0R_RFOM0;
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}
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}
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#ifdef CONFIG_SOC_SERIES_STM32F0X
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static void can_stm32_isr(void *arg)
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{
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struct device *dev;
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struct can_stm32_data *data;
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const struct can_stm32_config *cfg;
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CAN_TypeDef *can;
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dev = (struct device *)arg;
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data = DEV_DATA(dev);
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cfg = DEV_CFG(dev);
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can = cfg->can;
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can_stm32_tx_isr_handler(can, data);
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can_stm32_rx_isr_handler(can, data);
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}
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#else
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static void can_stm32_rx_isr(void *arg)
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{
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struct device *dev;
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struct can_stm32_data *data;
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const struct can_stm32_config *cfg;
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CAN_TypeDef *can;
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dev = (struct device *)arg;
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data = DEV_DATA(dev);
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cfg = DEV_CFG(dev);
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can = cfg->can;
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can_stm32_rx_isr_handler(can, data);
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}
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static void can_stm32_tx_isr(void *arg)
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{
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struct device *dev;
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struct can_stm32_data *data;
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const struct can_stm32_config *cfg;
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CAN_TypeDef *can;
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dev = (struct device *)arg;
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data = DEV_DATA(dev);
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cfg = DEV_CFG(dev);
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can = cfg->can;
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can_stm32_tx_isr_handler(can, data);
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}
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#endif
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void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan)
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{
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ARG_UNUSED(hcan);
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@ -798,8 +847,8 @@ static const struct can_stm32_config can_stm32_cfg_1 = {
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.prop_bs1 = CONFIG_CAN_1_PROP_SEG_PHASE_SEG1,
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.bs2 = CONFIG_CAN_1_PHASE_SEG2,
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.pclken = {
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.enr = RCC_APB1ENR_CANEN,
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.bus = STM32_CLOCK_BUS_APB1,
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.enr = CONFIG_CAN_1_CLOCK_BITS,
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.bus = CONFIG_CAN_1_CLOCK_BUS,
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},
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.config_irq = config_can_1_irq
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};
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@ -814,9 +863,23 @@ DEVICE_AND_API_INIT(can_stm32_1, CONFIG_CAN_1_NAME, &can_stm32_init,
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static void config_can_1_irq(CAN_TypeDef *can)
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{
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SYS_LOG_DBG("Enable CAN1 IRQ");
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#ifdef CONFIG_SOC_SERIES_STM32F0X
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IRQ_CONNECT(CONFIG_CAN_1_IRQ, CONFIG_CAN_1_IRQ_PRIORITY, can_stm32_isr,
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DEVICE_GET(can_stm32_1), 0);
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irq_enable(CONFIG_CAN_1_IRQ);
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#else
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IRQ_CONNECT(CONFIG_CAN_1_IRQ_RX0, CONFIG_CAN_1_IRQ_PRIORITY,
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can_stm32_rx_isr, DEVICE_GET(can_stm32_1), 0);
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irq_enable(CONFIG_CAN_1_IRQ_RX0);
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IRQ_CONNECT(CONFIG_CAN_1_IRQ_TX, CONFIG_CAN_1_IRQ_PRIORITY,
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can_stm32_tx_isr, DEVICE_GET(can_stm32_1), 0);
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irq_enable(CONFIG_CAN_1_IRQ_TX);
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IRQ_CONNECT(CONFIG_CAN_1_IRQ_SCE, CONFIG_CAN_1_IRQ_PRIORITY,
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can_stm32_tx_isr, DEVICE_GET(can_stm32_1), 0);
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irq_enable(CONFIG_CAN_1_IRQ_SCE);
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#endif
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can->IER |= CAN_IT_TME | CAN_IT_ERR | CAN_IT_FMP0 | CAN_IT_FMP1;
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}
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@ -64,6 +64,7 @@
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#size-cells = <0>;
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reg = <0x40006400 0x400>;
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interrupts = <30 0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
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status = "disabled";
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label = "CAN_1";
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bus-speed = <250000>;
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@ -45,4 +45,10 @@ properties:
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category: required
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description: tx pin name
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generation: define
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clocks:
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type: array
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category: required
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description: Clock gate control information
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generation: define
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...
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