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arm: st: add stm32l4r5xx support

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New parts from ST. See http://www.st.com/en/microcontrollers/stm32l4r5-s5.html
for more details.

Signed-off-by: Pushpal Sidhu <psidhu.devel@gmail.com>
This commit is contained in:
Pushpal Sidhu 2017-12-04 09:59:16 -08:00 • committed by Anas Nashif
commit f1d78d8f38
4 changed files with 181 additions and 0 deletions
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123
dts/arm/st/l4/stm32l4r5.dtsi Normal file
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@ -0,0 +1,123 @@
/*
* Copyright (c) 2018 Pushpal Sidhu
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/l4/stm32l4.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(640)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
erase-block-size = <4096>;
};
};
pinctrl: pin-controller@48000000 {
gpiod: gpio@48000c00 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
label = "GPIOD";
};
gpioe: gpio@48001000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
label = "GPIOE";
};
gpiof: gpio@48001400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48001400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
label = "GPIOF";
};
gpiog: gpio@48001800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48001800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
label = "GPIOG";
};
};
uart4: serial@40004c00 {
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
interrupts = <52 0>;
status = "disabled";
label = "UART_4";
};
uart5: serial@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
interrupts = <53 0>;
status = "disabled";
label = "UART_5";
};
i2c3: i2c@40005C00 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005C00 0x400>;
interrupts = <72 0>, <73 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_3";
};
i2c4: i2c@40008400 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40008400 0x400>;
interrupts = <83 0>, <84 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_4";
};
spi3: spi@40003C00 {
compatible = "st,stm32-spi-fifo";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003C00 0x400>;
interrupts = <51 5>;
status = "disabled";
label = "SPI_3";
};
usbotg_fs: otgfs@50000000 {
compatible = "st,stm32-otgfs";
reg = <0x50000000 0x40000>;
interrupts = <67 0>;
interrupt-names = "otgfs";
num-bidir-endpoints = <6>;
ram-size = <1280>;
status = "disabled";
label= "OTGFS";
};
};
};

18
dts/arm/st/l4/stm32l4r5Xi.dtsi Normal file
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@ -0,0 +1,18 @@
/*
* Copyright (c) 2018 Pushpal Sidhu
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/l4/stm32l4r5.dtsi>
/ {
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(2048)>;
};
};
};
};

37
soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4r5xx Normal file
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@ -0,0 +1,37 @@
# Kconfig - ST Microelectronics STM32L4R5xx MCU
#
# Copyright (c) 2018 Pushpal Sidhu
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_STM32L4R5XI
config SOC
string
default "stm32l4r5xx"
config NUM_IRQS
int
default 95
if GPIO_STM32
config GPIO_STM32_PORTD
def_bool y
config GPIO_STM32_PORTE
default y
config GPIO_STM32_PORTF
default y
config GPIO_STM32_PORTG
default y
config GPIO_STM32_PORTH
default y
endif # GPIO_STM32
endif # SOC_STM32L4R5XI

3
soc/arm/st_stm32/stm32l4/Kconfig.soc
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@ -25,4 +25,7 @@ config SOC_STM32L433XC
config SOC_STM32L475XG
bool "STM32L475XG"
config SOC_STM32L4R5XI
bool "STM32L4R5XI"
endchoice