drivers: timer: Add RTC-based system timer for Atmel SAM0 series MCU
Add sam0_rtc_driver that implements system timer API on top of the RTC and can be used as a replacement for the default systick timer. Signed-off-by: Martin Benda <martin.benda@omsquare.com>
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@ -79,3 +79,7 @@
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};
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};
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};
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&rtc {
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status = "ok";
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};
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@ -10,3 +10,4 @@ zephyr_sources_if_kconfig( rv32m1_lptmr_timer.c)
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zephyr_sources_if_kconfig( cortex_m_systick.c)
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zephyr_sources_ifdef(CONFIG_XTENSA_TIMER xtensa_sys_timer.c)
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zephyr_sources_if_kconfig( native_posix_timer.c)
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zephyr_sources_if_kconfig( sam0_rtc_timer.c)
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@ -175,6 +175,15 @@ config XTENSA_TIMER_ID
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carefully. Generally you want the timer with the highest
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priority maskable interrupt.
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config SAM0_RTC_TIMER
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bool "Atmel SAM0 series RTC timer"
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depends on SOC_FAMILY_SAM0
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select TICKLESS_CAPABLE
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help
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This module implements a kernel device driver for the Atmel SAM0
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series Real Time Counter and provides the standard "system clock
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driver" interfaces.
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config SYSTEM_CLOCK_DISABLE
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bool "API to disable system clock"
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help
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263
drivers/timer/sam0_rtc_timer.c
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263
drivers/timer/sam0_rtc_timer.c
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@ -0,0 +1,263 @@
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/*
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* Copyright (c) 2018 omSquare s.r.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Atmel SAM0 series RTC-based system timer
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*
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* This system timer implementation supports both tickless and ticking modes.
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* In tickless mode, RTC counts continually in 32-bit mode and timeouts are
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* scheduled using the RTC comparator. In ticking mode, RTC is configured to
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* generate an interrupt every tick.
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*/
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#include <soc.h>
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#include <clock_control.h>
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#include <system_timer.h>
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#include <sys_clock.h>
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/* RTC registers. */
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#define RTC0 ((RtcMode0 *) DT_RTC_SAM0_BASE_ADDRESS)
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/* Number of sys timer cycles per on tick. */
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#define CYCLES_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \
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/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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/* Maximum number of ticks. */
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#define MAX_TICKS (UINT32_MAX / CYCLES_PER_TICK - 2)
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#ifdef CONFIG_TICKLESS_KERNEL
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/*
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* Due to the nature of clock synchronization, reading from or writing to some
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* RTC registers takes approximately six RTC_GCLK cycles. This constant defines
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* a safe threshold for the comparator.
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*/
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#define TICK_THRESHOLD 7
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BUILD_ASSERT_MSG(CYCLES_PER_TICK > TICK_THRESHOLD,
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"CYCLES_PER_TICK must be greater than TICK_THRESHOLD for "
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"tickless mode");
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#else /* !CONFIG_TICKLESS_KERNEL */
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/*
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* For some reason, RTC does not generate interrupts when COMP == 0,
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* MATCHCLR == 1 and PRESCALER == 0. So we need to check that CYCLES_PER_TICK
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* is more than one.
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*/
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BUILD_ASSERT_MSG(CYCLES_PER_TICK > 1,
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"CYCLES_PER_TICK must be greater than 1 for ticking mode");
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#endif /* CONFIG_TICKLESS_KERNEL */
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/* Helper macro to get the correct GCLK GEN based on configuration. */
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#define GCLK_GEN(n) GCLK_EVAL(n)
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#define GCLK_EVAL(n) GCLK_CLKCTRL_GEN_GCLK##n
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/* Tick/cycle count of the last announce call. */
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static volatile u32_t rtc_last;
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#ifndef CONFIG_TICKLESS_KERNEL
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/* Current tick count. */
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static volatile u32_t rtc_counter;
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/* Tick value of the next timeout. */
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static volatile u32_t rtc_timeout;
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#endif /* CONFIG_TICKLESS_KERNEL */
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/*
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* Waits for RTC bus synchronization.
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*/
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static inline void rtc_sync(void)
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{
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while (RTC0->STATUS.reg & RTC_STATUS_SYNCBUSY) {
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/* Wait for bus synchronization... */
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}
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}
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/*
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* Reads RTC COUNT register. First a read request must be written to READREQ,
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* then - when bus synchronization completes - the COUNT register is read and
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* returned.
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*/
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static u32_t rtc_count(void)
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{
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RTC0->READREQ.reg = RTC_READREQ_RREQ;
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rtc_sync();
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return RTC0->COUNT.reg;
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}
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static void rtc_reset(void)
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{
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rtc_sync();
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/* Disable interrupt. */
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RTC0->INTENCLR.reg = RTC_MODE0_INTENCLR_MASK;
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/* Clear interrupt flag. */
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RTC0->INTFLAG.reg = RTC_MODE0_INTFLAG_MASK;
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/* Disable RTC module. */
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RTC0->CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE;
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rtc_sync();
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/* Initiate software reset. */
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RTC0->CTRL.reg |= RTC_MODE0_CTRL_SWRST;
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}
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static void rtc_isr(void *arg)
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{
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ARG_UNUSED(arg);
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/* Read and clear the interrupt flag register. */
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u16_t status = RTC0->INTFLAG.reg;
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RTC0->INTFLAG.reg = status;
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#ifdef CONFIG_TICKLESS_KERNEL
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/* Read the current counter and announce the elapsed time in ticks. */
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u32_t count = rtc_count();
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if (count != rtc_last) {
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u32_t ticks = (count - rtc_last) / CYCLES_PER_TICK;
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z_clock_announce(ticks);
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rtc_last += ticks * CYCLES_PER_TICK;
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}
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#else /* !CONFIG_TICKLESS_KERNEL */
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if (status) {
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/* RTC just ticked one more tick... */
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if (++rtc_counter == rtc_timeout) {
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z_clock_announce(rtc_counter - rtc_last);
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rtc_last = rtc_counter;
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}
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} else {
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/* ISR was invoked directly from z_clock_set_timeout. */
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z_clock_announce(0);
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}
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#endif /* CONFIG_TICKLESS_KERNEL */
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}
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int z_clock_driver_init(struct device *device)
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{
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ARG_UNUSED(device);
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/* Set up bus clock and GCLK generator. */
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PM->APBAMASK.reg |= PM_APBAMASK_RTC;
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(RTC_GCLK_ID) | GCLK_CLKCTRL_CLKEN
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| GCLK_GEN(DT_RTC_SAM0_CLOCK_GENERATOR);
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while (GCLK->STATUS.bit.SYNCBUSY) {
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/* Synchronize GCLK. */
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}
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/* Reset module to hardware defaults. */
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rtc_reset();
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rtc_last = 0;
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/* Configure RTC with 32-bit mode, configured prescaler and MATCHCLR. */
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u16_t ctrl = RTC_MODE0_CTRL_MODE(0) | RTC_MODE0_CTRL_PRESCALER(0);
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#ifndef CONFIG_TICKLESS_KERNEL
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ctrl |= RTC_MODE0_CTRL_MATCHCLR;
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#endif
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rtc_sync();
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RTC0->CTRL.reg = ctrl;
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#ifdef CONFIG_TICKLESS_KERNEL
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/* Tickless kernel lets RTC count continually and ignores overflows. */
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RTC0->INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
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#else
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/* Non-tickless mode uses comparator together with MATCHCLR. */
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rtc_sync();
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RTC0->COMP[0].reg = CYCLES_PER_TICK;
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RTC0->INTENSET.reg = RTC_MODE0_INTENSET_OVF;
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rtc_counter = 0;
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rtc_timeout = 0;
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#endif
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/* Enable RTC module. */
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rtc_sync();
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RTC0->CTRL.reg |= RTC_MODE0_CTRL_ENABLE;
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/* Enable RTC interrupt. */
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NVIC_ClearPendingIRQ(DT_RTC_SAM0_IRQ);
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IRQ_CONNECT(DT_RTC_SAM0_IRQ, DT_RTC_SAM0_IRQ_PRIORITY, rtc_isr, 0, 0);
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irq_enable(DT_RTC_SAM0_IRQ);
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return 0;
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}
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void z_clock_set_timeout(s32_t ticks, bool idle)
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{
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ARG_UNUSED(idle);
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#ifdef CONFIG_TICKLESS_KERNEL
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ticks = (ticks == K_FOREVER) ? MAX_TICKS : ticks;
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ticks = max(min(ticks - 1, (s32_t) MAX_TICKS), 0);
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/* Compute number of RTC cycles until the next timeout. */
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u32_t count = rtc_count();
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u32_t timeout = ticks * CYCLES_PER_TICK + count % CYCLES_PER_TICK;
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/* Round to the nearest tick boundary. */
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timeout = (timeout + CYCLES_PER_TICK - 1) / CYCLES_PER_TICK
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* CYCLES_PER_TICK;
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if (timeout < TICK_THRESHOLD) {
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timeout += CYCLES_PER_TICK;
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}
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rtc_sync();
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RTC0->COMP[0].reg = count + timeout;
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#else /* !CONFIG_TICKLESS_KERNEL */
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if (ticks == K_FOREVER) {
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/* Disable comparator for K_FOREVER and other negative
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* values.
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*/
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rtc_timeout = rtc_counter;
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return;
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}
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if (ticks < 1) {
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ticks = 1;
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}
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/* Avoid race condition between reading counter and ISR incrementing
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* it.
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*/
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int key = irq_lock();
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rtc_timeout = rtc_counter + ticks;
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irq_unlock(key);
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#endif /* CONFIG_TICKLESS_KERNEL */
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}
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u32_t z_clock_elapsed(void)
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{
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#ifdef CONFIG_TICKLESS_KERNEL
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return (rtc_count() - rtc_last) / CYCLES_PER_TICK;
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#else
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return rtc_counter - rtc_last;
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#endif
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}
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u32_t _timer_cycle_get_32(void)
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{
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/* Just return the absolute value of RTC cycle counter. */
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return rtc_count();
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}
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@ -134,6 +134,15 @@
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num-bidir-endpoints = <8>;
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label = "USB0";
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};
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rtc: rtc@40001400 {
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compatible = "atmel,sam0-rtc";
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reg = <0x40001400 0x1C>;
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interrupts = <3 0>;
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clock-generator = <0>;
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status = "disabled";
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label = "RTC";
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};
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};
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};
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31
dts/bindings/rtc/atmel,sam0-rtc.yaml
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31
dts/bindings/rtc/atmel,sam0-rtc.yaml
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#
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# Copyright (c) 2018 omSquare s.r.o.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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---
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title: Atmel SAM0 RTC
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version: 0.1
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description: >
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This binding gives a base representation of the Atmel SAM0 RTC
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inherits:
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!include rtc.yaml
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properties:
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compatible:
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constraint: "atmel,sam0-rtc"
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reg:
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type: array
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description: mmio register space
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generation: define
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category: required
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clock-generator:
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type: int
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description: clock generator index
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generation: define
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category: required
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...
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@ -99,6 +99,11 @@
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#define DT_PINMUX_SAM0_B_BASE_ADDRESS DT_ATMEL_SAM0_PINMUX_41004480_BASE_ADDRESS
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#define DT_PINMUX_SAM0_B_LABEL DT_ATMEL_SAM0_PINMUX_41004480_LABEL
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#define DT_RTC_SAM0_BASE_ADDRESS DT_ATMEL_SAM0_RTC_40001400_BASE_ADDRESS
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#define DT_RTC_SAM0_IRQ DT_ATMEL_SAM0_RTC_40001400_IRQ_0
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#define DT_RTC_SAM0_IRQ_PRIORITY DT_ATMEL_SAM0_RTC_40001400_IRQ_0_PRIORITY
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#define DT_RTC_SAM0_CLOCK_GENERATOR DT_ATMEL_SAM0_RTC_40001400_CLOCK_GENERATOR
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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/* End of SoC Level DTS fixup file */
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