boards: arm: stm32f3_disco: Enable SPI_1, SPI_2 ports
Enable SPI1 and SPI2 ports on stm32f3_disco. Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
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b2ce9df077
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8 changed files with 71 additions and 0 deletions
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@ -30,6 +30,15 @@
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#define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V2_40005800_IRQ_ERROR
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#define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
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#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
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#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
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#define CONFIG_SPI_1_NAME ST_STM32_SPI_FIFO_40013000_LABEL
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#define CONFIG_SPI_1_IRQ ST_STM32_SPI_FIFO_40013000_IRQ_0
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#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
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#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
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#define CONFIG_SPI_2_NAME ST_STM32_SPI_FIFO_40003800_LABEL
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#define CONFIG_SPI_2_IRQ ST_STM32_SPI_FIFO_40003800_IRQ_0
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#define FLASH_DEV_BASE_ADDRESS ST_STM32F3_FLASH_CONTROLLER_40022000_BASE_ADDRESS_0
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#define FLASH_DEV_NAME ST_STM32F3_FLASH_CONTROLLER_40022000_LABEL
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@ -27,4 +27,14 @@ config I2C_2
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endif # I2C
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if SPI
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config SPI_1
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default y
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config SPI_2
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default y
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endif # SPI
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endif # BOARD_STM32F3_DISCO
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@ -90,6 +90,8 @@ features:
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+-----------+------------+-------------------------------------+
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| I2C | on-chip | i2c |
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+-----------+------------+-------------------------------------+
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| SPI | on-chip | spi |
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+-----------+------------+-------------------------------------+
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Other hardware features are not yet supported on Zephyr porting.
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@ -116,6 +118,14 @@ Default Zephyr Peripheral Mapping:
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- I2C1_SDA : PB7
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- I2C2_SCL : PA9
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- I2C2_SDA : PA10
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- SPI1_NSS : PA4
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- SPI1_SCK : PA5
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- SPI1_MISO : PA6
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- SPI1_MOSI : PA7
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- SPI2_NSS : PB12
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- SPI2_SCK : PB13
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- SPI2_MISO : PB14
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- SPI2_MOSI : PB15
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- USER_PB : PA0
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- LD3 : PE9
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- LD4 : PE8
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@ -30,6 +30,18 @@ static const struct pin_config pinconf[] = {
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{STM32_PIN_PA9, STM32F3_PINMUX_FUNC_PA9_I2C2_SCL},
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{STM32_PIN_PA10, STM32F3_PINMUX_FUNC_PA10_I2C2_SDA},
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#endif /* CONFIG_I2C_2 */
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#ifdef CONFIG_SPI_1
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{STM32_PIN_PA4, STM32F3_PINMUX_FUNC_PA4_SPI1_NSS},
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{STM32_PIN_PA5, STM32F3_PINMUX_FUNC_PA5_SPI1_SCK},
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{STM32_PIN_PA6, STM32F3_PINMUX_FUNC_PA6_SPI1_MISO},
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{STM32_PIN_PA7, STM32F3_PINMUX_FUNC_PA7_SPI1_MOSI},
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#endif /* CONFIG_SPI_1 */
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#ifdef CONFIG_SPI_2
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{STM32_PIN_PB12, STM32F3_PINMUX_FUNC_PB12_SPI2_NSS},
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{STM32_PIN_PB13, STM32F3_PINMUX_FUNC_PB13_SPI2_SCK},
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{STM32_PIN_PB14, STM32F3_PINMUX_FUNC_PB14_SPI2_MISO},
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{STM32_PIN_PB15, STM32F3_PINMUX_FUNC_PB15_SPI2_MOSI},
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#endif /* CONFIG_SPI_2 */
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};
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static int pinmux_stm32_init(struct device *port)
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@ -41,3 +41,11 @@
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status = "ok";
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clock-frequency = <I2C_BITRATE_FAST>;
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};
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&spi1 {
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status = "ok";
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};
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&spi2 {
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status = "ok";
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};
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@ -22,6 +22,9 @@ CONFIG_UART_CONSOLE=y
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#enable I2C
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CONFIG_I2C=y
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#enable SPI
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CONFIG_SPI=y
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# enable pinmux
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CONFIG_PINMUX=y
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@ -53,4 +53,9 @@
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#define STM32F3_PINMUX_FUNC_PB8_I2C1_SCL (STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
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#define STM32F3_PINMUX_FUNC_PB9_I2C1_SDA (STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
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#define STM32F3_PINMUX_FUNC_PB12_SPI2_NSS (STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
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#define STM32F3_PINMUX_FUNC_PB13_SPI2_SCK (STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
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#define STM32F3_PINMUX_FUNC_PB14_SPI2_MISO (STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
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#define STM32F3_PINMUX_FUNC_PB15_SPI2_MOSI (STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
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#endif /* _STM32F3_PINMUX_H_ */
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@ -5,3 +5,17 @@
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*/
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#include <st/stm32f3.dtsi>
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/ {
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soc {
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spi2: spi@40003800 {
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compatible = "st,stm32-spi-fifo";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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interrupts = <36 5>;
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status = "disabled";
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label = "SPI_2";
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};
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};
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};
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