boards: arm: stm32f3_disco: Enable SPI_1, SPI_2 ports

Enable SPI1 and SPI2 ports on stm32f3_disco.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
This commit is contained in:
Yannis Damigos 2018-02-03 17:40:16 +02:00 committed by Kumar Gala
commit 5d3016aa65
8 changed files with 71 additions and 0 deletions

View file

@ -30,6 +30,15 @@
#define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V2_40005800_IRQ_ERROR
#define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_NAME ST_STM32_SPI_FIFO_40013000_LABEL
#define CONFIG_SPI_1_IRQ ST_STM32_SPI_FIFO_40013000_IRQ_0
#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
#define CONFIG_SPI_2_NAME ST_STM32_SPI_FIFO_40003800_LABEL
#define CONFIG_SPI_2_IRQ ST_STM32_SPI_FIFO_40003800_IRQ_0
#define FLASH_DEV_BASE_ADDRESS ST_STM32F3_FLASH_CONTROLLER_40022000_BASE_ADDRESS_0
#define FLASH_DEV_NAME ST_STM32F3_FLASH_CONTROLLER_40022000_LABEL

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@ -27,4 +27,14 @@ config I2C_2
endif # I2C
if SPI
config SPI_1
default y
config SPI_2
default y
endif # SPI
endif # BOARD_STM32F3_DISCO

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@ -90,6 +90,8 @@ features:
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on Zephyr porting.
@ -116,6 +118,14 @@ Default Zephyr Peripheral Mapping:
- I2C1_SDA : PB7
- I2C2_SCL : PA9
- I2C2_SDA : PA10
- SPI1_NSS : PA4
- SPI1_SCK : PA5
- SPI1_MISO : PA6
- SPI1_MOSI : PA7
- SPI2_NSS : PB12
- SPI2_SCK : PB13
- SPI2_MISO : PB14
- SPI2_MOSI : PB15
- USER_PB : PA0
- LD3 : PE9
- LD4 : PE8

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@ -30,6 +30,18 @@ static const struct pin_config pinconf[] = {
{STM32_PIN_PA9, STM32F3_PINMUX_FUNC_PA9_I2C2_SCL},
{STM32_PIN_PA10, STM32F3_PINMUX_FUNC_PA10_I2C2_SDA},
#endif /* CONFIG_I2C_2 */
#ifdef CONFIG_SPI_1
{STM32_PIN_PA4, STM32F3_PINMUX_FUNC_PA4_SPI1_NSS},
{STM32_PIN_PA5, STM32F3_PINMUX_FUNC_PA5_SPI1_SCK},
{STM32_PIN_PA6, STM32F3_PINMUX_FUNC_PA6_SPI1_MISO},
{STM32_PIN_PA7, STM32F3_PINMUX_FUNC_PA7_SPI1_MOSI},
#endif /* CONFIG_SPI_1 */
#ifdef CONFIG_SPI_2
{STM32_PIN_PB12, STM32F3_PINMUX_FUNC_PB12_SPI2_NSS},
{STM32_PIN_PB13, STM32F3_PINMUX_FUNC_PB13_SPI2_SCK},
{STM32_PIN_PB14, STM32F3_PINMUX_FUNC_PB14_SPI2_MISO},
{STM32_PIN_PB15, STM32F3_PINMUX_FUNC_PB15_SPI2_MOSI},
#endif /* CONFIG_SPI_2 */
};
static int pinmux_stm32_init(struct device *port)

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@ -41,3 +41,11 @@
status = "ok";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi1 {
status = "ok";
};
&spi2 {
status = "ok";
};

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@ -22,6 +22,9 @@ CONFIG_UART_CONSOLE=y
#enable I2C
CONFIG_I2C=y
#enable SPI
CONFIG_SPI=y
# enable pinmux
CONFIG_PINMUX=y

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@ -53,4 +53,9 @@
#define STM32F3_PINMUX_FUNC_PB8_I2C1_SCL (STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32F3_PINMUX_FUNC_PB9_I2C1_SDA (STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32F3_PINMUX_FUNC_PB12_SPI2_NSS (STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
#define STM32F3_PINMUX_FUNC_PB13_SPI2_SCK (STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
#define STM32F3_PINMUX_FUNC_PB14_SPI2_MISO (STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
#define STM32F3_PINMUX_FUNC_PB15_SPI2_MOSI (STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
#endif /* _STM32F3_PINMUX_H_ */

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@ -5,3 +5,17 @@
*/
#include <st/stm32f3.dtsi>
/ {
soc {
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
interrupts = <36 5>;
status = "disabled";
label = "SPI_2";
};
};
};