drivers: flash: Add the flash driver of the stm32f1x family
Most of the code is copied from the stm32f0x family Tested on stm32f103ze soc Signed-off-by: Feng Cheng <i@fengch.me>
This commit is contained in:
parent
5c28f39e7f
commit
ee57c8e749
14 changed files with 255 additions and 24 deletions
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@ -19,6 +19,7 @@ if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
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zephyr_sources(flash_stm32.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F0X flash_stm32f0x.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F1X flash_stm32f1x.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F3X flash_stm32f3x.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X flash_stm32f4x.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X flash_stm32f7x.c)
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@ -8,10 +8,11 @@ if SOC_FAMILY_STM32
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config SOC_FLASH_STM32
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bool "STM32 flash driver"
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depends on (SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32G0X || SOC_SERIES_STM32G4X)
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depends on (SOC_SERIES_STM32F0X || SOC_SERIES_STM32F1X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32G0X || SOC_SERIES_STM32G4X)
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select FLASH_HAS_DRIVER_ENABLED
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default y
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32F0X
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32F1X
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32F3X
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32G0X
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32F4X
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@ -20,6 +21,7 @@ config SOC_FLASH_STM32
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32WBX
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32G4X
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select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32F0X
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select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32F1X
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select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32F3X
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select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32G0X
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select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32F4X
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@ -19,6 +19,9 @@
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#if defined(CONFIG_SOC_SERIES_STM32F0X)
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#define STM32_FLASH_MAX_ERASE_TIME (K_MSEC(40))
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/* STM32F3: maximum erase time of 40ms for a 2K sector */
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#elif defined(CONFIG_SOC_SERIES_STM32F1X)
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#define STM32_FLASH_MAX_ERASE_TIME (K_MSEC(40))
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/* STM32F3: maximum erase time of 40ms for a 2K sector */
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#elif defined(CONFIG_SOC_SERIES_STM32F3X)
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#define STM32_FLASH_MAX_ERASE_TIME (K_MSEC(40))
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/* STM32F4: maximum erase time of 4s for a 128K sector */
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@ -226,6 +229,8 @@ static int flash_stm32_write_protection(struct device *dev, bool enable)
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{
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#if defined(CONFIG_SOC_SERIES_STM32F4X)
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struct stm32f4x_flash *regs = FLASH_STM32_REGS(dev);
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#elif defined(CONFIG_SOC_SERIES_STM32F1X)
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struct stm32f1x_flash *regs = FLASH_STM32_REGS(dev);
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#elif defined(CONFIG_SOC_SERIES_STM32F7X)
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struct stm32f7x_flash *regs = FLASH_STM32_REGS(dev);
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#elif defined(CONFIG_SOC_SERIES_STM32F0X)
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@ -269,6 +274,10 @@ static struct flash_stm32_priv flash_data = {
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.regs = (struct stm32f0x_flash *) DT_FLASH_DEV_BASE_ADDRESS,
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.pclken = { .bus = STM32_CLOCK_BUS_AHB1,
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.enr = LL_AHB1_GRP1_PERIPH_FLASH },
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#elif defined(CONFIG_SOC_SERIES_STM32F1X)
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.regs = (struct stm32f1x_flash *) DT_FLASH_DEV_BASE_ADDRESS,
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.pclken = { .bus = STM32_CLOCK_BUS_AHB1,
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.enr = LL_AHB1_GRP1_PERIPH_FLASH },
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#elif defined(CONFIG_SOC_SERIES_STM32F3X)
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.regs = (struct stm32f3x_flash *) DT_FLASH_DEV_BASE_ADDRESS,
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.pclken = { .bus = STM32_CLOCK_BUS_AHB1,
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@ -316,6 +325,7 @@ static int stm32_flash_init(struct device *dev)
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struct flash_stm32_priv *p = FLASH_STM32_PRIV(dev);
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F1X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X)
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struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
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@ -324,7 +334,9 @@ static int stm32_flash_init(struct device *dev)
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* On STM32F0, Flash interface clock source is always HSI,
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* so statically enable HSI here.
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*/
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32F3X)
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F1X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X)
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LL_RCC_HSI_Enable();
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while (!LL_RCC_HSI_IsReady()) {
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@ -12,6 +12,7 @@
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F1X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32G4X)
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@ -24,6 +25,9 @@ struct flash_stm32_priv {
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struct stm32f0x_flash *regs;
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/* clock subsystem driving this peripheral */
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struct stm32_pclken pclken;
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#elif defined(CONFIG_SOC_SERIES_STM32F1X)
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struct stm32f1x_flash *regs;
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struct stm32_pclken pclken;
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#elif defined(CONFIG_SOC_SERIES_STM32F3X)
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struct stm32f3x_flash *regs;
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/* clock subsystem driving this peripheral */
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167
drivers/flash/flash_stm32f1x.c
Normal file
167
drivers/flash/flash_stm32f1x.c
Normal file
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@ -0,0 +1,167 @@
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/*
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* Copyright (c) 2017 BayLibre, SAS
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* Copyright (c) 2019 Feng Cheng
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define LOG_DOMAIN flash_stm32f1
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#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(LOG_DOMAIN);
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#include <kernel.h>
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#include <device.h>
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#include <string.h>
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#include <drivers/flash.h>
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#include <init.h>
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#include <soc.h>
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#include "flash_stm32.h"
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/* offset and len must be aligned on 2 for write
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* positive and not beyond end of flash
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*/
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bool flash_stm32_valid_range(struct device *dev, off_t offset, u32_t len,
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bool write)
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{
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return (!write || (offset % 2 == 0 && len % 2 == 0U)) &&
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flash_stm32_range_exists(dev, offset, len);
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}
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static unsigned int get_page(off_t offset)
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{
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return offset / FLASH_PAGE_SIZE;
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}
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static int write_hword(struct device *dev, off_t offset, u16_t val)
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{
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volatile u16_t *flash = (u16_t *)(offset + CONFIG_FLASH_BASE_ADDRESS);
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struct stm32f1x_flash *regs = FLASH_STM32_REGS(dev);
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u32_t tmp;
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int rc;
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/* if the control register is locked, do not fail silently */
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if (regs->cr & FLASH_CR_LOCK) {
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return -EIO;
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}
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/* Check that no Flash main memory operation is ongoing */
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rc = flash_stm32_wait_flash_idle(dev);
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if (rc < 0) {
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return rc;
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}
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/* Check if this half word is erased */
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if (*flash != 0xFFFF) {
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return -EIO;
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}
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/* Set the PG bit */
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regs->cr |= FLASH_CR_PG;
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/* Flush the register write */
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tmp = regs->cr;
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/* Perform the data write operation at the desired memory address */
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*flash = val;
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/* Wait until the BSY bit is cleared */
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rc = flash_stm32_wait_flash_idle(dev);
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/* Clear the PG bit */
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regs->cr &= (~FLASH_CR_PG);
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return rc;
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}
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static int erase_page(struct device *dev, unsigned int page)
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{
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struct stm32f1x_flash *regs = FLASH_STM32_REGS(dev);
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u32_t page_address = CONFIG_FLASH_BASE_ADDRESS;
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u32_t tmp;
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int rc;
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/* if the control register is locked, do not fail silently */
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if (regs->cr & FLASH_CR_LOCK) {
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return -EIO;
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}
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/* Check that no Flash memory operation is ongoing */
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rc = flash_stm32_wait_flash_idle(dev);
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if (rc < 0) {
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return rc;
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}
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/* Calculate the flash page address */
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page_address += page * FLASH_PAGE_SIZE;
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/* Set the PER bit and select the page you wish to erase */
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regs->cr |= FLASH_CR_PER;
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regs->ar = page_address;
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/* Set the STRT bit */
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regs->cr |= FLASH_CR_STRT;
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/* flush the register write */
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tmp = regs->cr;
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/* Wait for the BSY bit */
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rc = flash_stm32_wait_flash_idle(dev);
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regs->cr &= ~FLASH_CR_PER;
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return rc;
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}
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int flash_stm32_block_erase_loop(struct device *dev, unsigned int offset,
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unsigned int len)
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{
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int i, rc = 0;
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i = get_page(offset);
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for (; i <= get_page(offset + len - 1) ; ++i) {
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rc = erase_page(dev, i);
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if (rc < 0) {
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break;
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}
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}
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return rc;
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}
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int flash_stm32_write_range(struct device *dev, unsigned int offset,
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const void *data, unsigned int len)
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{
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int i, rc = 0;
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for (i = 0; i < len; i += 2, offset += 2U) {
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rc = write_hword(dev, offset, ((const u16_t *) data)[i>>1]);
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if (rc < 0) {
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return rc;
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}
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}
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return rc;
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}
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void flash_stm32_page_layout(struct device *dev,
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const struct flash_pages_layout **layout,
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size_t *layout_size)
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{
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static struct flash_pages_layout stm32f0_flash_layout = {
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.pages_count = 0,
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.pages_size = 0,
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};
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ARG_UNUSED(dev);
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if (stm32f0_flash_layout.pages_count == 0) {
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stm32f0_flash_layout.pages_count = (CONFIG_FLASH_SIZE * 1024) /
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FLASH_PAGE_SIZE;
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stm32f0_flash_layout.pages_size = FLASH_PAGE_SIZE;
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}
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*layout = &stm32f0_flash_layout;
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*layout_size = 1;
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}
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@ -22,16 +22,30 @@
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};
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};
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flash0: flash@8000000 {
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compatible = "soc-nv-flash";
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label = "FLASH_STM32";
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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soc {
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flash-controller@40022000 {
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compatible = "st,stm32f1-flash-controller";
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label = "FLASH_CTRL";
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reg = <0x40022000 0x400>;
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interrupts = <3 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "soc-nv-flash";
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label = "FLASH_STM32";
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write-block-size = <2>;
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};
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};
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rcc: rcc@40021000 {
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compatible = "st,stm32-rcc";
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#clock-cells = <2>;
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@ -8,15 +8,19 @@
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#include <st/f1/stm32f1.dtsi>
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/ {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(64)>;
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};
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(20)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(64)>;
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erase-block-size = <DT_SIZE_K(1)>;
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};
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};
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/* spi2 is present on all STM32F103x8 SoCs except
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* STM32F103T8. Delete node in stm32f103t8.dtsi.
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*/
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@ -11,14 +11,18 @@
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#include <st/f1/stm32f1.dtsi>
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/ {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(128)>;
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};
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(20)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(128)>;
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erase-block-size = <DT_SIZE_K(1)>;
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};
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};
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/* spi2 is present on all STM32F103xB SoCs except
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* STM32F103TB. Delete node in stm32f103tb.dtsi.
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*/
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@ -11,15 +11,18 @@
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#include <st/f1/stm32f103Xb.dtsi>
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/ {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(512)>;
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};
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(64)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(512)>;
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erase-block-size = <DT_SIZE_K(2)>;
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};
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};
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uart4: serial@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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/ {
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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erase-block-size = <DT_SIZE_K(2)>;
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};
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};
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uart4: serial@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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#include <st/f1/stm32f107.dtsi>
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/ {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(256)>;
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};
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(64)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(256)>;
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};
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};
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};
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};
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title: STM32 F1 Flash Controller
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description: |
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This binding gives a base representation of the STM32 F1 Flash Controller
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compatible: "st,stm32f1-flash-controller"
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include: flash-controller.yaml
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@ -225,7 +225,6 @@
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#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_40012400_CLOCK_BITS_0
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#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_40012400_CLOCK_BUS_0
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#define DT_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS
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#define DT_CAN_1_BUS_SPEED DT_ST_STM32_CAN_40006400_BUS_SPEED
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#define DT_CAN_1_NAME DT_ST_STM32_CAN_40006400_LABEL
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#define DT_CAN_1_CLOCK_BUS DT_ST_STM32_CAN_40006400_CLOCK_BUS
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#define DT_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS
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#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32F1_FLASH_CONTROLLER_40022000_BASE_ADDRESS
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||||
#define DT_FLASH_DEV_NAME DT_ST_STM32F1_FLASH_CONTROLLER_40022000_LABEL
|
||||
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
|
@ -36,7 +36,7 @@ union __ef_acr {
|
|||
};
|
||||
|
||||
/* 3.3.3 Embedded flash registers */
|
||||
struct stm32f10x_flash {
|
||||
struct stm32f1x_flash {
|
||||
volatile union __ef_acr acr;
|
||||
volatile u32_t keyr;
|
||||
volatile u32_t optkeyr;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue