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dts: arm: STM32 boards use DT to configure I2C

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Configure I2C using DT for the following STM32 boards:

disco_l475_iot1
nucleo_f401re
96b_carbon
olimexino_stm32

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
This commit is contained in:
Yannis Damigos 2017-06-29 17:26:38 +03:00 • committed by Kumar Gala
commit 1bc2fdc704
18 changed files with 155 additions and 33 deletions
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3
boards/arm/96b_carbon/Kconfig.defconfig
View file

@ -15,9 +15,6 @@ if I2C_1
config I2C_1_DEFAULT_CFG
default 0x14
config I2C_1_IRQ_PRI
default 0
endif # I2C_1
endif # BOARD_96B_CARBON

6
boards/arm/disco_l475_iot1/Kconfig.defconfig
View file

@ -52,9 +52,6 @@ if I2C_1
config I2C_1_DEFAULT_CFG
default 0x14
config I2C_1_IRQ_PRI
default 0
endif # I2C_1
if I2C_2
@ -62,9 +59,6 @@ if I2C_2
config I2C_2_DEFAULT_CFG
default 0x14
config I2C_2_IRQ_PRI
default 0
endif # I2C_2

3
boards/arm/nucleo_f401re/Kconfig.defconfig
View file

@ -15,9 +15,6 @@ if I2C_1
config I2C_1_DEFAULT_CFG
default 0x14
config I2C_1_IRQ_PRI
default 0
endif # I2C_1
endif # BOARD_NUCLEO_F401RE

3
boards/arm/olimexino_stm32/Kconfig.defconfig
View file

@ -15,9 +15,6 @@ if I2C_2
config I2C_2_DEFAULT_CFG
default 0x14
config I2C_2_IRQ_PRI
default 0
endif # I2C_2
endif # BOARD_OLIMEXINO_STM32

14
drivers/i2c/Kconfig
View file

@ -94,6 +94,7 @@ config I2C_STM32_V1
bool "STM32 V1 Driver (F1/F4X)"
depends on SOC_FAMILY_STM32
depends on SOC_SERIES_STM32F1X || SOC_SERIES_STM32F4X
select HAS_DTS_I2C
default n
help
Enable I2C support on the STM32 F1 and F4X family of processors. This
@ -103,6 +104,7 @@ config I2C_STM32_V2
bool "STM32 V2 Driver (F3/L4X)"
depends on SOC_FAMILY_STM32
depends on SOC_SERIES_STM32F3X || SOC_SERIES_STM32L4X
select HAS_DTS_I2C
default n
help
Enable I2C support on the STM32 F3 and L4X family of processors. This
@ -218,7 +220,7 @@ config I2C_1
config I2C_1_NAME
string "Port 1 device name"
default "I2C_1"
depends on I2C_1
depends on I2C_1 && !HAS_DTS_I2C
config I2C_1_DEFAULT_CFG
hex "Port 1 default configuration"
@ -233,7 +235,7 @@ config I2C_1_DEFAULT_CFG
config I2C_1_IRQ_PRI
int "Port 1 interrupt priority"
depends on I2C_1
depends on I2C_1 && !HAS_DTS_I2C
help
IRQ priority.
@ -244,7 +246,7 @@ config I2C_2
config I2C_2_NAME
string "Port 2 device name"
default "I2C_2"
depends on I2C_2
depends on I2C_2 && !HAS_DTS_I2C
config I2C_2_DEFAULT_CFG
hex "Port 2 default configuration"
@ -259,7 +261,7 @@ config I2C_2_DEFAULT_CFG
config I2C_2_IRQ_PRI
int "Port 2 interrupt priority"
depends on I2C_2
depends on I2C_2 && !HAS_DTS_I2C
help
IRQ priority.
@ -269,7 +271,7 @@ config I2C_3
config I2C_3_NAME
string "Port 3 device name"
depends on I2C_3
depends on I2C_3 && !HAS_DTS_I2C
default "I2C_3"
config I2C_3_DEFAULT_CFG
@ -285,7 +287,7 @@ config I2C_3_DEFAULT_CFG
config I2C_3_IRQ_PRI
int "Port 3 interrupt priority"
depends on I2C_3
depends on I2C_3 && !HAS_DTS_I2C
help
IRQ priority.

24
drivers/i2c/i2c_ll_stm32.c
View file

@ -137,13 +137,13 @@ DEVICE_AND_API_INIT(i2c_stm32_1, CONFIG_I2C_1_NAME, &i2c_stm32_init,
#ifdef CONFIG_I2C_STM32_INTERRUPT
static void i2c_stm32_irq_config_func_1(struct device *dev)
{
IRQ_CONNECT(I2C1_EV_IRQn, CONFIG_I2C_1_IRQ_PRI,
IRQ_CONNECT(CONFIG_I2C_1_EVENT_IRQ, CONFIG_I2C_1_EVENT_IRQ_PRI,
stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_1), 0);
irq_enable(I2C1_EV_IRQn);
irq_enable(CONFIG_I2C_1_EVENT_IRQ);
IRQ_CONNECT(I2C1_ER_IRQn, CONFIG_I2C_1_IRQ_PRI,
IRQ_CONNECT(CONFIG_I2C_1_ERROR_IRQ, CONFIG_I2C_1_ERROR_IRQ_PRI,
stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_1), 0);
irq_enable(I2C1_ER_IRQn);
irq_enable(CONFIG_I2C_1_ERROR_IRQ);
}
#endif
@ -178,13 +178,13 @@ DEVICE_AND_API_INIT(i2c_stm32_2, CONFIG_I2C_2_NAME, &i2c_stm32_init,
#ifdef CONFIG_I2C_STM32_INTERRUPT
static void i2c_stm32_irq_config_func_2(struct device *dev)
{
IRQ_CONNECT(I2C2_EV_IRQn, CONFIG_I2C_2_IRQ_PRI,
IRQ_CONNECT(CONFIG_I2C_2_EVENT_IRQ, CONFIG_I2C_2_EVENT_IRQ_PRI,
stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_2), 0);
irq_enable(I2C2_EV_IRQn);
irq_enable(CONFIG_I2C_2_EVENT_IRQ);
IRQ_CONNECT(I2C2_ER_IRQn, CONFIG_I2C_2_IRQ_PRI,
IRQ_CONNECT(CONFIG_I2C_2_ERROR_IRQ, CONFIG_I2C_2_ERROR_IRQ_PRI,
stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_2), 0);
irq_enable(I2C2_ER_IRQn);
irq_enable(CONFIG_I2C_2_ERROR_IRQ);
}
#endif
@ -223,13 +223,13 @@ DEVICE_AND_API_INIT(i2c_stm32_3, CONFIG_I2C_3_NAME, &i2c_stm32_init,
#ifdef CONFIG_I2C_STM32_INTERRUPT
static void i2c_stm32_irq_config_func_3(struct device *dev)
{
IRQ_CONNECT(I2C3_EV_IRQn, CONFIG_I2C_3_IRQ_PRI,
IRQ_CONNECT(CONFIG_I2C_3_EVENT_IRQ, CONFIG_I2C_3_EVENT_IRQ_PRI,
stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_3), 0);
irq_enable(I2C3_EV_IRQn);
irq_enable(CONFIG_I2C_3_EVENT_IRQ);
IRQ_CONNECT(I2C3_ER_IRQn, CONFIG_I2C_3_IRQ_PRI,
IRQ_CONNECT(CONFIG_I2C_3_ERROR_IRQ, CONFIG_I2C_3_ERROR_IRQ_PRI,
stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_3), 0);
irq_enable(I2C3_ER_IRQn);
irq_enable(CONFIG_I2C_3_ERROR_IRQ);
}
#endif

4
dts/arm/96b_carbon.dts
View file

@ -27,3 +27,7 @@
current-speed = <115200>;
status = "ok";
};
&i2c1 {
status = "ok";
};

7
dts/arm/96b_carbon.fixup
View file

@ -18,3 +18,10 @@
#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY
#define CONFIG_UART_STM32_PORT_2_NAME ST_STM32_USART_40004400_LABEL
#define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0
#define CONFIG_I2C_1_BASE_ADDRESS ST_STM32_I2C_V1_40005400_BASE_ADDRESS
#define CONFIG_I2C_1_EVENT_IRQ_PRI ST_STM32_I2C_V1_40005400_EVENT_PRIORITY
#define CONFIG_I2C_1_ERROR_IRQ_PRI ST_STM32_I2C_V1_40005400_ERROR_PRIORITY
#define CONFIG_I2C_1_NAME ST_STM32_I2C_V1_40005400_LABEL
#define CONFIG_I2C_1_EVENT_IRQ ST_STM32_I2C_V1_40005400_EVENT
#define CONFIG_I2C_1_ERROR_IRQ ST_STM32_I2C_V1_40005400_ERROR

9
dts/arm/disco_l475_iot1.dts
View file

@ -22,6 +22,15 @@
current-speed = <115200>;
status = "ok";
};
&i2c1 {
status = "ok";
};
&i2c2 {
status = "ok";
};
&flash0 {
partitions {
/*

14
dts/arm/disco_l475_iot1.fixup
View file

@ -35,3 +35,17 @@
#define CONFIG_UART_STM32_PORT_5_IRQ_PRI ST_STM32_UART_40005000_IRQ_0_PRIORITY
#define CONFIG_UART_STM32_PORT_5_NAME ST_STM32_UART_40005000_LABEL
#define PORT_5_IRQ ST_STM32_UART_40005000_IRQ_0
#define CONFIG_I2C_1_BASE_ADDRESS ST_STM32_I2C_V2_40005400_BASE_ADDRESS
#define CONFIG_I2C_1_EVENT_IRQ_PRI ST_STM32_I2C_V2_40005400_EVENT_PRIORITY
#define CONFIG_I2C_1_ERROR_IRQ_PRI ST_STM32_I2C_V2_40005400_ERROR_PRIORITY
#define CONFIG_I2C_1_NAME ST_STM32_I2C_V2_40005400_LABEL
#define CONFIG_I2C_1_EVENT_IRQ ST_STM32_I2C_V2_40005400_EVENT
#define CONFIG_I2C_1_ERROR_IRQ ST_STM32_I2C_V2_40005400_ERROR
#define CONFIG_I2C_2_BASE_ADDRESS ST_STM32_I2C_V2_40005800_BASE_ADDRESS
#define CONFIG_I2C_2_EVENT_IRQ_PRI ST_STM32_I2C_V2_40005800_EVENT_PRIORITY
#define CONFIG_I2C_2_ERROR_IRQ_PRI ST_STM32_I2C_V2_40005800_ERROR_PRIORITY
#define CONFIG_I2C_2_NAME ST_STM32_I2C_V2_40005800_LABEL
#define CONFIG_I2C_2_EVENT_IRQ ST_STM32_I2C_V2_40005800_EVENT
#define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V2_40005800_ERROR

4
dts/arm/nucleo_f401re.dts
View file

@ -28,6 +28,10 @@
status = "ok";
};
&i2c1 {
status = "ok";
};
&flash0 {
partitions {
/*

7
dts/arm/nucleo_f401re.fixup
View file

@ -18,3 +18,10 @@
#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY
#define CONFIG_UART_STM32_PORT_2_NAME ST_STM32_USART_40004400_LABEL
#define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0
#define CONFIG_I2C_1_BASE_ADDRESS ST_STM32_I2C_V1_40005400_BASE_ADDRESS
#define CONFIG_I2C_1_EVENT_IRQ_PRI ST_STM32_I2C_V1_40005400_EVENT_PRIORITY
#define CONFIG_I2C_1_ERROR_IRQ_PRI ST_STM32_I2C_V1_40005400_EVENT_PRIORITY
#define CONFIG_I2C_1_NAME ST_STM32_I2C_V1_40005400_LABEL
#define CONFIG_I2C_1_EVENT_IRQ ST_STM32_I2C_V1_40005400_EVENT
#define CONFIG_I2C_1_ERROR_IRQ ST_STM32_I2C_V1_40005400_ERROR

4
dts/arm/olimexino_stm32.dts
View file

@ -22,3 +22,7 @@
current-speed = <115200>;
status = "ok";
};
&i2c2 {
status = "ok";
};

7
dts/arm/olimexino_stm32.fixup
View file

@ -24,3 +24,10 @@
#define CONFIG_UART_STM32_PORT_3_IRQ_PRI ST_STM32_USART_40004800_IRQ_0_PRIORITY
#define CONFIG_UART_STM32_PORT_3_NAME ST_STM32_USART_40004800_LABEL
#define PORT_3_IRQ ST_STM32_USART_40004800_IRQ_0
#define CONFIG_I2C_2_BASE_ADDRESS ST_STM32_I2C_V1_40005800_BASE_ADDRESS
#define CONFIG_I2C_2_EVENT_IRQ_PRI ST_STM32_I2C_V1_40005800_EVENT_PRIORITY
#define CONFIG_I2C_2_ERROR_IRQ_PRI ST_STM32_I2C_V1_40005800_ERROR_PRIORITY
#define CONFIG_I2C_2_NAME ST_STM32_I2C_V1_40005800_LABEL
#define CONFIG_I2C_2_EVENT_IRQ ST_STM32_I2C_V1_40005800_EVENT
#define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V1_40005800_ERROR

18
dts/arm/st/stm32f103Xb.dtsi
View file

@ -43,6 +43,24 @@
status = "disabled";
label = "UART_3";
};
i2c1: i2c@40005400 {
compatible = "st,stm32-i2c-v1";
reg = <0x40005400 0x400>;
interrupts = <31 0>, <32 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_1";
};
i2c2: i2c@40005800 {
compatible = "st,stm32-i2c-v1";
reg = <0x40005800 0x400>;
interrupts = <33 0>, <34 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_2";
};
};
};

27
dts/arm/st/stm32f4.dtsi
View file

@ -40,6 +40,33 @@
status = "disabled";
label = "UART_6";
};
i2c1: i2c@40005400 {
compatible = "st,stm32-i2c-v1";
reg = <0x40005400 0x400>;
interrupts = <31 0>, <32 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_1";
};
i2c2: i2c@40005800 {
compatible = "st,stm32-i2c-v1";
reg = <0x40005800 0x400>;
interrupts = <33 0>, <34 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_2";
};
i2c3: i2c@40005C00 {
compatible = "st,stm32-i2c-v1";
reg = <0x40005C00 0x400>;
interrupts = <72 0>, <73 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_3";
};
};
};

27
dts/arm/st/stm32l475.dtsi
View file

@ -56,6 +56,33 @@
status = "disabled";
label = "UART_5";
};
i2c1: i2c@40005400 {
compatible = "st,stm32-i2c-v2";
reg = <0x40005400 0x400>;
interrupts = <31 0>, <32 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_1";
};
i2c2: i2c@40005800 {
compatible = "st,stm32-i2c-v2";
reg = <0x40005800 0x400>;
interrupts = <33 0>, <34 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_2";
};
i2c3: i2c@40005C00 {
compatible = "st,stm32-i2c-v2";
reg = <0x40005C00 0x400>;
interrupts = <72 0>, <73 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_3";
};
};
};

7
kernel/Kconfig
View file

@ -15,6 +15,13 @@ config HAS_DTS
This option specifies that the target platform supports device tree
configuration.
config HAS_DTS_I2C
bool "I2C uses Device Tree"
depends on HAS_DTS
help
This option specifies that the target platform supports device tree
configuration for I2c.
config MULTITHREADING
bool
prompt "Multi-threading"