dts: arm: STM32 boards use DT to configure I2C
Configure I2C using DT for the following STM32 boards: disco_l475_iot1 nucleo_f401re 96b_carbon olimexino_stm32 Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
This commit is contained in:
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2cacb07216
commit
1bc2fdc704
18 changed files with 155 additions and 33 deletions
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@ -15,9 +15,6 @@ if I2C_1
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config I2C_1_DEFAULT_CFG
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default 0x14
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config I2C_1_IRQ_PRI
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default 0
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endif # I2C_1
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endif # BOARD_96B_CARBON
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@ -52,9 +52,6 @@ if I2C_1
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config I2C_1_DEFAULT_CFG
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default 0x14
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config I2C_1_IRQ_PRI
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default 0
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endif # I2C_1
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if I2C_2
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@ -62,9 +59,6 @@ if I2C_2
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config I2C_2_DEFAULT_CFG
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default 0x14
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config I2C_2_IRQ_PRI
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default 0
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endif # I2C_2
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@ -15,9 +15,6 @@ if I2C_1
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config I2C_1_DEFAULT_CFG
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default 0x14
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config I2C_1_IRQ_PRI
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default 0
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endif # I2C_1
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endif # BOARD_NUCLEO_F401RE
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@ -15,9 +15,6 @@ if I2C_2
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config I2C_2_DEFAULT_CFG
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default 0x14
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config I2C_2_IRQ_PRI
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default 0
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endif # I2C_2
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endif # BOARD_OLIMEXINO_STM32
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@ -94,6 +94,7 @@ config I2C_STM32_V1
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bool "STM32 V1 Driver (F1/F4X)"
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depends on SOC_FAMILY_STM32
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depends on SOC_SERIES_STM32F1X || SOC_SERIES_STM32F4X
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select HAS_DTS_I2C
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default n
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help
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Enable I2C support on the STM32 F1 and F4X family of processors. This
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@ -103,6 +104,7 @@ config I2C_STM32_V2
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bool "STM32 V2 Driver (F3/L4X)"
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depends on SOC_FAMILY_STM32
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depends on SOC_SERIES_STM32F3X || SOC_SERIES_STM32L4X
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select HAS_DTS_I2C
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default n
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help
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Enable I2C support on the STM32 F3 and L4X family of processors. This
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@ -218,7 +220,7 @@ config I2C_1
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config I2C_1_NAME
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string "Port 1 device name"
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default "I2C_1"
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depends on I2C_1
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depends on I2C_1 && !HAS_DTS_I2C
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config I2C_1_DEFAULT_CFG
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hex "Port 1 default configuration"
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@ -233,7 +235,7 @@ config I2C_1_DEFAULT_CFG
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config I2C_1_IRQ_PRI
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int "Port 1 interrupt priority"
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depends on I2C_1
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depends on I2C_1 && !HAS_DTS_I2C
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help
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IRQ priority.
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@ -244,7 +246,7 @@ config I2C_2
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config I2C_2_NAME
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string "Port 2 device name"
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default "I2C_2"
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depends on I2C_2
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depends on I2C_2 && !HAS_DTS_I2C
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config I2C_2_DEFAULT_CFG
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hex "Port 2 default configuration"
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@ -259,7 +261,7 @@ config I2C_2_DEFAULT_CFG
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config I2C_2_IRQ_PRI
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int "Port 2 interrupt priority"
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depends on I2C_2
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depends on I2C_2 && !HAS_DTS_I2C
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help
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IRQ priority.
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@ -269,7 +271,7 @@ config I2C_3
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config I2C_3_NAME
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string "Port 3 device name"
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depends on I2C_3
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depends on I2C_3 && !HAS_DTS_I2C
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default "I2C_3"
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config I2C_3_DEFAULT_CFG
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@ -285,7 +287,7 @@ config I2C_3_DEFAULT_CFG
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config I2C_3_IRQ_PRI
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int "Port 3 interrupt priority"
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depends on I2C_3
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depends on I2C_3 && !HAS_DTS_I2C
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help
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IRQ priority.
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@ -137,13 +137,13 @@ DEVICE_AND_API_INIT(i2c_stm32_1, CONFIG_I2C_1_NAME, &i2c_stm32_init,
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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static void i2c_stm32_irq_config_func_1(struct device *dev)
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{
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IRQ_CONNECT(I2C1_EV_IRQn, CONFIG_I2C_1_IRQ_PRI,
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IRQ_CONNECT(CONFIG_I2C_1_EVENT_IRQ, CONFIG_I2C_1_EVENT_IRQ_PRI,
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stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_1), 0);
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irq_enable(I2C1_EV_IRQn);
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irq_enable(CONFIG_I2C_1_EVENT_IRQ);
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IRQ_CONNECT(I2C1_ER_IRQn, CONFIG_I2C_1_IRQ_PRI,
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IRQ_CONNECT(CONFIG_I2C_1_ERROR_IRQ, CONFIG_I2C_1_ERROR_IRQ_PRI,
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stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_1), 0);
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irq_enable(I2C1_ER_IRQn);
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irq_enable(CONFIG_I2C_1_ERROR_IRQ);
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}
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#endif
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@ -178,13 +178,13 @@ DEVICE_AND_API_INIT(i2c_stm32_2, CONFIG_I2C_2_NAME, &i2c_stm32_init,
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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static void i2c_stm32_irq_config_func_2(struct device *dev)
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{
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IRQ_CONNECT(I2C2_EV_IRQn, CONFIG_I2C_2_IRQ_PRI,
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IRQ_CONNECT(CONFIG_I2C_2_EVENT_IRQ, CONFIG_I2C_2_EVENT_IRQ_PRI,
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stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_2), 0);
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irq_enable(I2C2_EV_IRQn);
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irq_enable(CONFIG_I2C_2_EVENT_IRQ);
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IRQ_CONNECT(I2C2_ER_IRQn, CONFIG_I2C_2_IRQ_PRI,
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IRQ_CONNECT(CONFIG_I2C_2_ERROR_IRQ, CONFIG_I2C_2_ERROR_IRQ_PRI,
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stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_2), 0);
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irq_enable(I2C2_ER_IRQn);
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irq_enable(CONFIG_I2C_2_ERROR_IRQ);
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}
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#endif
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@ -223,13 +223,13 @@ DEVICE_AND_API_INIT(i2c_stm32_3, CONFIG_I2C_3_NAME, &i2c_stm32_init,
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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static void i2c_stm32_irq_config_func_3(struct device *dev)
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{
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IRQ_CONNECT(I2C3_EV_IRQn, CONFIG_I2C_3_IRQ_PRI,
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IRQ_CONNECT(CONFIG_I2C_3_EVENT_IRQ, CONFIG_I2C_3_EVENT_IRQ_PRI,
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stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_3), 0);
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irq_enable(I2C3_EV_IRQn);
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irq_enable(CONFIG_I2C_3_EVENT_IRQ);
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IRQ_CONNECT(I2C3_ER_IRQn, CONFIG_I2C_3_IRQ_PRI,
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IRQ_CONNECT(CONFIG_I2C_3_ERROR_IRQ, CONFIG_I2C_3_ERROR_IRQ_PRI,
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stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_3), 0);
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irq_enable(I2C3_ER_IRQn);
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irq_enable(CONFIG_I2C_3_ERROR_IRQ);
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}
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#endif
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@ -27,3 +27,7 @@
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current-speed = <115200>;
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status = "ok";
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};
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&i2c1 {
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status = "ok";
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};
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@ -18,3 +18,10 @@
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#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY
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#define CONFIG_UART_STM32_PORT_2_NAME ST_STM32_USART_40004400_LABEL
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#define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0
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#define CONFIG_I2C_1_BASE_ADDRESS ST_STM32_I2C_V1_40005400_BASE_ADDRESS
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#define CONFIG_I2C_1_EVENT_IRQ_PRI ST_STM32_I2C_V1_40005400_EVENT_PRIORITY
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#define CONFIG_I2C_1_ERROR_IRQ_PRI ST_STM32_I2C_V1_40005400_ERROR_PRIORITY
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#define CONFIG_I2C_1_NAME ST_STM32_I2C_V1_40005400_LABEL
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#define CONFIG_I2C_1_EVENT_IRQ ST_STM32_I2C_V1_40005400_EVENT
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#define CONFIG_I2C_1_ERROR_IRQ ST_STM32_I2C_V1_40005400_ERROR
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current-speed = <115200>;
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status = "ok";
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};
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&i2c1 {
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status = "ok";
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};
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&i2c2 {
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status = "ok";
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};
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&flash0 {
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partitions {
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/*
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#define CONFIG_UART_STM32_PORT_5_IRQ_PRI ST_STM32_UART_40005000_IRQ_0_PRIORITY
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#define CONFIG_UART_STM32_PORT_5_NAME ST_STM32_UART_40005000_LABEL
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#define PORT_5_IRQ ST_STM32_UART_40005000_IRQ_0
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#define CONFIG_I2C_1_BASE_ADDRESS ST_STM32_I2C_V2_40005400_BASE_ADDRESS
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#define CONFIG_I2C_1_EVENT_IRQ_PRI ST_STM32_I2C_V2_40005400_EVENT_PRIORITY
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#define CONFIG_I2C_1_ERROR_IRQ_PRI ST_STM32_I2C_V2_40005400_ERROR_PRIORITY
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#define CONFIG_I2C_1_NAME ST_STM32_I2C_V2_40005400_LABEL
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#define CONFIG_I2C_1_EVENT_IRQ ST_STM32_I2C_V2_40005400_EVENT
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#define CONFIG_I2C_1_ERROR_IRQ ST_STM32_I2C_V2_40005400_ERROR
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#define CONFIG_I2C_2_BASE_ADDRESS ST_STM32_I2C_V2_40005800_BASE_ADDRESS
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#define CONFIG_I2C_2_EVENT_IRQ_PRI ST_STM32_I2C_V2_40005800_EVENT_PRIORITY
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#define CONFIG_I2C_2_ERROR_IRQ_PRI ST_STM32_I2C_V2_40005800_ERROR_PRIORITY
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#define CONFIG_I2C_2_NAME ST_STM32_I2C_V2_40005800_LABEL
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#define CONFIG_I2C_2_EVENT_IRQ ST_STM32_I2C_V2_40005800_EVENT
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#define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V2_40005800_ERROR
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status = "ok";
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};
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&i2c1 {
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status = "ok";
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};
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&flash0 {
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partitions {
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/*
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#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY
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#define CONFIG_UART_STM32_PORT_2_NAME ST_STM32_USART_40004400_LABEL
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#define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0
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#define CONFIG_I2C_1_BASE_ADDRESS ST_STM32_I2C_V1_40005400_BASE_ADDRESS
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#define CONFIG_I2C_1_EVENT_IRQ_PRI ST_STM32_I2C_V1_40005400_EVENT_PRIORITY
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#define CONFIG_I2C_1_ERROR_IRQ_PRI ST_STM32_I2C_V1_40005400_EVENT_PRIORITY
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#define CONFIG_I2C_1_NAME ST_STM32_I2C_V1_40005400_LABEL
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#define CONFIG_I2C_1_EVENT_IRQ ST_STM32_I2C_V1_40005400_EVENT
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#define CONFIG_I2C_1_ERROR_IRQ ST_STM32_I2C_V1_40005400_ERROR
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current-speed = <115200>;
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status = "ok";
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};
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&i2c2 {
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status = "ok";
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};
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#define CONFIG_UART_STM32_PORT_3_IRQ_PRI ST_STM32_USART_40004800_IRQ_0_PRIORITY
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#define CONFIG_UART_STM32_PORT_3_NAME ST_STM32_USART_40004800_LABEL
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#define PORT_3_IRQ ST_STM32_USART_40004800_IRQ_0
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#define CONFIG_I2C_2_BASE_ADDRESS ST_STM32_I2C_V1_40005800_BASE_ADDRESS
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#define CONFIG_I2C_2_EVENT_IRQ_PRI ST_STM32_I2C_V1_40005800_EVENT_PRIORITY
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#define CONFIG_I2C_2_ERROR_IRQ_PRI ST_STM32_I2C_V1_40005800_ERROR_PRIORITY
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#define CONFIG_I2C_2_NAME ST_STM32_I2C_V1_40005800_LABEL
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#define CONFIG_I2C_2_EVENT_IRQ ST_STM32_I2C_V1_40005800_EVENT
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#define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V1_40005800_ERROR
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status = "disabled";
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label = "UART_3";
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v1";
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reg = <0x40005400 0x400>;
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interrupts = <31 0>, <32 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_1";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v1";
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reg = <0x40005800 0x400>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_2";
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};
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};
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};
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status = "disabled";
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label = "UART_6";
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v1";
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reg = <0x40005400 0x400>;
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interrupts = <31 0>, <32 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_1";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v1";
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reg = <0x40005800 0x400>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_2";
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};
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i2c3: i2c@40005C00 {
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compatible = "st,stm32-i2c-v1";
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reg = <0x40005C00 0x400>;
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interrupts = <72 0>, <73 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_3";
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};
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};
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};
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status = "disabled";
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label = "UART_5";
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v2";
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reg = <0x40005400 0x400>;
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interrupts = <31 0>, <32 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_1";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v2";
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reg = <0x40005800 0x400>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_2";
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};
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i2c3: i2c@40005C00 {
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compatible = "st,stm32-i2c-v2";
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reg = <0x40005C00 0x400>;
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interrupts = <72 0>, <73 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_3";
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};
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};
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};
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@ -15,6 +15,13 @@ config HAS_DTS
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This option specifies that the target platform supports device tree
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configuration.
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config HAS_DTS_I2C
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bool "I2C uses Device Tree"
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depends on HAS_DTS
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help
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This option specifies that the target platform supports device tree
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configuration for I2c.
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config MULTITHREADING
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bool
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prompt "Multi-threading"
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