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dts: xilinx_zynqmp: Fix incorrect RPU device tree specification.

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This commit fixes the following problems with the RPU device tree:

1. The core type of the RPU of ZynqMP SoC is Cortex-R5F, not
  Cortex-R4.

2. RPU and APU use different interrupt controllers (PL390 GICv1 and
  GIC-400 GICv2, respectively) mapped to the same CPU local bus address
  region but with different offsets for the distributor and CPU
  interrupt control register sets. The GIC address mapping specified by
  the current dts is that of an APU and does not apply to the PL390
  GICv1 of an RPU (refer to the "Zynq UltraScale+ Devices Register
  Reference" document from Xilinx for more information).

For more details, refer to the issue #20217.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
Stephanos Ioannidis 2019-10-31 22:50:21 +09:00 • committed by Johan Hedberg
commit 38f0b05b99
1 changed files with 4 additions and 4 deletions
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8
dts/arm/xilinx/zynqmp_rpu.dtsi
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@ -13,7 +13,7 @@
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-r4";
compatible = "arm,cortex-r5f";
reg = <0>;
};
};
@ -21,10 +21,10 @@
soc {
interrupt-parent = <&gic>;
gic: interrupt-controller@f9010000 {
gic: interrupt-controller@f9000000 {
compatible = "arm,gic";
reg = <0xf9010000 0x1000>,
<0xf9020000 0x100>;
reg = <0xf9000000 0x1000>,
<0xf9001000 0x100>;
interrupt-controller;
#interrupt-cells = <4>;
label = "GIC";