dts: NXP LPC gpio updates

NXP's LPC family of MCU's GPIOs parameters is udated.
Boards LPC54xxx and LPC55xxx have updated values according
pin and interrupt layout.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>

dts/arm/nxp/nxp_lpc54xxx.dtsi

@@ -58,7 +58,7 @@
 		};
 
 		gpio0: gpio@0 {
-			compatible = "nxp,kinetis-gpio";
+			compatible = "nxp,lpc-gpio";
 			reg = <0x4008c000 0x2488>;
 			interrupts = <2 2>;
 			label = "GPIO_0";
@@ -67,7 +67,7 @@
 		};
 
 		gpio1: gpio@1 {
-			compatible = "nxp,kinetis-gpio";
+			compatible = "nxp,lpc-gpio";
 			reg = <0x4008C000 0x2488>;
 			interrupts = <3 2>;
 			label = "GPIO_1";

dts/arm/nxp/nxp_lpc55S6x.dtsi

@@ -63,23 +63,39 @@
 			status = "disabled";
 		};
 
-		gpio0: gpio@0 {
-			compatible = "nxp,kinetis-gpio";
+		gpio0:gpio@0 {
+			compatible = "nxp,lpc-gpio";
 			reg = <0x5008c000 0x2488>;
-			interrupts = <2 2>;
+			interrupts = <4 2>;
 			label = "GPIO_0";
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
 
-		gpio1: gpio@1 {
-			compatible = "nxp,kinetis-gpio";
+		gpio1:gpio@1 {
+			compatible = "nxp,lpc-gpio";
 			reg = <0x5008c000 0x2488>;
-			interrupts = <3 2>;
+			interrupts = <5 2>,<6 2>;
 			label = "GPIO_1";
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
+
+		gpio2:gpio@2 {
+			compatible = "nxp,lpc-gpio";
+			reg = <0x5008c000 0x2488>;
+			label = "GPIO_2";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio3:gpio@3 {
+			compatible = "nxp,lpc-gpio";
+			reg = <0x5008c000 0x2488>;
+			label = "GPIO_3";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 	};
 };
 

dts/bindings/gpio/nxp,lpc-gpio.yaml

@@ -0,0 +1,25 @@
+# Copyright (c) 2019, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+title: LPC GPIO
+
+description: |
+    This is a representation of the LPC GPIO nodes
+
+compatible: "nxp,lpc-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags