boards: arm: Add support for Nucleo L432KC

Add configuration, dts and documentation for the Nucleo L432KC board
based on the STM32L432KC SoC.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Neil Armstrong 2017-04-28 14:33:36 +02:00 committed by Anas Nashif
commit 6256c99703
12 changed files with 393 additions and 1 deletions

View file

@ -0,0 +1,11 @@
# Kconfig - STM32L432KC Nucleo board configuration
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 BayLibre, SAS
#
# SPDX-License-Identifier: Apache-2.0
#
config BOARD_NUCLEO_L432KC
bool "Nucleo L432KC Development Board"
depends on SOC_STM32L432XX

View file

@ -0,0 +1,14 @@
# Kconfig - STM32L432KC Nucleo board configuration
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 BayLibre, SAS
#
# SPDX-License-Identifier: Apache-2.0
#
if BOARD_NUCLEO_L432KC
config BOARD
default nucleo_l432kc
endif # BOARD_NUCLEO_L432KC

View file

@ -0,0 +1,2 @@
# No C files (yet)
obj- += dummy.o

View file

@ -0,0 +1,21 @@
/*
* Copyright (c) 2015 Intel Corporation
* Copyright (c) 2017 Linaro Limited.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __INC_BOARD_H
#define __INC_BOARD_H
#include <soc.h>
/* LD3 green LED */
#define LD3_GPIO_PORT "GPIOB"
#define LD3_GPIO_PIN 3
/* Create aliases to make the basic samples work */
#define LED0_GPIO_PORT LD3_GPIO_PORT
#define LED0_GPIO_PIN LD3_GPIO_PIN
#endif /* __INC_BOARD_H */

Binary file not shown.

After

Width:  |  Height:  |  Size: 14 KiB

Binary file not shown.

After

Width:  |  Height:  |  Size: 509 KiB

View file

@ -0,0 +1,237 @@
.. _nucleo_l432kc_board:
ST Nucleo L432KC
################
Overview
********
The Nucleo L432KC board features an ARM Cortex-M4 based STM32L432KC MCU
with a wide range of connectivity support and configurations. Here are
some highlights of the Nucleo L432KC board:
- STM32 microcontroller in UFQFPN32 package
- Arduino Uno V3 connectivity
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
- Flexible board power supply:
- USB VBUS or external source(3.3V, 5V, 7 - 12V)
- Power management access point
- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3)
- One push-button: RESET
.. image:: img/nucleo32_ulp_logo.jpg
:width: 250px
:align: center
:height: 188px
:alt: Nucleo L432KC
More information about the board can be found at the `Nucleo L432KC website`_.
Hardware
********
The STM32L432KC SoC provides the following hardware IPs:
- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 μA/MHz run mode)
- Core: ARM® 32-bit Cortex®-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1)
- Clock Sources:
- 32 kHz crystal oscillator for RTC (LSE)
- Internal 16 MHz factory-trimmed RC (±1%)
- Internal low-power 32 kHz RC (±5%)
- Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy)
- 2 PLLs for system clock, USB, audio, ADC
- RTC with HW calendar, alarms and calibration
- Up to 3 capacitive sensing channels: support touchkey, linear and rotary touch sensors
- 11x timers:
- 1x 16-bit advanced motor-control
- 1x 32-bit and 2x 16-bit general purpose
- 2x 16-bit basic
- 2x low-power 16-bit timers (available in Stop mode)
- 2x watchdogs
- SysTick timer
- Up to 26 fast I/Os, most 5 V-tolerant
- Memories
- Up to 256 KB single bank Flash, proprietary code readout protection
- Up to 64 KB of SRAM including 16 KB with hardware parity check
- Quad SPI memory interface
- Rich analog peripherals (independent supply)
- 1× 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 μA/MSPS
- 2x 12-bit DAC, low-power sample and hold
- 1x operational amplifiers with built-in PGA
- 2x ultra-low-power comparators
- 13x communication interfaces
- USB OTG 2.0 full-speed crystal less solution with LPM and BCD
- 1x SAIs (serial audio interface)
- 2x I2C FM+(1 Mbit/s), SMBus/PMBus
- 3x USARTs (ISO 7816, LIN, IrDA, modem)
- 2x SPIs (3x SPIs with the Quad SPI)
- CAN (2.0B Active)
- SWPMI single wire protocol master I/F
- IRTIM (Infrared interface)
- 14-channel DMA controller
- True random number generator
- CRC calculation unit, 96-bit unique ID
- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™
More information about STM32L432KC can be found here:
- `STM32L432KC on www.st.com`_
- `STM32L432 reference manual`_
Supported Features
==================
The Zephyr nucleo_l432kc board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in the defconfig file:
``boards/arm/nucleo_l432kc/nucleo_l432kc_defconfig``
Connections and IOs
===================
Nucleo L432KC Board has 6 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
Available pins:
---------------
.. image:: img/nucleo_l432kc_arduino_nano.png
:width: 960px
:align: center
:height: 720px
:alt: Nucleo L432KC Arduino connectors
For mode details please refer to `STM32 Nucleo-32 board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_1_TX : PA9
- UART_1_RX : PA10
- UART_2_TX : PA2
- UART_2_RX : PA3
- I2C_1_SCL : PB6
- I2C_1_SDA : PB7
- PWM_2_CH1 : PA0
- LD3 : PB3
System Clock
------------
Nucleo L432KC System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
driven by 16MHz high speed internal oscillator.
Serial Port
-----------
Nucleo L432KC board has 3 U(S)ARTs. The Zephyr console output is assigned to UART2.
Default settings are 115200 8N1.
Programming and Debugging
*************************
Flashing
========
Nucleo L432KC board includes an ST-LINK/V2-1 embedded debug tool interface.
This interface is not supported by the openocd version 0.9 included by the Zephyr SDK v0.9.
Until we update the Zephyr SDK, use openocd v0.10.0 from the openocd-stm32 project on GitHub
to get the minimum set of scripts needed to flash and debug STM32 development boards.
.. code-block:: console
$ git clone https://github.com/erwango/openocd-stm32.git
Then follow instructions in README.md
Flashing an application to Nucleo L432KC
----------------------------------------
The sample application :ref:`hello_world` is being used in this tutorial:
To build the Zephyr kernel and application, enter:
.. code-block:: console
$ cd <zephyr_root_path>
$ source zephyr-env.sh
$ cd $ZEPHYR_BASE/samples/hello_world/
$ make BOARD=nucleo_l432kc
Connect the Nucleo L432KC to your host computer using the USB port.
Then, enter the following command:
.. code-block:: console
$ cd <openocd-stm32_path>
$ stm32_flsh l4 $ZEPHYR_BASE/samples/hello_world/outdir/nucleo_l432kc/zephyr.bin
Run a serial host program to connect with your Nucleo board.
.. code-block:: console
$ minicom -D /dev/ttyACM0
You should see the following message:
.. code-block:: console
$ Hello World! arm
Debugging
=========
Access gdb with the following make command:
.. code-block:: console
$ cd <openocd-stm32_path>
$ stm32_dbg l4 $ZEPHYR_BASE/samples/hello_world/outdir/nucleo_l432kc/zephyr.elf
.. _Nucleo L432KC website:
http://www.st.com/en/evaluation-tools/nucleo-l432kc.html
.. _STM32 Nucleo-32 board User Manual:
http://www.st.com/resource/en/user_manual/dm00231744.pdf
.. _STM32L432KC on www.st.com:
http://www.st.com/en/microcontrollers/stm32l432kc.html
.. _STM32L432 reference manual:
http://www.st.com/resource/en/reference_manual/dm00151940.pdf

View file

@ -0,0 +1,55 @@
CONFIG_ARM=y
CONFIG_BOARD_STM32_NUCLEO_L432KC=y
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32L4X=y
CONFIG_SOC_STM32L432XX=y
CONFIG_CORTEX_M_SYSTICK=y
# 80MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=80000000
# enable uart driver
CONFIG_SERIAL=y
CONFIG_UART_STM32=y
CONFIG_UART_STM32_PORT_2=y
# enable pinmux
CONFIG_PINMUX=y
CONFIG_PINMUX_STM32=y
# enable GPIOs
CONFIG_GPIO=y
CONFIG_GPIO_STM32=y
CONFIG_GPIO_STM32_PORTA=y
CONFIG_GPIO_STM32_PORTB=y
CONFIG_GPIO_STM32_PORTC=y
CONFIG_GPIO_STM32_PORTH=y
# clock configuration
CONFIG_CLOCK_CONTROL=y
CONFIG_CLOCK_CONTROL_STM32_CUBE=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# PLL configuration
CONFIG_CLOCK_STM32_PLL_SRC_HSI
# produce 80MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=20
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=7
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_R_DIVISOR=4
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=1
CONFIG_CLOCK_STM32_APB2_PRESCALER=1
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_2"
#enable pwm
CONFIG_PWM=y
CONFIG_PWM_STM32=y
CONFIG_PWM_STM32_2=y
#enable DTS
CONFIG_HAS_DTS=y

View file

@ -8,6 +8,7 @@ dtb-$(CONFIG_BOARD_HEXIWEAR_KW40Z) = hexiwear_kw40z.dts_compiled
dtb-$(CONFIG_BOARD_CC3200_LAUNCHXL) = cc3200_launchxl.dts_compiled
dtb-$(CONFIG_BOARD_CC3220SF_LAUNCHXL) = cc3220sf_launchxl.dts_compiled
dtb-$(CONFIG_BOARD_NUCLEO_L476RG) = nucleo_l476rg.dts_compiled
dtb-$(CONFIG_BOARD_NUCLEO_L432KC) = nucleo_l432kc.dts_compiled
dtb-$(CONFIG_BOARD_V2M_BEETLE) = v2m_beetle.dts_compiled
dtb-$(CONFIG_BOARD_OLIMEXINO_STM32) = olimexino_stm32.dts_compiled
dtb-$(CONFIG_BOARD_96B_CARBON) = 96b_carbon.dts_compiled

24
dts/arm/nucleo_l432kc.dts Normal file
View file

@ -0,0 +1,24 @@
/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <st/stm32l432.dtsi>
/ {
model = "STMicroelectronics STM32L432KC-NUCLEO board";
compatible = "st,stm32l432kc-nucleo", "st,stm32l432";
chosen {
zephyr,console = &usart2;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
};
&usart2 {
current-speed = <115200>;
status = "ok";
};

View file

@ -0,0 +1,27 @@
/* This file is a temporary workaround for mapping of the generated information
* to the current driver definitions. This will be removed when the drivers
* are modified to handle the generated information, or the mapping of
* generated data matches the driver definitions.
*/
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_CURRENT_SPEED
#define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40013800_IRQ_0_PRIORITY
#define PORT_1_IRQ ST_STM32_USART_40013800_IRQ_0
#define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_CURRENT_SPEED
#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY
#define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0
#define CONFIG_UART_STM32_PORT_3_BASE_ADDRESS ST_STM32_USART_40004800_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_3_BAUD_RATE ST_STM32_USART_40004800_CURRENT_SPEED
#define CONFIG_UART_STM32_PORT_3_IRQ_PRI ST_STM32_USART_40004800_IRQ_0_PRIORITY
#define PORT_3_IRQ ST_STM32_USART_40004800_IRQ_0
#define CONFIG_UART_STM32_PORT_4_BASE_ADDRESS ST_STM32_USART_40004C00_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_4_BAUD_RATE ST_STM32_USART_40004C00_CURRENT_SPEED
#define CONFIG_UART_STM32_PORT_4_IRQ_PRI ST_STM32_USART_40004C00_IRQ_0_PRIORITY
#define PORT_4_IRQ ST_STM32_USART_40004C00_IRQ_0

View file

@ -7,7 +7,7 @@ platforms = qemu_cortex_m3 frdm_k64f arduino_due nucleo_f103rb stm32_mini_a15
v2m_beetle nucleo_l476rg nrf52840_pca10056 nucleo_f411re
stm3210c_eval nucleo_f334r8 stm32373c_eval mps2_an385 frdm_kw41z
sam_e70_xplained curie_ble nrf52_blenano2 hexiwear_kw40z
cc3220sf_launchxl frdm_kl25z disco_l475_iot1
cc3220sf_launchxl frdm_kl25z disco_l475_iot1 nucleo_l432kc
supported_toolchains = zephyr gccarmemb