dts: arm: st: Add dts and soc additions for stm32 F767ZI board

Added dts additions for stm32 nucleo f767zi board, also added
and modified soc addtions for thet board.
Updated dts reference file name.
Updated yaml to take out adc for now.

Signed-off-by: Roland Ma <rolandma@yahoo.com>

boards/arm/nucleo_f767zi/nucleo_f767zi.dts

@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2019 Roland Ma
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/f7/stm32f767Xi.dtsi>
+#include "arduino_r3_connector.dtsi"
+
+/ {
+	model = "STMicroelectronics STM32F767ZI-NUCLEO board";
+	compatible = "st,stm32f767zi-nucleo", "st,stm32f767";
+
+	chosen {
+		zephyr,console = &usart3;
+		zephyr,shell-uart = &usart3;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,dtcm = &dtcm;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		green_led: led_0 {
+			gpios = <&gpiob 0 GPIO_INT_ACTIVE_HIGH>;
+			label = "User LD1";
+		};
+		blue_led: led_1 {
+			gpios = <&gpiob 7 GPIO_INT_ACTIVE_HIGH>;
+			label = "User LD2";
+		};
+		red_led: led_2 {
+			gpios = <&gpiob 14 GPIO_INT_ACTIVE_HIGH>;
+			label = "User LD3";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button: button_0 {
+			label = "User";
+			gpios = <&gpioc 13 GPIO_INT_ACTIVE_LOW>;
+		};
+	};
+
+	aliases {
+		led0 = &green_led;
+		led1 = &blue_led;
+		led2 = &red_led;
+		sw0 = &user_button;
+	};
+};
+
+&usart3 {
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&usart6 {
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&usbotg_fs {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&timers1 {
+	status = "okay";
+
+	pwm {
+		status = "okay";
+	};
+};
+
+&spi1 {
+	/*
+	 * WARNING: The pin PA7 will conflict on selection of SPI_1 and
+	 *          ETH_STM32_HAL. See pinmux.c for further details.
+	 */
+	status = "okay";
+};
+
+&iwdg {
+	status = "okay";
+};
+
+&rtc {
+	status = "okay";
+};
+
+&can1 {
+	bus-speed = <125000>;
+	sjw = <1>;
+	prop-seg = <0>;
+	phase-seg1 = <6>;
+	phase-seg2 = <5>;
+	status = "okay";
+};
+
+&adc1 {
+	status = "okay";
+};

boards/arm/nucleo_f767zi/nucleo_f767zi.yaml

@@ -0,0 +1,24 @@
+identifier: nucleo_f767zi
+name: NUCLEO-F767ZI
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+ram: 512
+flash: 2048
+supported:
+  - arduino_i2c
+  - arduino_gpio
+  - arduino_spi
+  - uart
+  - gpio
+  - netif:eth
+  - usb_device
+  - i2c
+  - pwm
+  - spi
+  - watchdog
+  - counter
+  - can

dts/arm/st/f7/stm32f767.dtsi

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2019 Roland Ma
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f7/stm32f7.dtsi>
+
+/ {
+	/* 128KB DTCM @ 20000000, 368KB SRAM1 @ 20020000,
+	 * 16KB SRAM2 @ 2007C000
+	 */
+
+	sram0: memory@20020000 {
+		compatible = "mmio-sram";
+		reg = <0x20020000 DT_SIZE_K(384)>;
+	};
+
+	dtcm: memory@20000000 {
+		compatible = "arm,dtcm";
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		pinctrl: pin-controller@40020000 {
+			reg = <0x40020000 0x2C00>;
+
+			gpioj: gpio@40022400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40022400 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
+				label = "GPIOJ";
+			};
+
+			gpiok: gpio@40022800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x40022800 0x400>;
+				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
+				label = "GPIOK";
+			};
+		};
+
+		i2c4: i2c@40006000 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40006000 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
+			interrupts = <95 0>, <96 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label = "I2C_4";
+		};
+	};
+};

dts/arm/st/f7/stm32f767Xi.dtsi

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2019 Roland Ma
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f7/stm32f767.dtsi>
+
+/ {
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};

soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f767xx

@@ -0,0 +1,27 @@
+# Kconfig - ST STM32F767ZI MCU configuration options
+#
+# Copyright (c) 2019 Roland Ma
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F767XX
+
+config SOC
+	default "stm32f767xx"
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTJ
+	default y
+
+config GPIO_STM32_PORTK
+	default y
+
+endif # GPIO_STM32
+
+config NUM_IRQS
+	default 110
+
+endif # SOC_STM32F767XX
+

soc/arm/st_stm32/stm32f7/Kconfig.soc

@@ -16,6 +16,10 @@ config SOC_STM32F746XX
 config SOC_STM32F756XX
 	bool "STM32F756XX"
 
+config SOC_STM32F767XX
+	bool "STM32F767XX"
+	select CPU_HAS_FPU_DOUBLE_PRECISION
+
 config SOC_STM32F769XX
 	bool "STM32F769XX"
 	select CPU_HAS_FPU_DOUBLE_PRECISION