michaelh/zephyr
1
0
Fork 0
Code Releases Activity

dts: Add Kinetis SIM clock bindings

Browse source 
Adds device tree bindings for the Kinetis System Integration Module
(SIM), and defines peripheral source clocks (e.g., system clock or bus
clock) and clock gates for all Kinetis SoCs.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm 2017-08-25 17:13:39 -05:00 • committed by Kumar Gala
commit 3291735d11
14 changed files with 187 additions and 60 deletions
Download patch file Download diff file Expand all files Collapse all files

15
dts/arm/frdm_k64f.fixup
View file

@ -6,6 +6,8 @@
#define CONFIG_UART_MCUX_0_IRQ_ERROR_PRI NXP_KINETIS_UART_4006A000_IRQ_ERROR_PRIORITY
#define CONFIG_UART_MCUX_0_IRQ_STATUS NXP_KINETIS_UART_4006A000_IRQ_STATUS
#define CONFIG_UART_MCUX_0_IRQ_STATUS_PRI NXP_KINETIS_UART_4006A000_IRQ_STATUS_PRIORITY
#define CONFIG_UART_MCUX_0_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_0_CLOCK_SUBSYS NXP_KINETIS_UART_4006A000_SIM_CLK_NAME_0
#define CONFIG_UART_MCUX_1_BAUD_RATE NXP_KINETIS_UART_4006B000_CURRENT_SPEED
#define CONFIG_UART_MCUX_1_NAME NXP_KINETIS_UART_4006B000_LABEL
@ -13,6 +15,8 @@
#define CONFIG_UART_MCUX_1_IRQ_ERROR_PRI NXP_KINETIS_UART_4006B000_IRQ_ERROR_PRIORITY
#define CONFIG_UART_MCUX_1_IRQ_STATUS NXP_KINETIS_UART_4006B000_IRQ_STATUS
#define CONFIG_UART_MCUX_1_IRQ_STATUS_PRI NXP_KINETIS_UART_4006B000_IRQ_STATUS_PRIORITY
#define CONFIG_UART_MCUX_1_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_1_CLOCK_SUBSYS NXP_KINETIS_UART_4006B000_SIM_CLK_NAME_0
#define CONFIG_UART_MCUX_2_BAUD_RATE NXP_KINETIS_UART_4006C000_CURRENT_SPEED
#define CONFIG_UART_MCUX_2_NAME NXP_KINETIS_UART_4006C000_LABEL
@ -20,6 +24,8 @@
#define CONFIG_UART_MCUX_2_IRQ_ERROR_PRI NXP_KINETIS_UART_4006C000_IRQ_ERROR_PRIORITY
#define CONFIG_UART_MCUX_2_IRQ_STATUS NXP_KINETIS_UART_4006C000_IRQ_STATUS
#define CONFIG_UART_MCUX_2_IRQ_STATUS_PRI NXP_KINETIS_UART_4006C000_IRQ_STATUS_PRIORITY
#define CONFIG_UART_MCUX_2_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_2_CLOCK_SUBSYS NXP_KINETIS_UART_4006C000_SIM_CLK_NAME_0
#define CONFIG_UART_MCUX_3_BAUD_RATE NXP_KINETIS_UART_4006D000_CURRENT_SPEED
#define CONFIG_UART_MCUX_3_NAME NXP_KINETIS_UART_4006D000_LABEL
@ -27,6 +33,8 @@
#define CONFIG_UART_MCUX_3_IRQ_ERROR_PRI NXP_KINETIS_UART_4006D000_IRQ_ERROR_PRIORITY
#define CONFIG_UART_MCUX_3_IRQ_STATUS NXP_KINETIS_UART_4006D000_IRQ_STATUS
#define CONFIG_UART_MCUX_3_IRQ_STATUS_PRI NXP_KINETIS_UART_4006D000_IRQ_STATUS_PRIORITY
#define CONFIG_UART_MCUX_3_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_3_CLOCK_SUBSYS NXP_KINETIS_UART_4006D000_SIM_CLK_NAME_0
#define CONFIG_UART_MCUX_4_BAUD_RATE NXP_KINETIS_UART_400EA000_CURRENT_SPEED
#define CONFIG_UART_MCUX_4_NAME NXP_KINETIS_UART_400EA000_LABEL
@ -34,6 +42,8 @@
#define CONFIG_UART_MCUX_4_IRQ_ERROR_PRI NXP_KINETIS_UART_400EA000_IRQ_ERROR_PRIORITY
#define CONFIG_UART_MCUX_4_IRQ_STATUS NXP_KINETIS_UART_400EA000_IRQ_STATUS
#define CONFIG_UART_MCUX_4_IRQ_STATUS_PRI NXP_KINETIS_UART_400EA000_IRQ_STATUS_PRIORITY
#define CONFIG_UART_MCUX_4_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_4_CLOCK_SUBSYS NXP_KINETIS_UART_400EA000_SIM_CLK_NAME_0
#define CONFIG_UART_MCUX_5_BAUD_RATE NXP_KINETIS_UART_400EB000_CURRENT_SPEED
#define CONFIG_UART_MCUX_5_NAME NXP_KINETIS_UART_400EB000_LABEL
@ -41,6 +51,8 @@
#define CONFIG_UART_MCUX_5_IRQ_ERROR_PRI NXP_KINETIS_UART_400EB000_IRQ_ERROR_PRIORITY
#define CONFIG_UART_MCUX_5_IRQ_STATUS NXP_KINETIS_UART_400EB000_IRQ_STATUS
#define CONFIG_UART_MCUX_5_IRQ_STATUS_PRI NXP_KINETIS_UART_400EB000_IRQ_STATUS_PRIORITY
#define CONFIG_UART_MCUX_5_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_5_CLOCK_SUBSYS NXP_KINETIS_UART_400EB000_SIM_CLK_NAME_0
#define CONFIG_ADC_0_BASE_ADDRESS NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS_0
#define CONFIG_ADC_0_IRQ NXP_KINETIS_ADC16_4003B000_IRQ_0
@ -57,6 +69,9 @@
#define CONFIG_FTM_3_IRQ_PRI NXP_KINETIS_FTM_400B9000_IRQ_0_PRIORITY
#define CONFIG_FTM_3_NAME NXP_KINETIS_FTM_400B9000_LABEL
#define CONFIG_SIM_BASE_ADDRESS NXP_KINETIS_SIM_40047000_BASE_ADDRESS_0
#define CONFIG_SIM_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_I2C_0_NAME NXP_KINETIS_I2C_40066000_LABEL
#define CONFIG_FXOS8700_I2C_NAME NXP_KINETIS_I2C_40066000_LABEL
#define CONFIG_I2C_MCUX_0_BASE_ADDRESS NXP_KINETIS_I2C_40066000_BASE_ADDRESS_0

5
dts/arm/frdm_kl25z.fixup
View file

@ -1,11 +1,16 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define CONFIG_UART_MCUX_LPSCI_0_NAME NXP_KINETIS_LPSCI_4006A000_LABEL
#define CONFIG_UART_MCUX_LPSCI_0_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_LPSCI_0_CLOCK_SUBSYS NXP_KINETIS_LPSCI_4006A000_SIM_CLK_NAME_0
#define CONFIG_ADC_0_BASE_ADDRESS NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS_0
#define CONFIG_ADC_0_IRQ NXP_KINETIS_ADC16_4003B000_IRQ_0
#define CONFIG_ADC_0_IRQ_PRI NXP_KINETIS_ADC16_4003B000_IRQ_0_PRIORITY
#define CONFIG_ADC_0_NAME NXP_KINETIS_ADC16_4003B000_LABEL
#define CONFIG_SIM_BASE_ADDRESS NXP_KINETIS_SIM_40047000_BASE_ADDRESS_0
#define CONFIG_SIM_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_I2C_0_NAME NXP_KINETIS_I2C_40066000_LABEL
#define CONFIG_I2C_MCUX_0_BASE_ADDRESS NXP_KINETIS_I2C_40066000_BASE_ADDRESS_0
#define CONFIG_I2C_MCUX_0_IRQ NXP_KINETIS_I2C_40066000_IRQ_0

5
dts/arm/frdm_kw41z.fixup
View file

@ -4,12 +4,17 @@
#define CONFIG_UART_MCUX_LPUART_0_IRQ NXP_KINETIS_LPUART_40054000_IRQ_0
#define CONFIG_UART_MCUX_LPUART_0_IRQ_PRI NXP_KINETIS_LPUART_40054000_IRQ_0_PRIORITY
#define CONFIG_UART_MCUX_LPUART_0_NAME NXP_KINETIS_LPUART_40054000_LABEL
#define CONFIG_UART_MCUX_LPUART_0_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_LPUART_0_CLOCK_SUBSYS NXP_KINETIS_LPUART_40054000_SIM_CLK_NAME_0
#define CONFIG_ADC_0_BASE_ADDRESS NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS_0
#define CONFIG_ADC_0_IRQ NXP_KINETIS_ADC16_4003B000_IRQ_0
#define CONFIG_ADC_0_IRQ_PRI NXP_KINETIS_ADC16_4003B000_IRQ_0_PRIORITY
#define CONFIG_ADC_0_NAME NXP_KINETIS_ADC16_4003B000_LABEL
#define CONFIG_SIM_BASE_ADDRESS NXP_KINETIS_SIM_40047000_BASE_ADDRESS_0
#define CONFIG_SIM_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_I2C_1_NAME NXP_KINETIS_I2C_40067000_LABEL
#define CONFIG_FXOS8700_I2C_NAME NXP_KINETIS_I2C_40067000_LABEL
#define CONFIG_I2C_MCUX_1_BASE_ADDRESS NXP_KINETIS_I2C_40067000_BASE_ADDRESS_0

15
dts/arm/hexiwear_k64.fixup
View file

@ -6,6 +6,8 @@
#define CONFIG_UART_MCUX_0_IRQ_ERROR_PRI NXP_KINETIS_UART_4006A000_IRQ_ERROR_PRIORITY
#define CONFIG_UART_MCUX_0_IRQ_STATUS NXP_KINETIS_UART_4006A000_IRQ_STATUS
#define CONFIG_UART_MCUX_0_IRQ_STATUS_PRI NXP_KINETIS_UART_4006A000_IRQ_STATUS_PRIORITY
#define CONFIG_UART_MCUX_0_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_0_CLOCK_SUBSYS NXP_KINETIS_UART_4006A000_SIM_CLK_NAME_0
#define CONFIG_UART_MCUX_1_BAUD_RATE NXP_KINETIS_UART_4006B000_CURRENT_SPEED
#define CONFIG_UART_MCUX_1_NAME NXP_KINETIS_UART_4006B000_LABEL
@ -13,6 +15,8 @@
#define CONFIG_UART_MCUX_1_IRQ_ERROR_PRI NXP_KINETIS_UART_4006B000_IRQ_ERROR_PRIORITY
#define CONFIG_UART_MCUX_1_IRQ_STATUS NXP_KINETIS_UART_4006B000_IRQ_STATUS
#define CONFIG_UART_MCUX_1_IRQ_STATUS_PRI NXP_KINETIS_UART_4006B000_IRQ_STATUS_PRIORITY
#define CONFIG_UART_MCUX_1_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_1_CLOCK_SUBSYS NXP_KINETIS_UART_4006B000_SIM_CLK_NAME_0
#define CONFIG_UART_MCUX_2_BAUD_RATE NXP_KINETIS_UART_4006C000_CURRENT_SPEED
#define CONFIG_UART_MCUX_2_NAME NXP_KINETIS_UART_4006C000_LABEL
@ -20,6 +24,8 @@
#define CONFIG_UART_MCUX_2_IRQ_ERROR_PRI NXP_KINETIS_UART_4006C000_IRQ_ERROR_PRIORITY
#define CONFIG_UART_MCUX_2_IRQ_STATUS NXP_KINETIS_UART_4006C000_IRQ_STATUS
#define CONFIG_UART_MCUX_2_IRQ_STATUS_PRI NXP_KINETIS_UART_4006C000_IRQ_STATUS_PRIORITY
#define CONFIG_UART_MCUX_2_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_2_CLOCK_SUBSYS NXP_KINETIS_UART_4006C000_SIM_CLK_NAME_0
#define CONFIG_UART_MCUX_3_BAUD_RATE NXP_KINETIS_UART_4006D000_CURRENT_SPEED
#define CONFIG_UART_MCUX_3_NAME NXP_KINETIS_UART_4006D000_LABEL
@ -27,6 +33,8 @@
#define CONFIG_UART_MCUX_3_IRQ_ERROR_PRI NXP_KINETIS_UART_4006D000_IRQ_ERROR_PRIORITY
#define CONFIG_UART_MCUX_3_IRQ_STATUS NXP_KINETIS_UART_4006D000_IRQ_STATUS
#define CONFIG_UART_MCUX_3_IRQ_STATUS_PRI NXP_KINETIS_UART_4006D000_IRQ_STATUS_PRIORITY
#define CONFIG_UART_MCUX_3_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_3_CLOCK_SUBSYS NXP_KINETIS_UART_4006D000_SIM_CLK_NAME_0
#define CONFIG_UART_MCUX_4_BAUD_RATE NXP_KINETIS_UART_400EA000_CURRENT_SPEED
#define CONFIG_UART_MCUX_4_NAME NXP_KINETIS_UART_400EA000_LABEL
@ -34,6 +42,8 @@
#define CONFIG_UART_MCUX_4_IRQ_ERROR_PRI NXP_KINETIS_UART_400EA000_IRQ_ERROR_PRIORITY
#define CONFIG_UART_MCUX_4_IRQ_STATUS NXP_KINETIS_UART_400EA000_IRQ_STATUS
#define CONFIG_UART_MCUX_4_IRQ_STATUS_PRI NXP_KINETIS_UART_400EA000_IRQ_STATUS_PRIORITY
#define CONFIG_UART_MCUX_4_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_4_CLOCK_SUBSYS NXP_KINETIS_UART_400EA000_SIM_CLK_NAME_0
#define CONFIG_UART_MCUX_5_BAUD_RATE NXP_KINETIS_UART_400EB000_CURRENT_SPEED
#define CONFIG_UART_MCUX_5_NAME NXP_KINETIS_UART_400EB000_LABEL
@ -41,6 +51,8 @@
#define CONFIG_UART_MCUX_5_IRQ_ERROR_PRI NXP_KINETIS_UART_400EB000_IRQ_ERROR_PRIORITY
#define CONFIG_UART_MCUX_5_IRQ_STATUS NXP_KINETIS_UART_400EB000_IRQ_STATUS
#define CONFIG_UART_MCUX_5_IRQ_STATUS_PRI NXP_KINETIS_UART_400EB000_IRQ_STATUS_PRIORITY
#define CONFIG_UART_MCUX_5_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_5_CLOCK_SUBSYS NXP_KINETIS_UART_400EB000_SIM_CLK_NAME_0
#define CONFIG_ADC_0_BASE_ADDRESS NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS_0
#define CONFIG_ADC_0_IRQ NXP_KINETIS_ADC16_4003B000_IRQ_0
@ -57,6 +69,9 @@
#define CONFIG_FTM_3_IRQ_PRI NXP_KINETIS_FTM_400B9000_IRQ_0_PRIORITY
#define CONFIG_FTM_3_NAME NXP_KINETIS_FTM_400B9000_LABEL
#define CONFIG_SIM_BASE_ADDRESS NXP_KINETIS_SIM_40047000_BASE_ADDRESS_0
#define CONFIG_SIM_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_I2C_0_NAME NXP_KINETIS_I2C_40066000_LABEL
#define CONFIG_MAX30101_I2C_NAME NXP_KINETIS_I2C_40066000_LABEL
#define CONFIG_I2C_MCUX_0_BASE_ADDRESS NXP_KINETIS_I2C_40066000_BASE_ADDRESS_0

5
dts/arm/hexiwear_kw40z.fixup
View file

@ -4,12 +4,17 @@
#define CONFIG_UART_MCUX_LPUART_0_IRQ NXP_KINETIS_LPUART_40054000_IRQ_0
#define CONFIG_UART_MCUX_LPUART_0_IRQ_PRI NXP_KINETIS_LPUART_40054000_IRQ_0_PRIORITY
#define CONFIG_UART_MCUX_LPUART_0_NAME NXP_KINETIS_LPUART_40054000_LABEL
#define CONFIG_UART_MCUX_LPUART_0_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_LPUART_0_CLOCK_SUBSYS NXP_KINETIS_LPUART_40054000_SIM_CLK_NAME_0
#define CONFIG_ADC_0_BASE_ADDRESS NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS_0
#define CONFIG_ADC_0_IRQ NXP_KINETIS_ADC16_4003B000_IRQ_0
#define CONFIG_ADC_0_IRQ_PRI NXP_KINETIS_ADC16_4003B000_IRQ_0_PRIORITY
#define CONFIG_ADC_0_NAME NXP_KINETIS_ADC16_4003B000_LABEL
#define CONFIG_SIM_BASE_ADDRESS NXP_KINETIS_SIM_40047000_BASE_ADDRESS_0
#define CONFIG_SIM_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_I2C_1_NAME NXP_KINETIS_I2C_40067000_LABEL
#define CONFIG_I2C_MCUX_1_BASE_ADDRESS NXP_KINETIS_I2C_40067000_BASE_ADDRESS_0
#define CONFIG_I2C_MCUX_1_IRQ NXP_KINETIS_I2C_40067000_IRQ_0

31
dts/arm/nxp/nxp_k6x.dtsi
View file

@ -1,4 +1,5 @@
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/kinetis_sim.h>
#include <dt-bindings/i2c/i2c.h>
/ {
@ -50,8 +51,9 @@
};
sim: sim@40047000 {
compatible = "nxp,k64f-sim";
compatible = "nxp,kinetis-sim";
reg = <0x40047000 0x1060>;
label = "SIM";
clk-divider-core = <1>;
clk-divider-bus = <2>;
@ -59,7 +61,7 @@
clk-divider-flash = <5>;
clock-controller;
#clock-cells = <2>;
#clocks-cells = <3>;
};
flash-controller@4001f000 {
@ -85,6 +87,7 @@
#size-cells = <0>;
reg = <0x40066000 0x1000>;
interrupts = <24 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
label = "I2C_0";
status = "disabled";
};
@ -96,6 +99,7 @@
#size-cells = <0>;
reg = <0x40067000 0x1000>;
interrupts = <25 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
label = "I2C_1";
status = "disabled";
};
@ -107,6 +111,7 @@
#size-cells = <0>;
reg = <0x400e6000 0x1000>;
interrupts = <74 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 6>;
label = "I2C_2";
status = "disabled";
};
@ -116,6 +121,7 @@
reg = <0x4006a000 0x1000>;
interrupts = <31 0>, <32 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>;
label = "UART_0";
pinctrl-0 = <&uart0_default>;
@ -129,6 +135,7 @@
reg = <0x4006b000 0x1000>;
interrupts = <33 0>, <34 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 11>;
label = "UART_1";
status = "disabled";
@ -139,6 +146,7 @@
reg = <0x4006c000 0x1000>;
interrupts = <35 0>, <36 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 12>;
label = "UART_2";
status = "disabled";
@ -149,6 +157,7 @@
reg = <0x4006d000 0x1000>;
interrupts = <37 0>, <38 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 13>;
label = "UART_3";
status = "disabled";
@ -159,6 +168,7 @@
reg = <0x400ea000 0x1000>;
interrupts = <66 0>, <67 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 10>;
label = "UART_4";
status = "disabled";
@ -169,6 +179,7 @@
reg = <0x400eb000 0x1000>;
interrupts = <68 0>, <69 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 11>;
label = "UART_5";
status = "disabled";
@ -177,15 +188,13 @@
pinmux_a: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x40049000 0xd0>;
clocks = <&sim 0x1038 9>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
};
pinmux_b: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004a000 0xd0>;
clocks = <&sim 0x1038 10>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
uart0_default: uart0_default {
rx-tx {
pins = <16>, <17>;
@ -211,19 +220,19 @@
pinmux_c: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004b000 0xd0>;
clocks = <&sim 0x1038 11>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
};
pinmux_d: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004c000 0xd0>;
clocks = <&sim 0x1038 12>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
};
pinmux_e: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004d000 0xd0>;
clocks = <&sim 0x1038 13>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
};
gpioa: gpio@400ff000 {
@ -275,7 +284,7 @@
compatible = "nxp,k64f-spi";
reg = <0x4002c000 0x88>;
interrupts = <26 0>;
clocks = <&sim 0x103C 12>; /* clk gate */
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>;
cs = <&gpiob 10 0>, <&gpiob 9 0>;
pinctrl-0 = <&spi0_default>;
@ -286,7 +295,7 @@
compatible = "nxp,k64f-spi";
reg = <0x4002d000 0x88>;
interrupts = <0 0>;
clocks = <&sim 0x103C 13>; /* clk gate */
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>;
status = "disabled";
};

18
dts/arm/nxp/nxp_kl25z.dtsi
View file

@ -1,4 +1,5 @@
#include "armv6-m.dtsi"
#include <dt-bindings/clock/kinetis_sim.h>
#include <dt-bindings/i2c/i2c.h>
/ {
@ -31,6 +32,7 @@
#size-cells = <0>;
reg = <0x40066000 0x1000>;
interrupts = <8 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
label = "I2C_0";
status = "disabled";
};
@ -42,14 +44,30 @@
#size-cells = <0>;
reg = <0x40067000 0x1000>;
interrupts = <9 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
label = "I2C_1";
status = "disabled";
};
sim: sim@40047000 {
compatible = "nxp,kinetis-sim";
reg = <0x40047000 0x1060>;
label = "SIM";
clk-divider-core = <1>;
clk-divider-bus = <2>;
clk-divider-flexbus = <3>;
clk-divider-flash = <5>;
clock-controller;
#clocks-cells = <3>;
};
uart0: uart@4006A000 {
compatible = "nxp,kinetis-lpsci";
reg = <0x4006A000 0xc>;
interrupts = <12 0>;
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>;
label = "UART_0";
status = "disabled";

25
dts/arm/nxp/nxp_kw2xd.dtsi
View file

@ -1,4 +1,5 @@
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/kinetis_sim.h>
#include <dt-bindings/i2c/i2c.h>
/ {
@ -43,15 +44,16 @@
};
sim: sim@40047000 {
compatible = "nxp,k64f-sim";
compatible = "nxp,kinetis-sim";
reg = <0x40047000 0x1060>;
label = "SIM";
clk-divider-core = <1>;
clk-divider-bus = <1>;
clk-divider-flash = <2>;
clock-controller;
#clock-cells = <2>;
#clocks-cells = <3>;
};
flash-controller@4001f000 {
@ -74,6 +76,7 @@
#size-cells = <0>;
reg = <0x40066000 0x1000>;
interrupts = <24 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
label = "I2C_0";
status = "disabled";
};
@ -85,6 +88,7 @@
#size-cells = <0>;
reg = <0x40067000 0x1000>;
interrupts = <25 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
label = "I2C_1";
status = "disabled";
};
@ -94,6 +98,7 @@
reg = <0x4006a000 0x1000>;
interrupts = <31 0>, <32 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>;
label = "UART_0";
pinctrl-0 = <&uart0_default>;
@ -107,6 +112,7 @@
reg = <0x4006b000 0x1000>;
interrupts = <33 0>, <34 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 11>;
label = "UART_1";
status = "disabled";
@ -117,6 +123,7 @@
reg = <0x4006c000 0x1000>;
interrupts = <35 0>, <36 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 12>;
label = "UART_2";
pinctrl-0 = <&uart2_default>;
@ -128,7 +135,7 @@
pinmux_a: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x40049000 0xd0>;
clocks = <&sim 0x1038 9>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
uart0_default: uart0_default {
rx-tx {
@ -141,7 +148,7 @@
pinmux_b: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004a000 0xd0>;
clocks = <&sim 0x1038 10>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
spi1_default: spi1_default {
miso-mosi-clk {
@ -154,13 +161,13 @@
pinmux_c: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004b000 0xd0>;
clocks = <&sim 0x1038 11>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
};
pinmux_d: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004c000 0xd0>;
clocks = <&sim 0x1038 12>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
uart2_default: uart2_default {
rx-tx {
@ -173,7 +180,7 @@
pinmux_e: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004d000 0xd0>;
clocks = <&sim 0x1038 13>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
};
gpioa: gpio@400ff000 {
@ -225,7 +232,7 @@
compatible = "nxp,k64f-spi";
reg = <0x4002c000 0x88>;
interrupts = <26 0>;
clocks = <&sim 0x103C 12>; /* clk gate */
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>;
status = "disabled";
};
@ -233,7 +240,7 @@
compatible = "nxp,k64f-spi";
reg = <0x4002d000 0x88>;
interrupts = <27 0>;
clocks = <&sim 0x103C 13>; /* clk gate */
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>;
cs = <&gpiob 10 0>;
pinctrl-0 = <&spi1_default>;

19
dts/arm/nxp/nxp_kw40z.dtsi
View file

@ -1,4 +1,5 @@
#include "armv6-m.dtsi"
#include <dt-bindings/clock/kinetis_sim.h>
#include <dt-bindings/i2c/i2c.h>
/ {
@ -40,11 +41,12 @@
};
sim: sim@40047000 {
compatible = "nxp,kw41z-sim";
compatible = "nxp,kinetis-sim";
reg = <0x40047000 0x1060>;
label = "SIM";
clock-controller;
#clock-cells = <2>;
#clocks-cells = <3>;
};
flash0: flash@0 {
@ -58,6 +60,7 @@
#size-cells = <0>;
reg = <0x40066000 0x1000>;
interrupts = <8 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
label = "I2C_0";
status = "disabled";
};
@ -69,6 +72,7 @@
#size-cells = <0>;
reg = <0x40067000 0x1000>;
interrupts = <9 0>;
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 7>;
label = "I2C_1";
status = "disabled";
};
@ -77,6 +81,7 @@
compatible = "nxp,kinetis-lpuart";
reg = <0x40054000 0x18>;
interrupts = <12 0>;
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1038 20>;
label = "UART_0";
pinctrl-0 = <&lpuart0_default>;
@ -88,7 +93,7 @@
pinmux_a: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x40049000 0xa4>;
clocks = <&sim 0x1038 9>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
spi1_default: spi1_default {
mosi-miso-sck-pcs0 {
@ -101,13 +106,13 @@
pinmux_b: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004a000 0xa4>;
clocks = <&sim 0x1038 10>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
};
pinmux_c: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004b000 0xa4>;
clocks = <&sim 0x1038 11>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
lpuart0_default: lpuart0_default {
rx-tx {
@ -166,7 +171,7 @@
compatible = "nxp,kw41z-spi";
reg = <0x4002c000 0x9C>;
interrupts = <10 0>;
clocks = <&sim 0x103C 12>; /* clk gate */
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>;
cs = <&gpiob 18 0>, <&gpiob 17 0>;
pinctrl-0 = <&spi0_default>;
@ -177,7 +182,7 @@
compatible = "nxp,kw41z-spi";
reg = <0x4002d000 0x9C>;
interrupts = <29 0>;
clocks = <&sim 0x103C 13>; /* clk gate */
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>;
status = "disabled";
};

19
dts/arm/nxp/nxp_kw41z.dtsi
View file

@ -1,4 +1,5 @@
#include <arm/armv6-m.dtsi>
#include <dt-bindings/clock/kinetis_sim.h>
#include <dt-bindings/i2c/i2c.h>
/ {
@ -40,11 +41,12 @@
};
sim: sim@40047000 {
compatible = "nxp,kw41z-sim";
compatible = "nxp,kinetis-sim";
reg = <0x40047000 0x1060>;
label = "SIM";
clock-controller;
#clock-cells = <2>;
#clocks-cells = <3>;
};
flash0: flash@0 {
@ -58,6 +60,7 @@
#size-cells = <0>;
reg = <0x40066000 0x1000>;
interrupts = <8 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
label = "I2C_0";
status = "disabled";
};
@ -69,6 +72,7 @@
#size-cells = <0>;
reg = <0x40067000 0x1000>;
interrupts = <9 0>;
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 7>;
label = "I2C_1";
status = "disabled";
};
@ -77,6 +81,7 @@
compatible = "nxp,kinetis-lpuart";
reg = <0x40054000 0x18>;
interrupts = <12 0>;
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1038 20>;
label = "UART_0";
pinctrl-0 = <&lpuart0_default>;
@ -88,7 +93,7 @@
pinmux_a: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x40049000 0xa4>;
clocks = <&sim 0x1038 9>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
spi1_default: spi1_default {
mosi-miso-sck-pcs0 {
@ -101,13 +106,13 @@
pinmux_b: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004a000 0xa4>;
clocks = <&sim 0x1038 10>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
};
pinmux_c: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004b000 0xa4>;
clocks = <&sim 0x1038 11>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
lpuart0_default: lpuart0_default {
rx-tx {
@ -166,7 +171,7 @@
compatible = "nxp,kw41z-spi";
reg = <0x4002c000 0x9C>;
interrupts = <10 0>;
clocks = <&sim 0x103C 12>; /* clk gate */
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>;
cs = <&gpiob 18 0>, <&gpiob 17 0>;
pinctrl-0 = <&spi0_default>;
@ -177,7 +182,7 @@
compatible = "nxp,kw41z-spi";
reg = <0x4002d000 0x9C>;
interrupts = <29 0>;
clocks = <&sim 0x103C 13>; /* clk gate */
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>;
status = "disabled";
};

11
dts/arm/usb_kw24d512.fixup
View file

@ -6,6 +6,8 @@
#define CONFIG_UART_MCUX_0_IRQ_ERROR_PRI NXP_KINETIS_UART_4006A000_IRQ_ERROR_PRIORITY
#define CONFIG_UART_MCUX_0_IRQ_STATUS NXP_KINETIS_UART_4006A000_IRQ_STATUS
#define CONFIG_UART_MCUX_0_IRQ_STATUS_PRI NXP_KINETIS_UART_4006A000_IRQ_STATUS_PRIORITY
#define CONFIG_UART_MCUX_0_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_0_CLOCK_SUBSYS NXP_KINETIS_UART_4006A000_SIM_CLK_NAME_0
#define CONFIG_UART_MCUX_1_BAUD_RATE NXP_KINETIS_UART_4006B000_CURRENT_SPEED
#define CONFIG_UART_MCUX_1_NAME NXP_KINETIS_UART_4006B000_LABEL
@ -13,6 +15,8 @@
#define CONFIG_UART_MCUX_1_IRQ_ERROR_PRI NXP_KINETIS_UART_4006B000_IRQ_ERROR_PRIORITY
#define CONFIG_UART_MCUX_1_IRQ_STATUS NXP_KINETIS_UART_4006B000_IRQ_STATUS
#define CONFIG_UART_MCUX_1_IRQ_STATUS_PRI NXP_KINETIS_UART_4006B000_IRQ_STATUS_PRIORITY
#define CONFIG_UART_MCUX_1_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_1_CLOCK_SUBSYS NXP_KINETIS_UART_4006B000_SIM_CLK_NAME_0
#define CONFIG_UART_MCUX_2_BAUD_RATE NXP_KINETIS_UART_4006C000_CURRENT_SPEED
#define CONFIG_UART_MCUX_2_NAME NXP_KINETIS_UART_4006C000_LABEL
@ -20,6 +24,8 @@
#define CONFIG_UART_MCUX_2_IRQ_ERROR_PRI NXP_KINETIS_UART_4006C000_IRQ_ERROR_PRIORITY
#define CONFIG_UART_MCUX_2_IRQ_STATUS NXP_KINETIS_UART_4006C000_IRQ_STATUS
#define CONFIG_UART_MCUX_2_IRQ_STATUS_PRI NXP_KINETIS_UART_4006C000_IRQ_STATUS_PRIORITY
#define CONFIG_UART_MCUX_2_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_2_CLOCK_SUBSYS NXP_KINETIS_UART_4006C000_SIM_CLK_NAME_0
#define CONFIG_UART_MCUX_3_BAUD_RATE NXP_KINETIS_UART_4006D000_CURRENT_SPEED
#define CONFIG_UART_MCUX_3_NAME NXP_KINETIS_UART_4006D000_LABEL
@ -27,6 +33,8 @@
#define CONFIG_UART_MCUX_3_IRQ_ERROR_PRI NXP_KINETIS_UART_4006D000_IRQ_ERROR_PRIORITY
#define CONFIG_UART_MCUX_3_IRQ_STATUS NXP_KINETIS_UART_4006D000_IRQ_STATUS
#define CONFIG_UART_MCUX_3_IRQ_STATUS_PRI NXP_KINETIS_UART_4006D000_IRQ_STATUS_PRIORITY
#define CONFIG_UART_MCUX_3_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_UART_MCUX_3_CLOCK_SUBSYS NXP_KINETIS_UART_4006D000_SIM_CLK_NAME_0
#define CONFIG_I2C_0_NAME NXP_KINETIS_I2C_40066000_LABEL
#define CONFIG_I2C_MCUX_0_BASE_ADDRESS NXP_KINETIS_I2C_40066000_BASE_ADDRESS_0
@ -43,3 +51,6 @@
#define CONFIG_FTM_1_IRQ NXP_KINETIS_FTM_40039000_IRQ_0
#define CONFIG_FTM_1_IRQ_PRI NXP_KINETIS_FTM_40039000_IRQ_0_PRIORITY
#define CONFIG_FTM_1_NAME NXP_KINETIS_FTM_40039000_LABEL
#define CONFIG_SIM_BASE_ADDRESS NXP_KINETIS_SIM_40047000_BASE_ADDRESS_0
#define CONFIG_SIM_NAME NXP_KINETIS_SIM_40047000_LABEL

26
dts/arm/yaml/nxp,k64f-sim.yaml
View file

@ -1,26 +0,0 @@
---
title: K64 System Integration Module (SIM)
version: 0.1
description: >
This is a representation of the K64 SIM IP node
properties:
- compatible:
type: string
category: required
description: compatible strings
constraint: "nxp,k64f-sim"
- reg:
type: int
description: mmio register space
generation: define
category: required
cell_string: SIM_CLK
"#cells":
- offset
- bits
...

39
dts/arm/yaml/nxp,kinetis-sim.yaml Normal file
View file

@ -0,0 +1,39 @@
#
# Copyright (c) 2017, NXP
#
# SPDX-License-Identifier: Apache-2.0
#
---
title: Kinetis System Integration Module (SIM)
id: nxp,kinetis-sim
version: 0.1
description: >
This is a representation of the Kinetis SIM IP node
properties:
- compatible:
type: string
category: required
description: compatible strings
constraint: "nxp,kinetis-sim"
- reg:
type: int
description: mmio register space
generation: define
category: required
- label:
type: string
category: required
description: Human readable string describing the device (used by Zephyr for API name)
generation: define
cell_string: SIM_CLK
"#cells":
- name
- offset
- bits
...

14
include/dt-bindings/clock/kinetis_sim.h Normal file
View file

@ -0,0 +1,14 @@
/*
* Copyright (c) 2017, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __KINETIS_SIM_H
#define __KINETIS_SIM_H
#define KINETIS_SIM_CORESYS_CLK 0
#define KINETIS_SIM_PLATFORM_CLK 1
#define KINETIS_SIM_BUS_CLK 2
#endif /* __KINETIS_SIM_H */