dts: gpio: create gpio dt-bingings and inlude in stm32 dtsi files
Create a dt-bindings/gpio.h file. Bindings definitions are extracted from existing gpio.h. gpio dt-bindings file is required because existing gpio.h file could not be parsed by dts parser. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou
Kumar Gala
parent
2b4cb5a7ad
commit
4fe3a9776f
7 changed files with 187 additions and 164 deletions
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@ -9,6 +9,7 @@
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#include <st/mem.h>
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#include <dt-bindings/clock/stm32_clock.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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@ -9,6 +9,7 @@
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#include <st/mem.h>
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#include <dt-bindings/clock/stm32_clock.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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@ -9,6 +9,7 @@
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#include <st/mem.h>
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#include <dt-bindings/clock/stm32_clock.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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@ -9,6 +9,7 @@
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#include <st/mem.h>
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#include <dt-bindings/clock/stm32_clock.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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@ -10,6 +10,7 @@
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#include <st/mem.h>
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#include <dt-bindings/clock/stm32_clock.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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181
include/dt-bindings/gpio/gpio.h
Normal file
181
include/dt-bindings/gpio/gpio.h
Normal file
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@ -0,0 +1,181 @@
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/*
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* Copyright (c) 2018 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __DT_BINDINGS_GPIO_GPIO_H
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#define __DT_BINDINGS_GPIO_GPIO_H
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/**
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* @name GPIO direction flags
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* The `GPIO_DIR_*` flags are used with `gpio_pin_configure` or `gpio_port_configure`,
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* to specify whether a GPIO pin will be used for input or output.
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* @{
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*/
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/** GPIO pin to be input. */
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#define GPIO_DIR_IN (0 << 0)
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/** GPIO pin to be output. */
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#define GPIO_DIR_OUT (1 << 0)
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/** @cond INTERNAL_HIDDEN */
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#define GPIO_DIR_MASK 0x1
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/** @endcond */
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/** @} */
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/**
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* @name GPIO interrupt flags
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* The `GPIO_INT_*` flags are used with `gpio_pin_configure` or `gpio_port_configure`,
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* to specify how input GPIO pins will trigger interrupts.
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* @{
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*/
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/** GPIO pin to trigger interrupt. */
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#define GPIO_INT (1 << 1)
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/** GPIO pin trigger on level low or falling edge. */
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#define GPIO_INT_ACTIVE_LOW (0 << 2)
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/** GPIO pin trigger on level high or rising edge. */
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#define GPIO_INT_ACTIVE_HIGH (1 << 2)
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/** GPIO pin trigger to be synchronized to clock pulses. */
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#define GPIO_INT_CLOCK_SYNC (1 << 3)
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/** Enable GPIO pin debounce. */
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#define GPIO_INT_DEBOUNCE (1 << 4)
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/** Do Level trigger. */
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#define GPIO_INT_LEVEL (0 << 5)
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/** Do Edge trigger. */
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#define GPIO_INT_EDGE (1 << 5)
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/** Interrupt triggers on both rising and falling edge. */
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#define GPIO_INT_DOUBLE_EDGE (1 << 6)
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/** @} */
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/**
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* @name GPIO polarity flags
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* The `GPIO_POL_*` flags are used with `gpio_pin_configure` or `gpio_port_configure`,
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* to specify the polarity of a GPIO pin.
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* @{
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*/
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/** @cond INTERNAL_HIDDEN */
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#define GPIO_POL_POS 7
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/** @endcond */
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/** GPIO pin polarity is normal. */
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#define GPIO_POL_NORMAL (0 << GPIO_POL_POS)
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/** GPIO pin polarity is inverted. */
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#define GPIO_POL_INV (1 << GPIO_POL_POS)
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/** @cond INTERNAL_HIDDEN */
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#define GPIO_POL_MASK (1 << GPIO_POL_POS)
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/** @endcond */
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/** @} */
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/**
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* @name GPIO pull flags
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* The `GPIO_PUD_*` flags are used with `gpio_pin_configure` or `gpio_port_configure`,
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* to specify the pull-up or pull-down electrical configuration of a GPIO pin.
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* @{
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*/
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/** @cond INTERNAL_HIDDEN */
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#define GPIO_PUD_POS 8
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/** @endcond */
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/** Pin is neither pull-up nor pull-down. */
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#define GPIO_PUD_NORMAL (0 << GPIO_PUD_POS)
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/** Enable GPIO pin pull-up. */
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#define GPIO_PUD_PULL_UP (1 << GPIO_PUD_POS)
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/** Enable GPIO pin pull-down. */
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#define GPIO_PUD_PULL_DOWN (2 << GPIO_PUD_POS)
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/** @cond INTERNAL_HIDDEN */
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#define GPIO_PUD_MASK (3 << GPIO_PUD_POS)
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/** @endcond */
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/** @} */
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/**
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* @name GPIO drive strength flags
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* The `GPIO_DS_*` flags are used with `gpio_pin_configure` or `gpio_port_configure`,
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* to specify the drive strength configuration of a GPIO pin.
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*
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* The drive strength of individual pins can be configured
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* independently for when the pin output is low and high.
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*
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* The `GPIO_DS_*_LOW` enumerations define the drive strength of a pin
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* when output is low.
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* The `GPIO_DS_*_HIGH` enumerations define the drive strength of a pin
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* when output is high.
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*
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* The `DISCONNECT` drive strength indicates that the pin is placed in a
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* high impedance state and not driven, this option is used to
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* configure hardware that supports a open collector drive mode.
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*
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* The interface supports two different drive strengths:
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* `DFLT` - The lowest drive strength supported by the HW
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* `ALT` - The highest drive strength supported by the HW
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*
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* On hardware that supports only one standard drive strength, both
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* `DFLT` and `ALT` have the same behavior.
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*
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* On hardware that does not support a disconnect mode, `DISCONNECT`
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* will behave the same as `DFLT`.
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* @{
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*/
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/** @cond INTERNAL_HIDDEN */
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#define GPIO_DS_LOW_POS 12
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#define GPIO_DS_LOW_MASK (0x3 << GPIO_DS_LOW_POS)
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/** @endcond */
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/** Default drive strength standard when GPIO pin output is low.
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*/
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#define GPIO_DS_DFLT_LOW (0x0 << GPIO_DS_LOW_POS)
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/** Alternative drive strength when GPIO pin output is low.
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* For hardware that does not support configurable drive strength
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* use the default drive strength.
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*/
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#define GPIO_DS_ALT_LOW (0x1 << GPIO_DS_LOW_POS)
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/** Disconnect pin when GPIO pin output is low.
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* For hardware that does not support disconnect use the default
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* drive strength.
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*/
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#define GPIO_DS_DISCONNECT_LOW (0x3 << GPIO_DS_LOW_POS)
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/** @cond INTERNAL_HIDDEN */
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#define GPIO_DS_HIGH_POS 14
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#define GPIO_DS_HIGH_MASK (0x3 << GPIO_DS_HIGH_POS)
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/** @endcond */
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/** Default drive strength when GPIO pin output is high.
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*/
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#define GPIO_DS_DFLT_HIGH (0x0 << GPIO_DS_HIGH_POS)
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/** Alternative drive strength when GPIO pin output is high.
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* For hardware that does not support configurable drive strengths
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* use the default drive strength.
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*/
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#define GPIO_DS_ALT_HIGH (0x1 << GPIO_DS_HIGH_POS)
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/** Disconnect pin when GPIO pin output is high.
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* For hardware that does not support disconnect use the default
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* drive strength.
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*/
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#define GPIO_DS_DISCONNECT_HIGH (0x3 << GPIO_DS_HIGH_POS)
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/** @} */
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#endif /* __DT_BINDINGS_GPIO_GPIO_H */
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165
include/gpio.h
165
include/gpio.h
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@ -19,6 +19,7 @@
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#include <zephyr/types.h>
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#include <stddef.h>
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#include <device.h>
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#include <dt-bindings/gpio/gpio.h>
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#ifdef __cplusplus
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extern "C" {
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@ -35,99 +36,6 @@ extern "C" {
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#define GPIO_ACCESS_BY_PIN 0
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#define GPIO_ACCESS_BY_PORT 1
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/** @endcond */
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/**
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* @name GPIO direction flags
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* The `GPIO_DIR_*` flags are used with `gpio_pin_configure` or `gpio_port_configure`,
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* to specify whether a GPIO pin will be used for input or output.
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* @{
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*/
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/** GPIO pin to be input. */
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#define GPIO_DIR_IN (0 << 0)
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/** GPIO pin to be output. */
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#define GPIO_DIR_OUT (1 << 0)
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/** @cond INTERNAL_HIDDEN */
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#define GPIO_DIR_MASK 0x1
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/** @endcond */
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/** @} */
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/**
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* @name GPIO interrupt flags
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* The `GPIO_INT_*` flags are used with `gpio_pin_configure` or `gpio_port_configure`,
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* to specify how input GPIO pins will trigger interrupts.
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* @{
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*/
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/** GPIO pin to trigger interrupt. */
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#define GPIO_INT (1 << 1)
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/** GPIO pin trigger on level low or falling edge. */
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#define GPIO_INT_ACTIVE_LOW (0 << 2)
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/** GPIO pin trigger on level high or rising edge. */
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#define GPIO_INT_ACTIVE_HIGH (1 << 2)
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/** GPIO pin trigger to be synchronized to clock pulses. */
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#define GPIO_INT_CLOCK_SYNC (1 << 3)
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/** Enable GPIO pin debounce. */
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#define GPIO_INT_DEBOUNCE (1 << 4)
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/** Do Level trigger. */
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#define GPIO_INT_LEVEL (0 << 5)
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/** Do Edge trigger. */
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#define GPIO_INT_EDGE (1 << 5)
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/** Interrupt triggers on both rising and falling edge. */
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#define GPIO_INT_DOUBLE_EDGE (1 << 6)
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/** @} */
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/**
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* @name GPIO polarity flags
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* The `GPIO_POL_*` flags are used with `gpio_pin_configure` or `gpio_port_configure`,
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* to specify the polarity of a GPIO pin.
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* @{
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*/
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/** @cond INTERNAL_HIDDEN */
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#define GPIO_POL_POS 7
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/** @endcond */
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/** GPIO pin polarity is normal. */
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#define GPIO_POL_NORMAL (0 << GPIO_POL_POS)
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/** GPIO pin polarity is inverted. */
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#define GPIO_POL_INV (1 << GPIO_POL_POS)
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/** @cond INTERNAL_HIDDEN */
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#define GPIO_POL_MASK (1 << GPIO_POL_POS)
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/** @endcond */
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/** @} */
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/**
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* @name GPIO pull flags
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* The `GPIO_PUD_*` flags are used with `gpio_pin_configure` or `gpio_port_configure`,
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* to specify the pull-up or pull-down electrical configuration of a GPIO pin.
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* @{
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*/
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/** @cond INTERNAL_HIDDEN */
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#define GPIO_PUD_POS 8
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/** @endcond */
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/** Pin is neither pull-up nor pull-down. */
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#define GPIO_PUD_NORMAL (0 << GPIO_PUD_POS)
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/** Enable GPIO pin pull-up. */
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#define GPIO_PUD_PULL_UP (1 << GPIO_PUD_POS)
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/** Enable GPIO pin pull-down. */
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#define GPIO_PUD_PULL_DOWN (2 << GPIO_PUD_POS)
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/** @cond INTERNAL_HIDDEN */
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#define GPIO_PUD_MASK (3 << GPIO_PUD_POS)
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/** @endcond */
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/** @} */
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/**
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@ -142,77 +50,6 @@ extern "C" {
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*/
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#define GPIO_PIN_DISABLE (0 __DEPRECATED_MACRO)
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/**
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* @name GPIO drive strength flags
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* The `GPIO_DS_*` flags are used with `gpio_pin_configure` or `gpio_port_configure`,
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* to specify the drive strength configuration of a GPIO pin.
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*
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* The drive strength of individual pins can be configured
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* independently for when the pin output is low and high.
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*
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* The `GPIO_DS_*_LOW` enumerations define the drive strength of a pin
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* when output is low.
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* The `GPIO_DS_*_HIGH` enumerations define the drive strength of a pin
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* when output is high.
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*
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* The `DISCONNECT` drive strength indicates that the pin is placed in a
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* high impedance state and not driven, this option is used to
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* configure hardware that supports a open collector drive mode.
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*
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* The interface supports two different drive strengths:
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* `DFLT` - The lowest drive strength supported by the HW
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* `ALT` - The highest drive strength supported by the HW
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*
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* On hardware that supports only one standard drive strength, both
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* `DFLT` and `ALT` have the same behavior.
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*
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* On hardware that does not support a disconnect mode, `DISCONNECT`
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* will behave the same as `DFLT`.
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* @{
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*/
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/** @cond INTERNAL_HIDDEN */
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#define GPIO_DS_LOW_POS 12
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#define GPIO_DS_LOW_MASK (0x3 << GPIO_DS_LOW_POS)
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/** @endcond */
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/** Default drive strength standard when GPIO pin output is low.
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*/
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#define GPIO_DS_DFLT_LOW (0x0 << GPIO_DS_LOW_POS)
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/** Alternative drive strength when GPIO pin output is low.
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* For hardware that does not support configurable drive strength
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* use the default drive strength.
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*/
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#define GPIO_DS_ALT_LOW (0x1 << GPIO_DS_LOW_POS)
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/** Disconnect pin when GPIO pin output is low.
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* For hardware that does not support disconnect use the default
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* drive strength.
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*/
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#define GPIO_DS_DISCONNECT_LOW (0x3 << GPIO_DS_LOW_POS)
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/** @cond INTERNAL_HIDDEN */
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#define GPIO_DS_HIGH_POS 14
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#define GPIO_DS_HIGH_MASK (0x3 << GPIO_DS_HIGH_POS)
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/** @endcond */
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/** Default drive strength when GPIO pin output is high.
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*/
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#define GPIO_DS_DFLT_HIGH (0x0 << GPIO_DS_HIGH_POS)
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/** Alternative drive strength when GPIO pin output is high.
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* For hardware that does not support configurable drive strengths
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* use the default drive strength.
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*/
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#define GPIO_DS_ALT_HIGH (0x1 << GPIO_DS_HIGH_POS)
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/** Disconnect pin when GPIO pin output is high.
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* For hardware that does not support disconnect use the default
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* drive strength.
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*/
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#define GPIO_DS_DISCONNECT_HIGH (0x3 << GPIO_DS_HIGH_POS)
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/** @} */
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struct gpio_callback;
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