soc: nordic: Add support for nRF52833
This commit adds basic support for nRF52833 SoC. Changes affect introducing: - architecuture files (dtsi) - configuration of nrfx drivers - adaptation of inclusions based on chosen SoC - configuration of NFCT_PINS_AS_GPIOS depends on HAS_HW_NRF_NFCT. Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
This commit is contained in:
Emil Obalski
Kumar Gala
parent
5c711bd4ba
commit
3747fd0a68
5 changed files with 515 additions and 2 deletions
392
dts/arm/nordic/nrf52833.dtsi
Normal file
392
dts/arm/nordic/nrf52833.dtsi
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@ -0,0 +1,392 @@
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/*
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* Copyright (c) 2019 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "nrf5_common.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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aliases {
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i2c-0 = &i2c0;
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i2c-1 = &i2c1;
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spi-0 = &spi0;
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spi-1 = &spi1;
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spi-2 = &spi2;
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spi-3 = &spi3;
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uart-0 = &uart0;
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uart-1 = &uart1;
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adc-0 = &adc;
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gpio-0 = &gpio0;
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gpio-1 = &gpio1;
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gpiote-0 = &gpiote;
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wdt-0 = &wdt;
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usbd-0 = &usbd;
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pwm-0 = &pwm0;
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pwm-1 = &pwm1;
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pwm-2 = &pwm2;
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pwm-3 = &pwm3;
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qdec-0 = &qdec;
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rtc-0 = &rtc0;
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rtc-1 = &rtc1;
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rtc-2 = &rtc2;
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timer-0 = &timer0;
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timer-1 = &timer1;
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timer-2 = &timer2;
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timer-3 = &timer3;
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timer-4 = &timer4;
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};
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soc {
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flash-controller@4001e000 {
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compatible = "nordic,nrf52-flash-controller";
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reg = <0x4001e000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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label="NRF_FLASH_DRV_NAME";
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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label = "NRF_FLASH";
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erase-block-size = <4096>;
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write-block-size = <4>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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adc: adc@40007000 {
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compatible = "nordic,nrf-saadc";
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reg = <0x40007000 0x1000>;
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interrupts = <7 1>;
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status = "disabled";
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label = "ADC_0";
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#io-channel-cells = <1>;
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};
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clock: clock@40000000 {
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compatible = "nordic,nrf-clock";
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reg = <0x40000000 0x1000>;
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interrupts = <0 1>;
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status = "okay";
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label = "CLOCK";
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};
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uart0: uart@40002000 {
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/* uart can be either UART or UARTE, for the user to pick */
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/* compatible = "nordic,nrf-uarte" or "nordic,nrf-uart"; */
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reg = <0x40002000 0x1000>;
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interrupts = <2 1>;
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status = "disabled";
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label = "UART_0";
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};
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uart1: uart@40028000 {
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compatible = "nordic,nrf-uarte";
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reg = <0x40028000 0x1000>;
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interrupts = <40 1>;
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status = "disabled";
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label = "UART_1";
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};
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gpiote: gpiote@40006000 {
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compatible = "nordic,nrf-gpiote";
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reg = <0x40006000 0x1000>;
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interrupts = <6 5>;
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status = "disabled";
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label = "GPIOTE_0";
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};
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gpio0: gpio@50000000 {
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compatible = "nordic,nrf-gpio";
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gpio-controller;
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reg = <0x50000000 0x200
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0x50000500 0x300>;
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#gpio-cells = <2>;
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label = "GPIO_0";
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status = "disabled";
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};
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gpio1: gpio@50000300 {
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compatible = "nordic,nrf-gpio";
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gpio-controller;
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reg = <0x50000300 0x200
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0x50000800 0x300>;
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#gpio-cells = <2>;
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label = "GPIO_1";
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status = "disabled";
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};
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i2c0: i2c@40003000 {
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/*
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* This i2c node can be TWI, TWIM, or TWIS,
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* for the user to pick:
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* compatible = "nordic,nrf-twi" or
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* "nordic,nrf-twim" or
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* "nordic,nrf-twis".
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*/
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003000 0x1000>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <3 1>;
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status = "disabled";
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label = "I2C_0";
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};
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i2c1: i2c@40004000 {
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/*
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* This i2c node can be TWI, TWIM, or TWIS,
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* for the user to pick:
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* compatible = "nordic,nrf-twi" or
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* "nordic,nrf-twim" or
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* "nordic,nrf-twis".
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*/
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40004000 0x1000>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <4 1>;
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status = "disabled";
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label = "I2C_1";
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};
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pwm0: pwm@4001c000 {
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compatible = "nordic,nrf-pwm";
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reg = <0x4001c000 0x1000>;
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interrupts = <28 1>;
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status = "disabled";
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label = "PWM_0";
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#pwm-cells = <1>;
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};
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pwm1: pwm@40021000 {
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compatible = "nordic,nrf-pwm";
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reg = <0x40021000 0x1000>;
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interrupts = <33 1>;
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status = "disabled";
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label = "PWM_1";
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#pwm-cells = <1>;
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};
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pwm2: pwm@40022000 {
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compatible = "nordic,nrf-pwm";
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reg = <0x40022000 0x1000>;
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interrupts = <34 1>;
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status = "disabled";
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label = "PWM_2";
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#pwm-cells = <1>;
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};
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pwm3: pwm@4002d000 {
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compatible = "nordic,nrf-pwm";
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reg = <0x4002d000 0x1000>;
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interrupts = <45 1>;
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status = "disabled";
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label = "PWM_3";
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#pwm-cells = <1>;
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};
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qdec: qdec@40012000 {
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compatible = "nordic,nrf-qdec";
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reg = <0x40012000 0x1000>;
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interrupts = <18 1>;
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status = "disabled";
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label = "QDEC";
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};
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spi0: spi@40003000 {
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/*
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* This spi node can be SPI, SPIM, or SPIS,
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* for the user to pick:
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* compatible = "nordic,nrf-spi" or
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* "nordic,nrf-spim" or
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* "nordic,nrf-spis".
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*/
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003000 0x1000>;
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interrupts = <3 1>;
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status = "disabled";
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label = "SPI_0";
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};
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spi1: spi@40004000 {
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/*
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* This spi node can be SPI, SPIM, or SPIS,
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* for the user to pick:
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* compatible = "nordic,nrf-spi" or
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* "nordic,nrf-spim" or
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* "nordic,nrf-spis".
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*/
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40004000 0x1000>;
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interrupts = <4 1>;
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status = "disabled";
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label = "SPI_1";
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};
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spi2: spi@40023000 {
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/*
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* This spi node can be SPI, SPIM, or SPIS,
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* for the user to pick:
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* compatible = "nordic,nrf-spi" or
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* "nordic,nrf-spim" or
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* "nordic,nrf-spis".
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*/
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40023000 0x1000>;
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interrupts = <35 1>;
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status = "disabled";
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label = "SPI_2";
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};
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spi3: spi@4002f000 {
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compatible = "nordic,nrf-spim";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4002f000 0x1000>;
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interrupts = <47 1>;
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status = "disabled";
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label = "SPI_3";
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};
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rtc0: rtc@4000b000 {
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compatible = "nordic,nrf-rtc";
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reg = <0x4000b000 0x1000>;
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interrupts = <11 1>;
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status = "okay";
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clock-frequency = <32768>;
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prescaler = <1>;
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label = "RTC_0";
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};
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rtc1: rtc@40011000 {
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compatible = "nordic,nrf-rtc";
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reg = <0x40011000 0x1000>;
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interrupts = <17 1>;
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status = "okay";
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clock-frequency = <32768>;
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prescaler = <1>;
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label = "RTC_1";
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};
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rtc2: rtc@40024000 {
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compatible = "nordic,nrf-rtc";
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reg = <0x40024000 0x1000>;
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interrupts = <36 1>;
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status = "okay";
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clock-frequency = <32768>;
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prescaler = <1>;
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label = "RTC_2";
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};
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timer0: timer@40008000 {
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compatible = "nordic,nrf-timer";
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status = "okay";
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reg = <0x40008000 0x1000>;
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interrupts = <8 1>;
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prescaler = <0>;
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label = "TIMER_0";
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};
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timer1: timer@40009000 {
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compatible = "nordic,nrf-timer";
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status = "okay";
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reg = <0x40009000 0x1000>;
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interrupts = <9 1>;
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prescaler = <0>;
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label = "TIMER_1";
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};
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timer2: timer@4000a000 {
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compatible = "nordic,nrf-timer";
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status = "okay";
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reg = <0x4000a000 0x1000>;
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interrupts = <10 1>;
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prescaler = <0>;
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label = "TIMER_2";
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};
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timer3: timer@4001a000 {
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compatible = "nordic,nrf-timer";
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status = "okay";
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reg = <0x4001a000 0x1000>;
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interrupts = <26 1>;
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prescaler = <0>;
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label = "TIMER_3";
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};
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timer4: timer@4001b000 {
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compatible = "nordic,nrf-timer";
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status = "okay";
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reg = <0x4001b000 0x1000>;
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interrupts = <27 1>;
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prescaler = <0>;
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label = "TIMER_4";
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};
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temp: temp@4000c000 {
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compatible = "nordic,nrf-temp";
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reg = <0x4000c000 0x1000>;
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interrupts = <12 1>;
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status = "okay";
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label = "TEMP_0";
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};
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usbd: usbd@40027000 {
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compatible = "nordic,nrf-usbd";
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reg = <0x40027000 0x1000>;
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interrupts = <39 1>;
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num-bidir-endpoints = <1>;
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num-in-endpoints = <7>;
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num-out-endpoints = <7>;
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num-isoin-endpoints = <1>;
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num-isoout-endpoints = <1>;
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status = "disabled";
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label = "USBD";
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};
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wdt: watchdog@40010000 {
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compatible = "nordic,nrf-watchdog";
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reg = <0x40010000 0x1000>;
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interrupts = <16 1>;
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status = "okay";
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label = "WDT";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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&sw_pwm {
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timer-instance = <2>;
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channel-count = <3>;
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clock-prescaler = <0>;
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ppi-base = <14>;
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gpiote-base = <0>;
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#pwm-cells = <1>;
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};
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22
dts/arm/nordic/nrf52833_qiaa.dtsi
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22
dts/arm/nordic/nrf52833_qiaa.dtsi
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/*
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* Copyright (c) 2019 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <nordic/nrf52833.dtsi>
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&flash0 {
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reg = <0x00000000 DT_SIZE_K(512)>;
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(128)>;
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};
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/ {
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soc {
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compatible = "nordic,nRF52833-QIAA", "nordic,nRF52833", "nordic,nRF52", "simple-bus";
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};
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};
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22
soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QIAA
Normal file
22
soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QIAA
Normal file
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# Kconfig.defconfig.nrf52833 - Nordic Semiconductor nRF52833 MCU
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#
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# Copyright (c) 2019 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_NRF52833_QIAA
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config SOC
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string
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default "nRF52833_QIAA"
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config NUM_IRQS
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int
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default 48
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config NET_CONFIG_IEEE802154_DEV_NAME
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default IEEE802154_NRF5_DRV_NAME
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endif # SOC_NRF52833_QIAA
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@ -155,6 +155,77 @@ config SOC_NRF52832
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select HAS_HW_NRF_UARTE0
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select HAS_HW_NRF_WDT
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config SOC_NRF52833
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depends on SOC_SERIES_NRF52X
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bool
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select CPU_HAS_FPU
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select HAS_HW_NRF_ACL
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select HAS_HW_NRF_CCM
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select HAS_HW_NRF_CLOCK
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select HAS_HW_NRF_COMP
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select HAS_HW_NRF_ECB
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select HAS_HW_NRF_EGU0
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select HAS_HW_NRF_EGU1
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select HAS_HW_NRF_EGU2
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select HAS_HW_NRF_EGU3
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select HAS_HW_NRF_EGU4
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select HAS_HW_NRF_EGU5
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select HAS_HW_NRF_GPIO0
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select HAS_HW_NRF_GPIO1
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select HAS_HW_NRF_GPIOTE
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select HAS_HW_NRF_I2S
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select HAS_HW_NRF_LPCOMP
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select HAS_HW_NRF_MWU
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select HAS_HW_NRF_NFCT
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select HAS_HW_NRF_PDM
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select HAS_HW_NRF_POWER
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select HAS_HW_NRF_PPI
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select HAS_HW_NRF_PWM0
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select HAS_HW_NRF_PWM1
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select HAS_HW_NRF_PWM2
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select HAS_HW_NRF_PWM3
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select HAS_HW_NRF_QDEC
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select HAS_HW_NRF_RADIO_BLE_CODED
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select HAS_HW_NRF_RADIO_IEEE802154
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select HAS_HW_NRF_RNG
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select HAS_HW_NRF_RTC0
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select HAS_HW_NRF_RTC1
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select HAS_HW_NRF_RTC2
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select HAS_HW_NRF_SAADC
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select HAS_HW_NRF_SPI0
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select HAS_HW_NRF_SPI1
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select HAS_HW_NRF_SPI2
|
||||
select HAS_HW_NRF_SPIM0
|
||||
select HAS_HW_NRF_SPIM1
|
||||
select HAS_HW_NRF_SPIM2
|
||||
select HAS_HW_NRF_SPIM3
|
||||
select HAS_HW_NRF_SPIS0
|
||||
select HAS_HW_NRF_SPIS1
|
||||
select HAS_HW_NRF_SPIS2
|
||||
select HAS_HW_NRF_SWI0
|
||||
select HAS_HW_NRF_SWI1
|
||||
select HAS_HW_NRF_SWI2
|
||||
select HAS_HW_NRF_SWI3
|
||||
select HAS_HW_NRF_SWI4
|
||||
select HAS_HW_NRF_SWI5
|
||||
select HAS_HW_NRF_TEMP
|
||||
select HAS_HW_NRF_TIMER0
|
||||
select HAS_HW_NRF_TIMER1
|
||||
select HAS_HW_NRF_TIMER2
|
||||
select HAS_HW_NRF_TIMER3
|
||||
select HAS_HW_NRF_TIMER4
|
||||
select HAS_HW_NRF_TWI0
|
||||
select HAS_HW_NRF_TWI1
|
||||
select HAS_HW_NRF_TWIM0
|
||||
select HAS_HW_NRF_TWIM1
|
||||
select HAS_HW_NRF_TWIS0
|
||||
select HAS_HW_NRF_TWIS1
|
||||
select HAS_HW_NRF_UART0
|
||||
select HAS_HW_NRF_UARTE0
|
||||
select HAS_HW_NRF_UARTE1
|
||||
select HAS_HW_NRF_USBD
|
||||
select HAS_HW_NRF_WDT
|
||||
|
||||
config SOC_NRF52840
|
||||
depends on SOC_SERIES_NRF52X
|
||||
bool
|
||||
|
|
@ -252,6 +323,10 @@ config SOC_NRF52832_QFAB
|
|||
bool "NRF52832_QFAB"
|
||||
select SOC_NRF52832
|
||||
|
||||
config SOC_NRF52833_QIAA
|
||||
bool "NRF52833_QIAA"
|
||||
select SOC_NRF52833
|
||||
|
||||
config SOC_NRF52840_QIAA
|
||||
bool "NRF52840_QIAA"
|
||||
select SOC_NRF52840
|
||||
|
|
@ -265,7 +340,7 @@ config SOC_DCDC_NRF52X
|
|||
|
||||
config NFCT_PINS_AS_GPIOS
|
||||
bool "NFCT pins as GPIOs"
|
||||
depends on SOC_NRF52832 || SOC_NRF52840
|
||||
depends on HAS_HW_NRF_NFCT
|
||||
help
|
||||
P0.9 and P0.10 are usually reserved for NFC. This option switch
|
||||
them to normal GPIO mode. HW enabling happens once in the device
|
||||
|
|
@ -281,5 +356,5 @@ config GPIO_AS_PINRESET
|
|||
|
||||
config NRF_ENABLE_ICACHE
|
||||
bool "Enable the instruction cache (I-Cache)"
|
||||
depends on SOC_NRF52832 || SOC_NRF52840
|
||||
depends on SOC_NRF52832 || SOC_NRF52833 || SOC_NRF52840
|
||||
default y
|
||||
|
|
|
|||
|
|
@ -32,6 +32,8 @@ extern void z_arm_nmi_init(void);
|
|||
#include <system_nrf52811.h>
|
||||
#elif defined(CONFIG_SOC_NRF52832)
|
||||
#include <system_nrf52.h>
|
||||
#elif defined(CONFIG_SOC_NRF52833)
|
||||
#include <system_nrf52833.h>
|
||||
#elif defined(CONFIG_SOC_NRF52840)
|
||||
#include <system_nrf52840.h>
|
||||
#else
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue